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author | Andree Buschmann <AndreeBuschmann@t-online.de> | 2011-02-02 17:43:32 +0000 |
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committer | Andree Buschmann <AndreeBuschmann@t-online.de> | 2011-02-02 17:43:32 +0000 |
commit | 5d849a963e562d1996c20cd72228835276288141 (patch) | |
tree | 8c96a2524f6c1b6d714506a8d012a9c7ded24918 /firmware/target/coldfire/crt0.S | |
parent | 35bcdef1441519bb66a77b675013309ef39e9eec (diff) | |
download | rockbox-5d849a963e562d1996c20cd72228835276288141.tar.gz rockbox-5d849a963e562d1996c20cd72228835276288141.zip |
Clean up multiple definitions of RAM size. Remove -DMEM (make) and MEM (code), use the already defined MEMORYSIZE instead.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29189 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/crt0.S')
-rw-r--r-- | firmware/target/coldfire/crt0.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S index 7734970ff0..e6717710b1 100644 --- a/firmware/target/coldfire/crt0.S +++ b/firmware/target/coldfire/crt0.S @@ -138,7 +138,7 @@ start: /* Set up the DRAM controller. The refresh is based on the 11.2896MHz clock (5.6448MHz bus frequency). We haven't yet started the PLL */ -#if MEM < 32 +#if MEMORYSIZE < 32 move.w #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */ #else move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ @@ -153,7 +153,7 @@ start: In our case this means that we set the base address 16M ahead and use a 64M mask. */ -#if MEM < 32 +#if MEMORYSIZE < 32 move.l #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up, CAS latency 2, Page mode, No refresh yet */ move.l %d0,(0x108,%a0) |