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authorJens Arnold <amiconn@rockbox.org>2006-11-02 20:50:50 +0000
committerJens Arnold <amiconn@rockbox.org>2006-11-02 20:50:50 +0000
commit83aded979f074b6d48cd05db8f7f991e51372e38 (patch)
treeb8bad1edd08bee7d8659cb1bb582fc305a9d70fa /firmware/target/coldfire/iriver/system-iriver.c
parentd86350c9fad03356990e0844f1d35502e35b1d3b (diff)
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H300: (1) Use DMA for LCD updates, with auto-aligned line reads. Speeds up LCD updates by ~ 75% at 11MHz and 45MHz. Only ~ 11% speedup at 124MHz due to (2). (2) Less aggressive LCD transfer timing at 124MHz. With the previous timing, slightly corrupted display contents was reported, and with DMA transfers at least 4 waitstates are needed to make updates work at all. * A table in system-iriver.c shows settings for all integer multiples of the base clock frequency (info for developers, not yet complete).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11418 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iriver/system-iriver.c')
-rw-r--r--firmware/target/coldfire/iriver/system-iriver.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c
index 5f404fb8cf..3517788641 100644
--- a/firmware/target/coldfire/iriver/system-iriver.c
+++ b/firmware/target/coldfire/iriver/system-iriver.c
@@ -24,6 +24,28 @@
#include "timer.h"
#include "pcf50606.h"
+/* Settings for all possible clock frequencies (with properly working timers)
+ *
+ * xxx_REFRESH_TIMER below
+ * system.h, CPUFREQ_xxx_MULT |
+ * | |
+ * V V
+ * Refreshtim. IDECONFIG1/IDECONFIG2
+ * CPUCLK/Hz MULT PLLCR 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait
+ * ---------------------------------------------------------------------------------------
+ * 11289600 1 0x10c00200 4 1 0x0180 0x0180 0x0180 1 0 0
+ * 22579200 2 0x15c4e005 10 4 0x0180 0x0180 0x0180 1 0 0
+ * 33868800 3 0x13c46005 15 7 0x0180 0x0180 0x0180 1 0 0
+ * 45158400 4 0x15c4e001 21 10 0x0580 0x0180 0x0580 1 0 0
+ * 56448000 5 0x12c4e005 26 12 0x0580 0x0980
+ * 67737600 6 0x13c46001 32 15 0x0980 0x0d80
+ * 79027200 7 0x13c52001 37 18 0x0980 0x1180
+ * 90316800 8 0x13c5e001 43 21 0x0d80 0x1580
+ * 101606400 9 0x11c48005 48 23 0x0d80 0x1980
+ * 112896000 10 0x11c4e005 54 26 0x1180 0x1d80
+ * 124185600 11 0x11c56005 59 29 0x1180 0x1180 0x2180 2 1 2
+ */
+
#if MEM < 32
#define MAX_REFRESH_TIMER 59
#define NORMAL_REFRESH_TIMER 21
@@ -61,7 +83,7 @@ void set_cpu_frequency(long frequency)
RECALC_DELAYS(CPUFREQ_MAX);
PLLCR = 0x11c56005;
CSCR0 = 0x00001180; /* Flash: 4 wait states */
- CSCR1 = 0x00000980; /* LCD: 2 wait states */
+ CSCR1 = 0x00001580; /* LCD: 5 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
#endif