summaryrefslogtreecommitdiffstats
path: root/firmware/target/coldfire/iriver/system-iriver.c
diff options
context:
space:
mode:
authorMichael Sevakis <jethead71@rockbox.org>2006-12-08 23:33:22 +0000
committerMichael Sevakis <jethead71@rockbox.org>2006-12-08 23:33:22 +0000
commit9b720239a3a342e03bb6a59026cef7fa8d3b6a8a (patch)
treecdd5f34f572571d4f5abd08336ebf64a25d10d79 /firmware/target/coldfire/iriver/system-iriver.c
parent4ccbcc8071fe0ba105dfce63793aae3890919459 (diff)
downloadrockbox-9b720239a3a342e03bb6a59026cef7fa8d3b6a8a.tar.gz
rockbox-9b720239a3a342e03bb6a59026cef7fa8d3b6a8a.tar.bz2
rockbox-9b720239a3a342e03bb6a59026cef7fa8d3b6a8a.zip
iRiver: Clearing CRSEL bit when using default CPU frequency caused audio chip to run at half frequency when radio screen called cpu_idle_mode(true) and corresponding high end loss after kepress timeout. CRSEL was originally preserved when bypassing PLL. CRSEL shouldn't have any bearing on PSTCLK or SCLK when PLL is bypassed since the dividers are bypassed as well (except for the divX2 for SCLK).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11695 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iriver/system-iriver.c')
-rw-r--r--firmware/target/coldfire/iriver/system-iriver.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c
index 63011969b4..b67a4228b9 100644
--- a/firmware/target/coldfire/iriver/system-iriver.c
+++ b/firmware/target/coldfire/iriver/system-iriver.c
@@ -134,8 +134,8 @@ void set_cpu_frequency(long frequency)
PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
RECALC_DELAYS(CPUFREQ_DEFAULT);
- /* Power down PLL, but keep CLSEL */
- PLLCR = 0x00000200 | (PLLCR & 0x70400000);
+ /* Power down PLL, but keep CRSEL and CLSEL */
+ PLLCR = 0x00800200 | (PLLCR & 0x70400000);
CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362