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authorJonathan Gordon <rockbox@jdgordon.info>2007-02-18 04:57:28 +0000
committerJonathan Gordon <rockbox@jdgordon.info>2007-02-18 04:57:28 +0000
commitac61951452e001da48430d8487521ad32b7a123c (patch)
tree0696d0c278976c9ec51fd6b5adb65429739b0164 /firmware/target/coldfire/iriver/system-iriver.c
parent00d249ab672e2ce5c27ddd35ea7a40f71ec7a426 (diff)
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Do the CONFIG_USBOTG define correctly
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12382 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iriver/system-iriver.c')
-rw-r--r--firmware/target/coldfire/iriver/system-iriver.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c
index 1cb0a502be..32fc44f963 100644
--- a/firmware/target/coldfire/iriver/system-iriver.c
+++ b/firmware/target/coldfire/iriver/system-iriver.c
@@ -85,7 +85,7 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
CSCR0 = 0x00001180; /* Flash: 4 wait states */
CSCR1 = 0x00001580; /* LCD: 5 wait states */
-#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
+#if CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
#endif
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -112,7 +112,7 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x038be025 | (PLLCR & 0x70400000);
CSCR0 = 0x00000580; /* Flash: 1 wait state */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
-#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
+#if CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
#endif
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -139,7 +139,7 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x00800200 | (PLLCR & 0x70400000);
CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
-#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
+#if CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
#endif
DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */