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| author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-07 00:44:55 -0400 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-07 11:42:45 -0400 |
| commit | eb0e41c1ccb0dcf35efa7e1434bb0e35c9df1543 (patch) | |
| tree | 8989f4d1bfe2c24d67d72026f97ec8e0cc11f949 /firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | |
| parent | 62146ed73513ec62b57163d229c6719b9349c640 (diff) | |
| download | rockbox-eb0e41c1ccb0dcf35efa7e1434bb0e35c9df1543.tar.gz rockbox-eb0e41c1ccb0dcf35efa7e1434bb0e35c9df1543.tar.bz2 rockbox-eb0e41c1ccb0dcf35efa7e1434bb0e35c9df1543.zip | |
jz4760: Support dynamic reclocking!
default/low speed is 192 MHz, Max is 576
Downclock PCLK/MCLK/etc to 96MHz to save a bit of juice
Honestly the high speed could be dialed down to, eg 384
as this thing is so bloody fast..
Change-Id: Ie65597c74290f1603e65f69dae8e75b59c8ba0b4
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c')
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c index 0135c1ced9..6862262045 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c @@ -633,14 +633,23 @@ static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) return clkrt; } -static inline void cpm_select_msc_clk(unsigned int rate) +#ifndef HAVE_ADJUSTABLE_CPU_FREQ +#define cpu_frequency __cpm_get_pllout2() +#endif + +void cpm_select_msc_clk(void) { - unsigned int div = __cpm_get_pllout2() / rate; + unsigned int div = cpu_frequency / SD_CLOCK_FAST; + if (div == 0) div = 1; + if (div == __cpm_get_mscdiv()) + return; + REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1); DEBUG("MSCCLK == %x\n", REG_CPM_MSCCDR); + __cpm_enable_pll_change(); } /* Set the MMC clock frequency */ @@ -651,9 +660,8 @@ static void jz_sd_set_clock(const int drive, unsigned int rate) jz_sd_stop_clock(drive); /* select clock source from CPM */ - cpm_select_msc_clk(rate); + cpm_select_msc_clk(); - __cpm_enable_pll_change(); clkrt = jz_sd_calc_clkrt(drive, rate); REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt; |