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authorMaurus Cuelenaere <mcuelenaere@gmail.com>2008-07-17 10:13:56 +0000
committerMaurus Cuelenaere <mcuelenaere@gmail.com>2008-07-17 10:13:56 +0000
commit1f692e5f55a6493f48ae74b56935623f69daefc6 (patch)
tree78e8bc50b3d14a3b72fa75f64609e154ff3f9c8b /firmware/target/mips/ingenic_jz47xx/crt0.S
parentccf4ce98fd6f5fd76c392774181cad8b051a4f01 (diff)
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1) Set svn:keywords where they should've been set
2) Onda VX747 specific changes git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18080 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/crt0.S')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/crt0.S226
1 files changed, 125 insertions, 101 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S
index 43daa2d720..d56bd57f16 100644
--- a/firmware/target/mips/ingenic_jz47xx/crt0.S
+++ b/firmware/target/mips/ingenic_jz47xx/crt0.S
@@ -1,3 +1,24 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
/*
* init.S
*
@@ -21,14 +42,10 @@
.set mips3
- .extern main
+ .extern system_main
.global _start
-#ifdef BOOTLOADER
- .section .init.text,"ax",%progbits
-#else
.section .resetvectors,"ax",%progbits
-#endif
.set noreorder
.set noat
@@ -80,6 +97,15 @@ _init_cache_loop:
ori t0, 2
mtc0 t0, C0_CONFIG
nop
+
+ //----------------------------------------------------
+ // clear BSS section
+ //----------------------------------------------------
+ la t0, _edata
+ la t1, _end
+1: sw zero, 0(t0)
+ bne t0, t1, 1b
+ addiu t0, 4
//----------------------------------------------------
// setup stack, jump to C code
@@ -93,14 +119,12 @@ _init_stack_loop:
bne t0, sp, _init_stack_loop
addiu t0, t0, 4
- la t0, main
+ la t0, system_main
jr t0
nop
-#ifndef BOOTLOADER
.section .vectors,"ax",%progbits
-#endif
.extern exception_handler
.global except_common_entry
.type except_common_entry,@function
@@ -119,57 +143,57 @@ except_common_entry:
exception_handler:
- addiu sp, -0x80 # Add Immediate Unsigned
- sw ra, 0(sp) # Store Word
- sw fp, 4(sp) # Store Word
- sw gp, 8(sp) # Store Word
- sw t9, 0xC(sp) # Store Word
- sw t8, 0x10(sp) # Store Word
- sw s7, 0x14(sp) # Store Word
- sw s6, 0x18(sp) # Store Word
- sw s5, 0x1C(sp) # Store Word
- sw s4, 0x20(sp) # Store Word
- sw s3, 0x24(sp) # Store Word
- sw s2, 0x28(sp) # Store Word
- sw s1, 0x2C(sp) # Store Word
- sw s0, 0x30(sp) # Store Word
- sw t7, 0x34(sp) # Store Word
- sw t6, 0x38(sp) # Store Word
- sw t5, 0x3C(sp) # Store Word
- sw t4, 0x40(sp) # Store Word
- sw t3, 0x44(sp) # Store Word
- sw t2, 0x48(sp) # Store Word
- sw t1, 0x4C(sp) # Store Word
- sw t0, 0x50(sp) # Store Word
- sw a3, 0x54(sp) # Store Word
- sw a2, 0x58(sp) # Store Word
- sw a1, 0x5C(sp) # Store Word
- sw a0, 0x60(sp) # Store Word
- sw v1, 0x64(sp) # Store Word
- sw v0, 0x68(sp) # Store Word
- sw $1, 0x6C(sp) # Store Word
- mflo t0 # Move F LO
- nop
- sw t0, 0x70(sp) # Store Word
- mfhi t0 # Move F HI
- nop
- sw t0, 0x74(sp) # Store Word
+ addiu sp, -0x80
+ sw ra, 0(sp)
+ sw fp, 4(sp)
+ sw gp, 8(sp)
+ sw t9, 0xC(sp)
+ sw t8, 0x10(sp)
+ sw s7, 0x14(sp)
+ sw s6, 0x18(sp)
+ sw s5, 0x1C(sp)
+ sw s4, 0x20(sp)
+ sw s3, 0x24(sp)
+ sw s2, 0x28(sp)
+ sw s1, 0x2C(sp)
+ sw s0, 0x30(sp)
+ sw t7, 0x34(sp)
+ sw t6, 0x38(sp)
+ sw t5, 0x3C(sp)
+ sw t4, 0x40(sp)
+ sw t3, 0x44(sp)
+ sw t2, 0x48(sp)
+ sw t1, 0x4C(sp)
+ sw t0, 0x50(sp)
+ sw a3, 0x54(sp)
+ sw a2, 0x58(sp)
+ sw a1, 0x5C(sp)
+ sw a0, 0x60(sp)
+ sw v1, 0x64(sp)
+ sw v0, 0x68(sp)
+ sw $1, 0x6C(sp)
+ mflo t0 # Move From LO
+ nop
+ sw t0, 0x70(sp)
+ mfhi t0 # Move From HI
+ nop
+ sw t0, 0x74(sp)
mfc0 t0, C0_STATUS # Status register
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sw t0, 0x78(sp) # Store Word
+ sll zero, 1
+ sll zero, 1
+ sll zero, 1
+ sll zero, 1
+ sw t0, 0x78(sp)
mfc0 t0, C0_EPC # Exception Program Counter
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sw t0, 0x7C(sp) # Store Word
- li k1, 0x7C # Load Immediate
+ sll zero, 1
+ sll zero, 1
+ sll zero, 1
+ sll zero, 1
+ sw t0, 0x7C(sp)
+ li k1, 0x7C
mfc0 k0, C0_CAUSE # C0_CAUSE of last exception
- and k0, k1 # AND
- beq zero, k0, _int # Branch on Equal
+ and k0, k1
+ beq zero, k0, _int
nop
la k0, _exception
jr k0
@@ -178,57 +202,57 @@ exception_handler:
.global _int
.type _int,@function
_int:
- jal intr_handler # Jump And Link
- nop
- lw ra, 0(sp) # Load Word
- lw fp, 4(sp) # Load Word
- sw gp, 8(sp) # Store Word
- lw t9, 0xC(sp) # Load Word
- lw t8, 0x10(sp) # Load Word
- lw s7, 0x14(sp) # Load Word
- lw s6, 0x18(sp) # Load Word
- lw s5, 0x1C(sp) # Load Word
- lw s4, 0x20(sp) # Load Word
- lw s3, 0x24(sp) # Load Word
- lw s2, 0x28(sp) # Load Word
- lw s1, 0x2C(sp) # Load Word
- lw s0, 0x30(sp) # Load Word
- lw t7, 0x34(sp) # Load Word
- lw t6, 0x38(sp) # Load Word
- lw t5, 0x3C(sp) # Load Word
- lw t4, 0x40(sp) # Load Word
- lw t3, 0x44(sp) # Load Word
- lw t2, 0x48(sp) # Load Word
- lw t1, 0x4C(sp) # Load Word
- lw t0, 0x50(sp) # Load Word
- lw a3, 0x54(sp) # Load Word
- lw a2, 0x58(sp) # Load Word
- lw a1, 0x5C(sp) # Load Word
- lw a0, 0x60(sp) # Load Word
- lw v1, 0x64(sp) # Load Word
- lw v0, 0x68(sp) # Load Word
- lw v1, 0x6C(sp) # Load Word
- lw k0, 0x70(sp) # Load Word
+ jal intr_handler
+ nop
+ lw ra, 0(sp)
+ lw fp, 4(sp)
+ sw gp, 8(sp)
+ lw t9, 0xC(sp)
+ lw t8, 0x10(sp)
+ lw s7, 0x14(sp)
+ lw s6, 0x18(sp)
+ lw s5, 0x1C(sp)
+ lw s4, 0x20(sp)
+ lw s3, 0x24(sp)
+ lw s2, 0x28(sp)
+ lw s1, 0x2C(sp)
+ lw s0, 0x30(sp)
+ lw t7, 0x34(sp)
+ lw t6, 0x38(sp)
+ lw t5, 0x3C(sp)
+ lw t4, 0x40(sp)
+ lw t3, 0x44(sp)
+ lw t2, 0x48(sp)
+ lw t1, 0x4C(sp)
+ lw t0, 0x50(sp)
+ lw a3, 0x54(sp)
+ lw a2, 0x58(sp)
+ lw a1, 0x5C(sp)
+ lw a0, 0x60(sp)
+ lw v1, 0x64(sp)
+ lw v0, 0x68(sp)
+ lw v1, 0x6C(sp)
+ lw k0, 0x70(sp)
mtlo k0 # Move To LO
nop
- lw k0, 0x74(sp) # Load Word
+ lw k0, 0x74(sp)
mthi k0 # Move To HI
nop
- lw k0, 0x78(sp) # Load Word
+ lw k0, 0x78(sp)
nop
mtc0 k0, C0_STATUS # Status register
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- lw k0, 0x7C(sp) # Load Word
+ sll zero, 1
+ sll zero, 1
+ sll zero, 1
+ sll zero, 1
+ lw k0, 0x7C(sp)
nop
mtc0 k0, C0_EPC # Exception Program Counter
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- sll zero, 1 # Shift Left Logical
- addiu sp, 0x80 # Add Immediate Unsigned
+ sll zero, 1
+ sll zero, 1
+ sll zero, 1
+ sll zero, 1
+ addiu sp, 0x80
eret # Exception Return
nop
@@ -239,8 +263,8 @@ _exception:
move a0, sp
mfc0 a1, C0_CAUSE # C0_CAUSE of last exception
mfc0 a2, C0_EPC # Exception Program Counter
- la k0, except_handler # Load Address
- jr k0 # Jump Register
+ la k0, except_handler
+ jr k0
nop
.set reorder