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authorMaurus Cuelenaere <mcuelenaere@gmail.com>2009-01-21 20:58:33 +0000
committerMaurus Cuelenaere <mcuelenaere@gmail.com>2009-01-21 20:58:33 +0000
commit29b136b82dda3b3170589df62120705b1b954652 (patch)
tree51dd27061fb7a2da2e2cc826bda1ec6dafb9e5b2 /firmware/target/mips/ingenic_jz47xx/system-jz4740.c
parent868a4bdbc3f08a7c9d26a84bb67a5b3e083ffcec (diff)
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Onda VX747:
* Get USB working (it isn't good at writing support though) * Clean up NAND & SD a bit * Other comments/fixes Ingenic Jz4740/MIPS: * Split MMU from system git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19815 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-jz4740.c')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-jz4740.c101
1 files changed, 1 insertions, 100 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
index 033b42214b..9c7f83530f 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
@@ -23,6 +23,7 @@
#include "jz4740.h"
#include "mips.h"
#include "mipsregs.h"
+#include "mmu-mips.h"
#include "panic.h"
#include "system.h"
#include "string.h"
@@ -524,106 +525,6 @@ void dma_cache_wback_inv(unsigned long addr, unsigned long size)
}
}
-#define BARRIER \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " .set reorder \n");
-
-#define DEFAULT_PAGE_SHIFT PL_4K
-#define DEFAULT_PAGE_MASK PM_4K
-#define UNIQUE_ENTRYHI(idx, ps) (A_K0BASE + ((idx) << (ps + 1)))
-#define ASID_MASK M_EntryHiASID
-#define VPN2_SHIFT S_EntryHiVPN2
-#define PFN_SHIFT S_EntryLoPFN
-#define PFN_MASK 0xffffff
-static void local_flush_tlb_all(void)
-{
- unsigned long old_ctx;
- int entry;
- unsigned int old_irq = disable_irq_save();
-
- /* Save old context and create impossible VPN2 value */
- old_ctx = read_c0_entryhi();
- write_c0_entrylo0(0);
- write_c0_entrylo1(0);
- BARRIER;
-
- /* Blast 'em all away. */
- for(entry = 0; entry < 32; entry++)
- {
- /* Make sure all entries differ. */
- write_c0_entryhi(UNIQUE_ENTRYHI(entry, DEFAULT_PAGE_SHIFT));
- write_c0_index(entry);
- BARRIER;
- tlb_write_indexed();
- }
- BARRIER;
- write_c0_entryhi(old_ctx);
-
- restore_irq(old_irq);
-}
-
-static void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
- unsigned long entryhi, unsigned long pagemask)
-{
- unsigned long wired;
- unsigned long old_pagemask;
- unsigned long old_ctx;
- unsigned int old_irq = disable_irq_save();
-
- old_ctx = read_c0_entryhi() & ASID_MASK;
- old_pagemask = read_c0_pagemask();
- wired = read_c0_wired();
- write_c0_wired(wired + 1);
- write_c0_index(wired);
- BARRIER;
- write_c0_pagemask(pagemask);
- write_c0_entryhi(entryhi);
- write_c0_entrylo0(entrylo0);
- write_c0_entrylo1(entrylo1);
- BARRIER;
- tlb_write_indexed();
- BARRIER;
-
- write_c0_entryhi(old_ctx);
- BARRIER;
- write_c0_pagemask(old_pagemask);
- local_flush_tlb_all();
- restore_irq(old_irq);
-}
-
-static void map_address(unsigned long virtual, unsigned long physical, unsigned long length)
-{
- unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT;
- unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT;
- unsigned long entryhi = virtual & ~VPN2_SHIFT;
-
- entry0 |= (M_EntryLoG | M_EntryLoV | (K_CacheAttrC << S_EntryLoC) );
- entry1 |= (M_EntryLoG | M_EntryLoV | (K_CacheAttrC << S_EntryLoC) );
-
- add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK);
-}
-
-
-static void tlb_init(void)
-{
- write_c0_pagemask(DEFAULT_PAGE_MASK);
- write_c0_wired(0);
- write_c0_framemask(0);
-
- local_flush_tlb_all();
-/*
- map_address(0x80000000, 0x80000000, 0x4000);
- map_address(0x80004000, 0x80004000, MEM * 0x100000);
-*/
-}
-
void tlb_refill_handler(void)
{
panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr());