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authorSolomon Peachy <pizza@shaftnet.org>2018-06-28 06:24:26 -0400
committerMichael Giacomelli <giac2000@hotmail.com>2018-07-28 10:56:31 -0400
commit0662793ca0050e823cd1207cc4689a1cba5068bd (patch)
tree08cd2ec59c9044c96b697b5bf8d0640841d044e0 /firmware/target/mips/ingenic_jz47xx/system-target.h
parentb3e2bd619b1b7ea94ef29d32db48e80b347a1990 (diff)
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Add cleaned-up xDuoo X3 support
Cleaned up, rebased, and forward-ported from the xvortex fork. (original credit to vsoftster@gmail.com) Change-Id: Ibcc023a0271ea81e901450a88317708c2683236d Signed-off-by: Solomon Peachy <pizza@shaftnet.org>
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-target.h')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-target.h14
1 files changed, 12 insertions, 2 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index 1c2e7d7173..9720d3a80c 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -25,7 +25,7 @@
#include <inttypes.h>
#include "config.h"
-#include "jz4740.h"
+#include "cpu.h"
#include "mipsregs.h"
#define CACHE_SIZE 16*1024
@@ -35,6 +35,8 @@
/* no optimized byteswap functions implemented for mips, yet */
#define NEED_GENERIC_BYTESWAPS
+#define STORAGE_WANTS_ALIGN
+
/* This one returns the old status */
static inline int set_interrupt_status(int status, int mask)
{
@@ -86,10 +88,18 @@ void mdelay(unsigned int msec);
void dma_enable(void);
void dma_disable(void);
+#if CONFIG_CPU == JZ4732
#define DMA_AIC_TX_CHANNEL 0
#define DMA_NAND_CHANNEL 1
#define DMA_USB_CHANNEL 2
#define DMA_LCD_CHANNEL 3
+#elif CONFIG_CPU == JZ4760B
+#define DMA_AIC_TX_CHANNEL 0
+#define DMA_NAND_CHANNEL 1
+#define DMA_USB_CHANNEL 2
+#define DMA_SD_RX_CHANNEL 3
+#define DMA_SD_TX_CHANNEL 4
+#endif
#define XDMA_CALLBACK(n) DMA ## n
#define DMA_CALLBACK(n) XDMA_CALLBACK(n)
@@ -103,7 +113,7 @@ void dma_disable(void);
*/
static inline void core_sleep(void)
{
-#if CONFIG_CPU == JZ4732
+#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
__cpm_idle_mode();
#endif
asm volatile(".set mips32r2 \n"