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authorMaurus Cuelenaere <mcuelenaere@gmail.com>2008-08-06 20:39:02 +0000
committerMaurus Cuelenaere <mcuelenaere@gmail.com>2008-08-06 20:39:02 +0000
commit88ae9024e4a1fec45e867f6a1f6cbea0ae0455bb (patch)
tree67fd77d2267eeda80987db55692886546a457e59 /firmware/target/mips/ingenic_jz47xx/system-target.h
parent496e1f7e85f929c487eb89f85ff0fc7edfcf3a27 (diff)
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* Add basic (non-working) support for NAND flash
* Add panicf() handling * Add not-yet-enabled dma acceleration * Other (minor) fixes git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18203 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-target.h')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-target.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index c11ad4be1f..f60bcff7c8 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -101,11 +101,13 @@ static inline void restore_interrupt(int status)
#define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff)
#define UNCACHED_ADDRESS(addr) ((unsigned int)(addr) | 0xA0000000)
+#define PHYSADDR(x) ((x) & 0x1fffffff)
void __dcache_writeback_all(void);
void __dcache_invalidate_all(void);
void __icache_invalidate_all(void);
void __flush_dcache_line(unsigned long addr);
+void dma_cache_wback_inv(unsigned long addr, unsigned long size);
void sti(void);
void cli(void);