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authorSolomon Peachy <pizza@shaftnet.org>2020-09-14 20:36:24 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-09-17 11:26:04 -0400
commitec413f7692de3e33254d79a84c46bd036fd27d0a (patch)
treed5853dd677c5d39233a067a9d7f1dc2d3290a8ae /firmware/target/mips/ingenic_jz47xx/system-target.h
parenta66b9088014fd77d08c34fc07a4e701051e1525a (diff)
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jz4760: Heavily rework USB driver to add working DMA support
* DMA Bulk IN (ie our TX) results in sequential transfers 33-68% faster. * DMA Bulk OUT (ie RX) is mostly stripped out due to complete brokenness. * Interrupt and control endpoints remain PIO-driven. Other improvements: 1) Use consistent endpoint references (no magic numbers) 2) Greatly enhanced logging 3) DMA support can be compiled out completely 4) Setting lockswitch will disable all DMA operations at runtime 5) Much more robust error checking and recovery Change-Id: I57b82e655e55ced0dfe289e379b0b61d8fe443b4
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-target.h')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-target.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index 30c1668bf7..9dc1a5c8c8 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -83,6 +83,7 @@ static inline void restore_interrupt(int status)
#define UNCACHED_ADDRESS(addr) ((unsigned int)(addr) | 0xA0000000)
#define UNCACHED_ADDR(x) UNCACHED_ADDRESS((x))
#define PHYSADDR(x) ((x) & 0x1fffffff)
+#define VIRTADDR(x) ((x) | 0xA0000000)
void system_enable_irq(unsigned int irq);
void udelay(unsigned int usec);