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| author | Solomon Peachy <pizza@shaftnet.org> | 2020-10-15 13:22:51 -0400 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2020-10-15 13:30:48 -0400 |
| commit | 0cde20fadb9aeeb8e724d76e51bce7580296621b (patch) | |
| tree | da9695975e4705d39fc4e048e60a9f9a73b82ed3 /firmware/target/mips/ingenic_jz47xx | |
| parent | d544ce46a78c834492ae1116cd1d1e47cb9d8cb0 (diff) | |
| download | rockbox-0cde20fadb9aeeb8e724d76e51bce7580296621b.tar.gz rockbox-0cde20fadb9aeeb8e724d76e51bce7580296621b.zip | |
xduoox3: Disable the DAC's digital de-emphasis filter.
Whether or not this is correct depends on how the source material was
mastered, digitized, and/or encoded. There is no setting appropriate
for everything.
Eventually I'd like to make this configurable, but I'd want to have it
shared with more than one target first.
Change-Id: I20a0eff4b3dc2517c33db49d4f72e85bf81d1ca6
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx')
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/codec-jz4760.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c index b00b3fddef..5adc4232af 100644 --- a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c @@ -203,7 +203,6 @@ void audiohw_set_frequency(int fsel) { unsigned int pll1_speed; unsigned short mclk_div, bclk_div, func_mode; - unsigned char dem = CS4398_DEM_NONE; // bclk is 2,3,4,6,8,12 ONLY // mclk is 1..512 @@ -250,21 +249,18 @@ void audiohw_set_frequency(int fsel) pll1_speed = 426000000/4; mclk_div = 52/4; bclk_div = 4; - dem = CS4398_DEM_32000; func_mode = 0; break; case HW_FREQ_44: // 2.8224 MHz pll1_speed = 508000000 / 3; mclk_div = 45 / 3; bclk_div = 4; - dem = CS4398_DEM_44100; func_mode = 0; break; case HW_FREQ_48: // 3.072 MHz pll1_speed = 516000000/2/3; mclk_div = 42/2/3; bclk_div = 4; - dem = CS4398_DEM_48000; func_mode = 0; break; case HW_FREQ_64: // 4.096 MHz @@ -307,7 +303,7 @@ void audiohw_set_frequency(int fsel) /* 0 = Single-Speed Mode (<50KHz); 1 = Double-Speed Mode (50-100KHz); 2 = Quad-Speed Mode; (100-200KHz) */ - cs4398_write_reg(CS4398_REG_MODECTL, (cs4398_read_reg(CS4398_REG_MODECTL) & ~(CS4398_FM_MASK|CS4398_DEM_MASK)) | func_mode | dem); + cs4398_write_reg(CS4398_REG_MODECTL, (cs4398_read_reg(CS4398_REG_MODECTL) & ~(CS4398_FM_MASK|CS4398_DEM_MASK)) | func_mode | CS4398_DEM_NONE); if (func_mode == 2) cs4398_write_reg(CS4398_REG_MISC, cs4398_read_reg(CS4398_REG_MISC) | CS4398_MCLKDIV2); else |