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authorSolomon Peachy <pizza@shaftnet.org>2020-08-28 11:17:32 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-08-28 15:19:07 +0000
commit4a6d8e91bbb1abf7ae59affb2d5a105b6e481344 (patch)
tree0557047fccef5081bc46a5c282552369ed3c19ff /firmware/target/mips/ingenic_jz47xx
parent77019c2c3c72cd7f0b6e716dd66a6e0d7bb21e04 (diff)
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jz4740: Timer not re-enabled properly
(same fix as g#2703 for the jz4760) Change-Id: Ic6467d9e6085e3057528b6d1a08b7c07e9dceab4
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/timer-jz4740.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c b/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c
index 538547041d..b3f0f71aa3 100644
--- a/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c
@@ -18,7 +18,7 @@
* KIND, either express or implied.
*
****************************************************************************/
-
+
#include "config.h"
#include "jz4740.h"
#include "system.h"
@@ -61,7 +61,7 @@ bool timer_set(long cycles, bool start)
{
__tcu_disable_pwm_output(1);
- __tcu_mask_half_match_irq(1);
+ __tcu_mask_half_match_irq(1);
__tcu_unmask_full_match_irq(1);
/* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */
@@ -78,10 +78,10 @@ bool timer_set(long cycles, bool start)
if(start)
{
system_enable_irq(IRQ_TCU1);
- __tcu_start_counter(1);
}
restore_irq(old_irq);
+ __tcu_start_counter(1);
return true;
}