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authorAidan MacDonald <amachronic@protonmail.com>2021-03-03 17:54:38 +0000
committerSolomon Peachy <pizza@shaftnet.org>2021-03-03 20:50:28 +0000
commit74a3d1f5be2d364a33f37e0ad621538df1bfba4b (patch)
tree8989db6f499d53384645a7a6c6ee84933764f7fd /firmware/target/mips/ingenic_jz47xx
parentf906df017dd7e82f8452cc479373a1b341a02bd9 (diff)
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Fix MIPS cache operations and enable HAVE_CPU_CACHE_ALIGN on MIPS
- The range-based cache operations on MIPS were broken and only worked properly when BOTH the address and size were multiples of the cache line size. If this was not the case, the last cache line of the range would not be touched! Fix is to align start/end pointers to cache lines before iterating. - To my knowledge all MIPS processors have a cache, so I enabled HAVE_CPU_CACHE_ALIGN by default. This also allows mmu-mips.c to use the CACHEALIGN_UP/DOWN macros. - Make jz4760/system-target.h define its cache line size properly. Change-Id: I1fcd04a59791daa233b9699f04d5ac1cc6bacee7
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-target.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index 9dc1a5c8c8..862ec403d2 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -29,7 +29,7 @@
#include "mipsregs.h"
#define CACHE_SIZE 16*1024
-#define CACHE_LINE_SIZE 32
+#define CACHEALIGN_BITS 5
#include "mmu-mips.h"
#define CFG_UART_BASE UART1_BASE /* Base of the UART channel */