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authorSolomon Peachy <pizza@shaftnet.org>2020-08-28 21:45:58 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-09-03 15:34:28 -0400
commit0cb162a76b16d58250a33e817af6a763e89a770a (patch)
treeaf5ac50c1ec59f665e0a4845672a16d758b44953 /firmware/target/mips/mmu-mips.h
parent1ae8213a64c23ac86173b8139e01c7cad350ec6b (diff)
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mips: Heavily rework DMA & caching code
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527) but rebased and heavily updated. Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
Diffstat (limited to 'firmware/target/mips/mmu-mips.h')
-rw-r--r--firmware/target/mips/mmu-mips.h34
1 files changed, 20 insertions, 14 deletions
diff --git a/firmware/target/mips/mmu-mips.h b/firmware/target/mips/mmu-mips.h
index 7e1e36d3f4..f96ddcc28d 100644
--- a/firmware/target/mips/mmu-mips.h
+++ b/firmware/target/mips/mmu-mips.h
@@ -28,19 +28,25 @@ void map_address(unsigned long virtual, unsigned long physical,
unsigned long length, unsigned int cache_flags);
void mmu_init(void);
-#define HAVE_CPUCACHE_INVALIDATE
-//#define HAVE_CPUCACHE_FLUSH
-
-void __idcache_invalidate_all(void);
-void __icache_invalidate_all(void);
-void __dcache_invalidate_all(void);
-void __dcache_writeback_all(void);
-
-void dma_cache_wback_inv(unsigned long addr, unsigned long size);
-
-#define commit_discard_idcache __idcache_invalidate_all
-#define commit_discard_icache __icache_invalidate_all
-#define commit_discard_dcache __dcache_invalidate_all
-#define commit_dcache __dcache_writeback_all
+/* Commits entire DCache */
+void commit_dcache(void);
+/* Commit and discard entire DCache, will do writeback */
+void commit_discard_dcache(void);
+
+/* Write DCache back to RAM for the given range and remove cache lines
+ * from DCache afterwards */
+void commit_discard_dcache_range(const void *base, unsigned int size);
+
+/* Write DCache back to RAM for the given range */
+void commit_dcache_range(const void *base, unsigned int size);
+
+/*
+ * Remove cache lines for the given range from DCache
+ * will *NOT* do write back except for buffer edges not on a line boundary
+ */
+void discard_dcache_range(const void *base, unsigned int size);
+
+/* Discards the entire ICache, and commit+discards the entire DCache */
+void commit_discard_idcache(void);
#endif /* __MMU_MIPS_INCLUDE_H */