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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-04-26 22:57:31 +0100 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-04-28 20:04:10 +0100 |
commit | 20fc9282213b2c50938bc75e8556c8cfa0d1aee7 (patch) | |
tree | 34357e0106df71ab14ef0d5217508b01779e66c8 /firmware/target/mips | |
parent | ed8c977e2fb3c525868411a270a5d57fe0105611 (diff) | |
download | rockbox-20fc9282213b2c50938bc75e8556c8cfa0d1aee7.tar.gz rockbox-20fc9282213b2c50938bc75e8556c8cfa0d1aee7.zip |
x1000: Centralize common definitions, memory layout
Change-Id: I8daad058ae55d4b750b1ae407153e4917de5d095
Diffstat (limited to 'firmware/target/mips')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/app.lds | 35 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c | 4 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/spl.lds | 23 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/system-target.h | 16 |
4 files changed, 25 insertions, 53 deletions
diff --git a/firmware/target/mips/ingenic_x1000/app.lds b/firmware/target/mips/ingenic_x1000/app.lds index 48a2d8d3c5..26b2854728 100644 --- a/firmware/target/mips/ingenic_x1000/app.lds +++ b/firmware/target/mips/ingenic_x1000/app.lds @@ -1,30 +1,21 @@ #include "config.h" +#include "cpu.h" OUTPUT_FORMAT("elf32-littlemips") OUTPUT_ARCH(MIPS) ENTRY(_start) STARTUP(target/mips/ingenic_x1000/crt0.o) -/* Stub area is used for loading new firmware via RoLo */ -#define STUBSIZE 0x4000 -#define SDRAM_ORIG 0x80000000 - -/* IRAM contains stub, DRAM contains main app */ -#define IRAMORIG SDRAM_ORIG -#define IRAMSIZE STUBSIZE -#define DRAMORIG (SDRAM_ORIG + STUBSIZE) -#define DRAMSIZE (MEMORYSIZE * 0x100000 - STUBSIZE) - /* End of the audio buffer, where the codec buffer starts */ -#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE) +#define ENDAUDIOADDR (X1000_DRAM_END - PLUGIN_BUFFER_SIZE - CODEC_SIZE) /* Where the codec buffer ends, and the plugin buffer starts */ #define ENDCODECADDR (ENDAUDIOADDR + CODEC_SIZE) MEMORY { - IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE - DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE + IRAM : ORIGIN = X1000_IRAM_BASE, LENGTH = X1000_IRAM_SIZE + DRAM : ORIGIN = X1000_DRAM_BASE, LENGTH = X1000_DRAM_SIZE } SECTIONS @@ -50,7 +41,7 @@ SECTIONS *(.sdata*); } > DRAM - .iram IRAMORIG: AT (_bssbegin) + .iram X1000_IRAM_BASE: AT (_bssbegin) { _iramstart = .; . = 0x000; /* TLB refill */ @@ -75,10 +66,10 @@ SECTIONS { *(.stack); stackbegin = .; - . += 0x1E00; + . += X1000_STACKSIZE; stackend = .; _irqstackbegin = .; - . += 0x300; + . += X1000_IRQSTACKSIZE; _irqstackend = .; } > IRAM @@ -93,23 +84,17 @@ SECTIONS _end = .; } > DRAM -#ifdef BOOTLOADER - . = ALIGN(4); - loadbuffer = .; - . += 0x100000 * 4; /* Allow 4 MiB for the rockbox binary */ - loadbufferend = .; -#else - .audiobuf : { - . = ALIGN(4); /* XXX might need more alignment here */ + . = ALIGN(4); audiobuffer = .; + loadbuffer = .; } > DRAM + loadbufferend = ENDAUDIOADDR; audiobufend = ENDAUDIOADDR; codecbuf = ENDAUDIOADDR; pluginbuf = ENDCODECADDR; -#endif /DISCARD/ : { diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c index 7f4441c109..bdd0ffc2e0 100644 --- a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c @@ -56,8 +56,8 @@ const struct spl_boot_option spl_boot_options[] = { */ .nand_addr = 0x6800, .nand_size = 0x19800, - .load_addr = 0x80003ff8, /* first 8 bytes are bootloader ID */ - .exec_addr = 0x80004000, + .load_addr = X1000_DRAM_BASE - 8, /* first 8 bytes are bootloader ID */ + .exec_addr = X1000_DRAM_BASE, .cmdline = NULL, }, { diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds index 39b5939a6a..e8bf9d4700 100644 --- a/firmware/target/mips/ingenic_x1000/spl.lds +++ b/firmware/target/mips/ingenic_x1000/spl.lds @@ -1,23 +1,22 @@ #include "config.h" +#include "cpu.h" OUTPUT_FORMAT("elf32-littlemips") OUTPUT_ARCH(MIPS) ENTRY(_start) STARTUP(target/mips/ingenic_x1000/crt0.o) -#define DRAMORIG 0x80000000 -#define DRAMSIZE (MEMORYSIZE * 0x100000) -#define USED_DRAM 16K - -/* TCSM is 16 KiB and is mapped starting at address 0xf4000000. - * - * The SPL is loaded to TCSM + 0x1000. The area below that is stack space. - * The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800. - * The maskrom will jump to that address (via jalr) after loading the SPL. - */ MEMORY { - TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800 - DRAM : ORIGIN = DRAMORIG + DRAMSIZE - USED_DRAM, LENGTH = USED_DRAM + /* First 4k of TCSM is used by mask ROM for stack + variables, + * and the next 2k are occupied by SPL header */ + TCSM : ORIGIN = X1000_TCSM_BASE + 0x1800, + LENGTH = X1000_TCSM_SIZE - 0x1800 + + /* Small area of DRAM is required for NAND bounce buffers, + * though not strictly necessary as ECC isn't really practical + * this early in the boot */ + DRAM : ORIGIN = X1000_DRAM_END - 16K, + LENGTH = 16K } SECTIONS diff --git a/firmware/target/mips/ingenic_x1000/system-target.h b/firmware/target/mips/ingenic_x1000/system-target.h index 13024584d3..1390faf43a 100644 --- a/firmware/target/mips/ingenic_x1000/system-target.h +++ b/firmware/target/mips/ingenic_x1000/system-target.h @@ -22,35 +22,23 @@ #ifndef __SYSTEM_TARGET_H__ #define __SYSTEM_TARGET_H__ -/* For the sake of system.h CACHEALIGN macros. - * We need this to align DMA buffers, etc. - */ -#define CACHEALIGN_BITS 5 -#define CACHE_SIZE (16*1024) - #ifdef DEBUG /* Define this to get CPU idle stats, visible in the debug menu. */ # define X1000_CPUIDLE_STATS #endif -#define OTGBASE 0xb3500000 -#define USB_NUM_ENDPOINTS 9 - +#include "cpu.h" #include "mmu-mips.h" #include "mipsregs.h" #include "mipsr2-endian.h" #include <stdint.h> -/* Get physical address for DMA */ -#define PHYSADDR(addr) (((unsigned long)(addr)) & 0x1fffffff) - -#define HIGHEST_IRQ_LEVEL 0 - /* Rockbox API */ #define enable_irq() set_c0_status(ST0_IE) #define disable_irq() clear_c0_status(ST0_IE) #define disable_irq_save() set_irq_level(0) #define restore_irq(arg) write_c0_status(arg) +#define HIGHEST_IRQ_LEVEL 0 static inline int set_irq_level(int lev) { |