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authorSolomon Peachy <pizza@shaftnet.org>2020-08-29 10:54:45 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-08-29 14:59:46 -0400
commit3dc4f817def3f106abab05db8e8395ff77c3d087 (patch)
treeb80f1c6f3fd46cfe81b0f02296b507c376a2fed5 /firmware/target
parent3867f0b95958a6219ed5b459c22b246fb827efe2 (diff)
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jz4760: Disable dynamic clocking entirely.
Back off to 480MHz [max] clock, bus/mem clock of 120MHz. 576 is unstable on at least one unit, and 528 still glitches. Change-Id: I020e48532524e739f3bfa42bed570381ccd34959
Diffstat (limited to 'firmware/target')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-jz4760.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
index eab3ef64e6..73bd31c72c 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
@@ -451,7 +451,7 @@ static void pll0_init(unsigned int freq)
* DIV should be one of [1, 2, 3, 4, 6, 8]
*/
const int div[2][6] = { { 1, 2, 2, 2, 2, 2 },
- { 1, 6, 6, 6, 6, 6 } };
+ { 1, 4, 4, 4, 4, 4 } };
const int n2FR[9] = {
0, 0, 1, 2, 3, 0, 4, 0, 5
};