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authoramachronic <amachronic@protonmail.com>2021-04-05 13:21:42 +0100
committeramachronic <amachronic@protonmail.com>2021-04-06 17:27:09 +0100
commitb5558c1cf968f0fcff072456408b14f130f29ce3 (patch)
tree333f75446e2e10e1152c22764e9a7f9d7a86ffcf /firmware/target
parent1b314502c838947a4f5b211ebf9814f39c7a3c9f (diff)
downloadrockbox-b5558c1cf968f0fcff072456408b14f130f29ce3.tar.gz
rockbox-b5558c1cf968f0fcff072456408b14f130f29ce3.zip
x1000: place SPL's NAND bounce buffers in DRAM
This frees up 2 KiB in the SPL's memory map, leaving more room for code. Change-Id: I01bbe2ab2905b2773a8b76d8c53e9f3d55bd040f
Diffstat (limited to 'firmware/target')
-rw-r--r--firmware/target/mips/ingenic_x1000/nand-x1000.c14
-rw-r--r--firmware/target/mips/ingenic_x1000/spl.lds14
2 files changed, 22 insertions, 6 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c
index 54a1d11d95..df86bebf4d 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c
@@ -40,11 +40,15 @@
/* Defined by target */
extern const nand_chip_desc target_nand_chip_descs[];
-/* Globals for the driver
- * TODO: get rid of pagebuffer in the SPL to save code size
- */
-static unsigned char pagebuffer[NAND_MAX_PAGE_SIZE] CACHEALIGN_ATTR;
-static unsigned char auxbuffer[NAND_AUX_BUFFER_SIZE] CACHEALIGN_ATTR;
+#ifdef BOOTLOADER_SPL
+# define NANDBUFFER_ATTR __attribute__((section(".sdram"))) CACHEALIGN_ATTR
+#else
+# define NANDBUFFER_ATTR CACHEALIGN_ATTR
+#endif
+
+/* Globals for the driver */
+static unsigned char pagebuffer[NAND_MAX_PAGE_SIZE] NANDBUFFER_ATTR;
+static unsigned char auxbuffer[NAND_AUX_BUFFER_SIZE] NANDBUFFER_ATTR;
static nand_drv nand_driver;
static void nand_drv_reset(nand_drv* d)
diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds
index 2a0b6b3eaa..ab4a2720f3 100644
--- a/firmware/target/mips/ingenic_x1000/spl.lds
+++ b/firmware/target/mips/ingenic_x1000/spl.lds
@@ -5,13 +5,20 @@ OUTPUT_ARCH(MIPS)
ENTRY(_start)
STARTUP(target/mips/ingenic_x1000/crt0.o)
+#define DRAMORIG 0x80000000
+#define DRAMSIZE (MEMORYSIZE * 0x100000)
+#define USED_DRAM 16K
+
/* TCSM is 16 KiB and is mapped starting at address 0xf4000000.
*
* The SPL is loaded to TCSM + 0x1000. The area below that is stack space.
* The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800.
* The maskrom will jump to that address (via jalr) after loading the SPL.
*/
-MEMORY { TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800 }
+MEMORY {
+ TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800
+ DRAM : ORIGIN = DRAMORIG + DRAMSIZE - USED_DRAM, LENGTH = USED_DRAM
+}
SECTIONS
{
@@ -44,4 +51,9 @@ SECTIONS
*(.scommon*);
_bssend = .;
} > TCSM
+
+ .sdram (NOLOAD) :
+ {
+ *(.sdram);
+ } > DRAM
}