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authorRafaël Carré <rafael.carre@gmail.com>2009-06-29 14:29:06 +0000
committerRafaël Carré <rafael.carre@gmail.com>2009-06-29 14:29:06 +0000
commitc34ca87b64b71741327ec2ca7908080427babab0 (patch)
tree2790f01c2fbb9f335d8e64397267cb62fbf3dd7e /firmware/target
parent15a7f5e5e9495667e204cde8852b33587427911f (diff)
downloadrockbox-c34ca87b64b71741327ec2ca7908080427babab0.tar.gz
rockbox-c34ca87b64b71741327ec2ca7908080427babab0.zip
Move coldfire timer code in the target tree
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21555 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target')
-rw-r--r--firmware/target/coldfire/timer-coldfire.c119
-rw-r--r--firmware/target/coldfire/timer-target.h40
2 files changed, 159 insertions, 0 deletions
diff --git a/firmware/target/coldfire/timer-coldfire.c b/firmware/target/coldfire/timer-coldfire.c
new file mode 100644
index 0000000000..ef9fd9ea7a
--- /dev/null
+++ b/firmware/target/coldfire/timer-coldfire.c
@@ -0,0 +1,119 @@
+/***************************************************************************
+* __________ __ ___.
+* Open \______ \ ____ ____ | | _\_ |__ _______ ___
+* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+* \/ \/ \/ \/ \/
+* $Id$
+*
+* Copyright (C) 2005 Jens Arnold
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+* KIND, either express or implied.
+*
+****************************************************************************/
+
+#include <stdlib.h>
+
+#include "config.h"
+#include "system.h"
+#include "cpu.h"
+#include "timer.h"
+#include "timer-target.h"
+
+static int base_prescale;
+
+void TIMER1(void) __attribute__ ((interrupt_handler));
+void TIMER1(void)
+{
+ if (pfn_timer != NULL)
+ pfn_timer();
+ TER1 = 0xff; /* clear all events */
+}
+
+bool __timer_set(long cycles, bool start)
+{
+ int phi = 0; /* bits for the prescaler */
+ int prescale = 1;
+
+ while (cycles > 0x10000)
+ {
+ prescale <<= 1;
+ cycles >>= 1;
+ }
+
+ if (prescale > 4096/CPUFREQ_MAX_MULT)
+ return false;
+
+ if (prescale > 256/CPUFREQ_MAX_MULT)
+ {
+ phi = 0x05; /* prescale sysclk/16, timer enabled */
+ prescale >>= 4;
+ }
+ else
+ phi = 0x03; /* prescale sysclk, timer enabled */
+
+ base_prescale = prescale;
+ prescale *= (cpu_frequency / CPU_FREQ);
+
+ if (start)
+ {
+ if (pfn_unregister != NULL)
+ {
+ pfn_unregister();
+ pfn_unregister = NULL;
+ }
+ phi &= ~1; /* timer disabled at start */
+
+ /* If it is already enabled, writing a 0 to the RST bit will clear
+ the register, so we clear RST explicitly before writing the real
+ data. */
+ TMR1 = 0;
+ }
+
+ /* We are using timer 1 */
+ TMR1 = 0x0018 | (unsigned short)phi | ((unsigned short)(prescale - 1) << 8);
+ TRR1 = (unsigned short)(cycles - 1);
+ if (start || (TCN1 >= TRR1))
+ TCN1 = 0; /* reset the timer */
+ TER1 = 0xff; /* clear all events */
+
+ return true;
+}
+
+bool __timer_start(void)
+{
+ ICR2 = 0x90; /* interrupt on level 4.0 */
+ and_l(~(1<<10), &IMR);
+ TMR1 |= 1; /* start timer */
+ return true;
+}
+
+void __timer_stop(void)
+{
+ TMR1 = 0; /* disable timer 1 */
+ or_l((1<<10), &IMR); /* disable interrupt */
+}
+
+void timers_adjust_prescale(int multiplier, bool enable_irq)
+{
+ /* tick timer */
+ TMR0 = (TMR0 & 0x00ef)
+ | ((unsigned short)(multiplier - 1) << 8)
+ | (enable_irq ? 0x10 : 0);
+
+ if (pfn_timer)
+ {
+ /* user timer */
+ int prescale = base_prescale * multiplier;
+ TMR1 = (TMR1 & 0x00ef)
+ | ((unsigned short)(prescale - 1) << 8)
+ | (enable_irq ? 0x10 : 0);
+ }
+}
diff --git a/firmware/target/coldfire/timer-target.h b/firmware/target/coldfire/timer-target.h
new file mode 100644
index 0000000000..29488887e8
--- /dev/null
+++ b/firmware/target/coldfire/timer-target.h
@@ -0,0 +1,40 @@
+/***************************************************************************
+* __________ __ ___.
+* Open \______ \ ____ ____ | | _\_ |__ _______ ___
+* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+* \/ \/ \/ \/ \/
+* $Id$
+*
+* Copyright (C) 2005 Jens Arnold
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+* KIND, either express or implied.
+*
+****************************************************************************/
+#ifndef TIMER_TARGET_H
+#define TIMER_TARGET_H
+
+bool __timer_set(long cycles, bool start);
+bool __timer_start(void);
+void __timer_stop(void);
+
+/* timer is based on busclk == cpuclk/2 */
+#define TIMER_FREQ (CPU_FREQ/2)
+
+#define __TIMER_SET(cycles, set) \
+ __timer_set(cycles, set)
+
+#define __TIMER_START() \
+ __timer_start()
+
+#define __TIMER_STOP(...) \
+ __timer_stop()
+
+#endif /* TIMER_TARGET_H */