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| author | Amaury Pouly <amaury.pouly@gmail.com> | 2012-05-21 16:28:12 +0200 |
|---|---|---|
| committer | Amaury Pouly <amaury.pouly@gmail.com> | 2012-05-21 16:29:11 +0200 |
| commit | cd7a478ec1a48facc6729bd51aa1016cc7263081 (patch) | |
| tree | c48131ac6b9272ceab393517dbff319e655f2b96 /firmware/target | |
| parent | 0ebfb937aaa073282415e561f8d1f150813a00fd (diff) | |
| download | rockbox-cd7a478ec1a48facc6729bd51aa1016cc7263081.tar.gz rockbox-cd7a478ec1a48facc6729bd51aa1016cc7263081.zip | |
imx233: enable PLL on startup
Implement PLL enabling/disable and unconditionally power the PLL
on startup. This is needed at least on the Zen X-Fi2.
Change-Id: Ib9ddfdeaf973cedded4b3586dd16aa95a61e78ba
Diffstat (limited to 'firmware/target')
| -rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.c | 11 | ||||
| -rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.h | 3 | ||||
| -rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 1 |
3 files changed, 14 insertions, 1 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index 064ee8013b..a5fc706350 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c @@ -43,6 +43,17 @@ void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable) { case CLK_PIX: REG = &HW_CLKCTRL_PIX; break; case CLK_SSP: REG = &HW_CLKCTRL_SSP; break; + case CLK_PLL: + { + if(enable) + { + __REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__POWER; + while(!(HW_CLKCTRL_PLLCTRL1 & HW_CLKCTRL_PLLCTRL1__LOCK)); + } + else + __REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__POWER; + return; + } default: return; } diff --git a/firmware/target/arm/imx233/clkctrl-imx233.h b/firmware/target/arm/imx233/clkctrl-imx233.h index d49e8b2802..c887391602 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.h +++ b/firmware/target/arm/imx233/clkctrl-imx233.h @@ -34,6 +34,7 @@ #define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BM (3 << 20) #define HW_CLKCTRL_PLLCTRL1 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x10)) +#define HW_CLKCTRL_PLLCTRL1__LOCK (1 << 31) #define HW_CLKCTRL_CPU (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x20)) #define HW_CLKCTRL_CPU__DIV_CPU_BP 0 @@ -121,7 +122,7 @@ enum imx233_clock_t CLK_IO, /* freq, frac */ CLK_CPU, /* freq, div, frac, bypass */ CLK_HBUS, /* freq, div, frac */ - CLK_PLL, /* freq */ + CLK_PLL, /* freq, enable */ CLK_XTAL, /* freq */ CLK_EMI, /* freq */ CLK_XBUS, /* freq, div */ diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index 07c29a8644..bcdb47ebaa 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c @@ -100,6 +100,7 @@ void memory_init(void) void system_init(void) { + imx233_clkctrl_enable_clock(CLK_PLL, true); imx233_rtc_init(); imx233_icoll_init(); imx233_pinctrl_init(); |