diff options
| author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-06 22:17:23 -0400 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-07 03:44:01 +0000 |
| commit | e0bb30a1bdf977765d1e891c1bc32bed3fa7c36e (patch) | |
| tree | 8e34e32bb4c34bc68e11cabcf35922ade9b60db0 /firmware/target | |
| parent | f554c7873428018b482e57c6ba9c96e0e67d320c (diff) | |
| download | rockbox-e0bb30a1bdf977765d1e891c1bc32bed3fa7c36e.tar.gz rockbox-e0bb30a1bdf977765d1e891c1bc32bed3fa7c36e.zip | |
xduoox3: Set PLL0 to 480MHz, not 492.
PLL0 Needs to be a multiple of 48MHz for sane USB operation!
(Indeed, "typical" clock for this part is 528, but that seems a
waste of power)
Also fixes a minor bugaboo in the jz4670 usb divisor calculation
that won't matter until we enable reclocking
Change-Id: I40b1fd1ae48871e50885981ccc8b01feb711b9a5
Diffstat (limited to 'firmware/target')
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index 7bbf6d36ae..072bdb49b8 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c @@ -478,7 +478,7 @@ static void pll0_init(unsigned int freq) * Init USB Host clock, pllout2 must be n*48MHz * For JZ4760b UHC - River. */ - usbdiv = (cfcr & CPCCR_PCS) ? CPU_FREQ : (CPU_FREQ / 2); + usbdiv = (cfcr & CPCCR_PCS) ? freq : (freq / 2); REG_CPM_UHCCDR = usbdiv / 48000000 - 1; /* init PLL */ |