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authorTomasz Moń <desowin@gmail.com>2011-12-26 09:45:18 +0000
committerTomasz Moń <desowin@gmail.com>2011-12-26 09:45:18 +0000
commitfdcf5e48e1221ca8575170269dcfd31fd6869152 (patch)
treef597c6b4862465697eb5d8a1274c7c1a48483b2a /firmware/target
parent5dba771d63b26195b24fc5bbd098aff733da2599 (diff)
downloadrockbox-fdcf5e48e1221ca8575170269dcfd31fd6869152.tar.gz
rockbox-fdcf5e48e1221ca8575170269dcfd31fd6869152.zip
Sansa Connect: Set unknown GIOs to state with lowest power consumption. This slightly improves runtime.
Use proper delay for DSP reset and interrupt. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31438 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target')
-rw-r--r--firmware/target/arm/tms320dm320/dsp-dm320.c4
-rw-r--r--firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S4
-rw-r--r--firmware/target/arm/tms320dm320/system-dm320.c13
3 files changed, 17 insertions, 4 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp-dm320.c b/firmware/target/arm/tms320dm320/dsp-dm320.c
index be9f8d8bd9..a8610f703a 100644
--- a/firmware/target/arm/tms320dm320/dsp-dm320.c
+++ b/firmware/target/arm/tms320dm320/dsp-dm320.c
@@ -66,7 +66,7 @@ void dsp_reset(void)
bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8);
/* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */
- nop; nop;
+ udelay(1);
bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8);
/* TODO: Timeout. */
@@ -82,7 +82,7 @@ void dsp_wake(void)
/* The first time you INT0 the DSP, the ROM loader will branch to your RST
handler. Subsequent times, your INT0 handler will get executed. */
bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7);
- nop; nop;
+ udelay(1); /* wait atleast two DSP clocks */
bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7);
restore_irq(old_level);
diff --git a/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S b/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S
index debd2cd2be..a356016fb4 100644
--- a/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S
+++ b/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S
@@ -121,7 +121,9 @@ _clock_setup:
/* IO_CLK_DIV1: Accelerator, SDRAM */
mwh 0x3088C, 0x0102
- /* IO_CLK_DIV2: DSP, MS Clock */
+ /* IO_CLK_DIV2: DSP, MS Clock
+ * OF must be booted with this value
+ */
mwhm 0x3088E, 0x0200
# PLLA &= ~0x1000 (BIC #0x1000)
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c
index dc9c2060c6..a918d99064 100644
--- a/firmware/target/arm/tms320dm320/system-dm320.c
+++ b/firmware/target/arm/tms320dm320/system-dm320.c
@@ -7,6 +7,7 @@
* \/ \/ \/ \/ \/
* $Id$
*
+ * Copyright (C) 2011 by Tomasz Moń
* Copyright (C) 2007 by Karl Kurbjun
*
* This program is free software; you can redistribute it and/or
@@ -311,7 +312,7 @@ void system_init(void)
#endif
{
#ifdef SANSA_CONNECT
- /* Setting AHB divisor to 0 causes MMC/SD interface to lock */
+ /* Setting AHB divisor to 0 increases power consumption */
clock_arm_slow = (1 << 8) | 3;
clock_arm_fast = (1 << 8) | 1;
#else
@@ -379,6 +380,16 @@ void system_init(void)
/* Disable External Memory interface (used for accessing NOR flash) */
bitclr16(&IO_CLK_MOD0, CLK_MOD0_EMIF);
#endif
+
+ /* Unknown GIOs - set them to save power */
+ /* GIO40 - output 0
+ * GIO28 - output 0
+ */
+ IO_GIO_DIR2 &= ~(1 << 8);
+ IO_GIO_BITCLR2 = (1 << 8);
+
+ IO_GIO_DIR1 &= ~(1 << 12);
+ IO_GIO_BITCLR1 = (1 << 12);
#endif
}