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authorLinus Nielsen Feltzing <linus@haxx.se>2006-08-25 11:46:04 +0000
committerLinus Nielsen Feltzing <linus@haxx.se>2006-08-25 11:46:04 +0000
commit07eea493471a774e8281a9d1a8775f854349676c (patch)
treeb016f1fd95c3aed5c5c0ffdf0ba373d97be14a4b /firmware/timer.c
parent798a8c1b7695b0e948e8e4a8f46ec622f403c5f7 (diff)
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Ooops. The TMR reset must only be done when starting the timer.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@10744 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/timer.c')
-rw-r--r--firmware/timer.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/firmware/timer.c b/firmware/timer.c
index fb1a7ffcca..6513d80a25 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -131,12 +131,13 @@ static bool timer_set(long cycles, bool start)
pfn_unregister = NULL;
}
phi &= ~1; /* timer disabled at start */
+
+ /* If it is already enabled, writing a 0 to the RST bit will clear
+ the register, so we clear RST explicitly before writing the real
+ data. */
+ TMR1 = 0;
}
- /* If it is already enabled, writing a 0 to the RST bit will clear the
- register, so we clear RST explicitly before writing the real data. */
- TMR1 = 0;
-
/* We are using timer 1 */
TMR1 = 0x0018 | (unsigned short)phi | ((unsigned short)(prescale - 1) << 8);
TRR1 = (unsigned short)(cycles - 1);