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authorMichael Sevakis <jethead71@rockbox.org>2008-06-03 05:08:24 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-06-03 05:08:24 +0000
commit191320cd0f39a1dd831273f6ad57602d1b2e6cf9 (patch)
treeceedf028763a7855bf1b2caeb11765e7c6dd79af /firmware/timer.c
parent606d9d0c83f8396fa418fa16a23da68aa2e4d784 (diff)
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Rename CPU/COP_INT_CLR to CPU/COP_INT_DIS since it's really a 'write one to disable' register and hasn't anything to do with acknowledging interrupts-- that's handled at the module level.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17683 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/timer.c')
-rw-r--r--firmware/timer.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/timer.c b/firmware/timer.c
index bd9050f872..eefebb38f8 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -201,8 +201,8 @@ static bool timer_set(long cycles, bool start)
pfn_unregister();
pfn_unregister = NULL;
}
- CPU_INT_CLR = TIMER2_MASK;
- COP_INT_CLR = TIMER2_MASK;
+ CPU_INT_DIS = TIMER2_MASK;
+ COP_INT_DIS = TIMER2_MASK;
}
if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
TIMER2_CFG = 0xc0000000 | (cycles - 1); /* enable timer */
@@ -311,8 +311,8 @@ void timer_unregister(void)
or_l((1<<10), &IMR); /* disable interrupt */
#elif defined(CPU_PP)
TIMER2_CFG = 0; /* stop timer 2 */
- CPU_INT_CLR = TIMER2_MASK;
- COP_INT_CLR = TIMER2_MASK;
+ CPU_INT_DIS = TIMER2_MASK;
+ COP_INT_DIS = TIMER2_MASK;
#elif CONFIG_CPU == PNX0101
TIMER1.ctrl &= ~0x80; /* disable timer 1 */
irq_disable_int(IRQ_TIMER1);