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authorTomasz Malesinski <tomal@rockbox.org>2007-03-24 19:26:13 +0000
committerTomasz Malesinski <tomal@rockbox.org>2007-03-24 19:26:13 +0000
commitcd630c9e0a2e0aa259a6e53a5af1369f36984b1c (patch)
tree84bff67d18b47884f1a777eabfb7ba3de7d35c14 /firmware/timer.c
parent7d9ff93b79ef66333669e01d67c7b1736370a346 (diff)
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PNX0101 changes:
Make PNX0101-specific system.c and crt0.S. Add new register names from LPC2880 user manual. Add support for timer. Enable CPU frequency changing. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12904 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/timer.c')
-rw-r--r--firmware/timer.c48
1 files changed, 45 insertions, 3 deletions
diff --git a/firmware/timer.c b/firmware/timer.c
index 849e4ba598..ca23cb890c 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -28,7 +28,7 @@ static void (*pfn_timer)(void) = NULL; /* timer callback */
static void (*pfn_unregister)(void) = NULL; /* unregister callback */
#ifdef CPU_COLDFIRE
static int base_prescale;
-#elif defined CPU_PP
+#elif defined CPU_PP || CONFIG_CPU == PNX0101
static long cycles_new = 0;
#endif
@@ -67,6 +67,24 @@ void TIMER2(void)
cycles_new = 0;
}
}
+#elif CONFIG_CPU == PNX0101
+void TIMER1_ISR(void)
+{
+ if (cycles_new > 0)
+ {
+ TIMER1.load = cycles_new - 1;
+ cycles_new = 0;
+ }
+ if (pfn_timer != NULL)
+ {
+ cycles_new = -1;
+ /* "lock" the variable, in case timer_set_period()
+ * is called within pfn_timer() */
+ pfn_timer();
+ cycles_new = 0;
+ }
+ TIMER1.clr = 1; /* clear the interrupt */
+}
#endif /* CONFIG_CPU */
static bool timer_set(long cycles, bool start)
@@ -85,8 +103,26 @@ static bool timer_set(long cycles, bool start)
}
#endif
-#if CONFIG_CPU == PNX0101 /* TODO: Implement for iFP */
- (void)start;
+#if CONFIG_CPU == PNX0101
+ if (start)
+ {
+ if (pfn_unregister != NULL)
+ {
+ pfn_unregister();
+ pfn_unregister = NULL;
+ }
+ TIMER1.ctrl &= ~0x80; /* disable the counter */
+ TIMER1.ctrl |= 0x40; /* reload after counting down to zero */
+ TIMER1.ctrl &= ~0xc; /* no prescaler */
+ TIMER1.clr = 1; /* clear an interrupt event */
+ }
+ if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
+ { /* enable timer */
+ TIMER1.load = cycles - 1;
+ TIMER1.ctrl |= 0x80; /* enable the counter */
+ }
+ else
+ cycles_new = cycles;
#endif
#if CONFIG_CPU == SH7034
@@ -229,6 +265,9 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
#elif defined(CPU_PP)
/* unmask interrupt source */
CPU_INT_EN = TIMER2_MASK;
+#elif CONFIG_CPU == PNX0101
+ irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
+ irq_enable_int(IRQ_TIMER1);
#endif
return true;
}
@@ -249,6 +288,9 @@ void timer_unregister(void)
#elif defined(CPU_PP)
TIMER2_CFG = 0; /* stop timer 2 */
CPU_INT_CLR = TIMER2_MASK;
+#elif CONFIG_CPU == PNX0101
+ TIMER1.ctrl &= ~0x80; /* disable timer 1 */
+ irq_disable_int(5);
#endif
pfn_timer = NULL;
pfn_unregister = NULL;