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authorCástor Muñoz <cmvidal@gmail.com>2016-02-05 02:02:02 +0100
committerCástor Muñoz <cmvidal@gmail.com>2017-02-09 20:47:16 +0100
commit882921efb64218e9b8cc3a7d9c7308734f9b12f3 (patch)
treefca2e1b77104419156a07c6b6d80fa7af9fa3969 /firmware
parent0d0b163dd15c35a427c8bb2bbd7b906afe9c491d (diff)
downloadrockbox-bootloader_ipod6g_v1.tar.gz
rockbox-bootloader_ipod6g_v1.zip
ipod6g: bootloader v1bootloader_ipod6g_v1
- dual boot - USB mode - battery trap Change-Id: I8586cfeb21ee63f45ab965430725225fdfc4212d
Diffstat (limited to 'firmware')
-rw-r--r--firmware/SOURCES12
-rw-r--r--firmware/export/config.h4
-rw-r--r--firmware/export/config/ipod6g.h13
-rw-r--r--firmware/target/arm/s5l8702/boot.lds54
-rw-r--r--firmware/target/arm/s5l8702/crt0.S67
5 files changed, 118 insertions, 32 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 88e40fa74f..09716be40e 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -1597,12 +1597,12 @@ target/arm/s5l8700/ipodnano2g/piezo-nano2g.c
#ifdef IPOD_6G
target/arm/ipod/button-clickwheel.c
target/arm/s5l8702/ipod6g/storage_ata-ipod6g.c
-target/arm/s5l8702/ipod6g/cscodec-ipod6g.c
target/arm/s5l8702/ipod6g/backlight-ipod6g.c
target/arm/s5l8702/ipod6g/powermgmt-ipod6g.c
target/arm/s5l8702/ipod6g/power-ipod6g.c
target/arm/s5l8702/kernel-s5l8702.c
target/arm/s5l8702/system-s5l8702.c
+target/arm/s5l8702/timer-s5l8702.c
target/arm/s5l8702/gpio-s5l8702.c
target/arm/s5l8702/pl080.c
target/arm/s5l8702/dma-s5l8702.c
@@ -1615,24 +1615,26 @@ target/arm/s5l8702/postmortemstub.S
#endif
target/arm/s5l8702/ipod6g/pmu-ipod6g.c
target/arm/s5l8702/ipod6g/rtc-ipod6g.c
+target/arm/s5l8702/ipod6g/adc-ipod6g.c
+#if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE)
target/arm/s5l8702/usb-s5l8702.c
+#endif
#ifdef HAVE_SERIAL
target/arm/uc870x.c
target/arm/s5l8702/uart-s5l8702.c
target/arm/s5l8702/ipod6g/serial-ipod6g.c
#endif
#ifndef BOOTLOADER
-target/arm/s5l8702/timer-s5l8702.c
target/arm/s5l8702/debug-s5l8702.c
target/arm/s5l8702/pcm-s5l8702.c
target/arm/s5l8702/ipod6g/audio-ipod6g.c
-target/arm/s5l8702/ipod6g/adc-ipod6g.c
+target/arm/s5l8702/ipod6g/cscodec-ipod6g.c
#else
target/arm/s5l8702/spi-s5l8702.c
target/arm/s5l8702/crypto-s5l8702.c
target/arm/s5l8702/nor-s5l8702.c
-#endif
-#endif
+#endif /* BOOTLOADER */
+#endif /* IPOD_6G */
#if CONFIG_CPU == RK27XX
target/arm/rk27xx/audio-rk27xx.c
diff --git a/firmware/export/config.h b/firmware/export/config.h
index e7cfc698df..efad75f1b2 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -872,8 +872,12 @@ Lyre prototype 1 */
#ifdef HAVE_BOOTLOADER_USB_MODE
/* Priority in bootloader is wanted */
#define HAVE_PRIORITY_SCHEDULING
+#if (CONFIG_CPU == S5L8702)
+#define USB_DRIVER_CLOSE
+#else
#define USB_STATUS_BY_EVENT
#define USB_DETECT_BY_REQUEST
+#endif
#if defined(HAVE_USBSTACK) && CONFIG_USBOTG == USBOTG_ARC
#define INCLUDE_TIMEOUT_API
#define USB_DRIVER_CLOSE
diff --git a/firmware/export/config/ipod6g.h b/firmware/export/config/ipod6g.h
index 01934a0cc2..5494cf387a 100644
--- a/firmware/export/config/ipod6g.h
+++ b/firmware/export/config/ipod6g.h
@@ -248,14 +248,27 @@
#define USB_VENDOR_ID 0x05AC
#define USB_PRODUCT_ID 0x1261
#define USB_DEVBSS_ATTR __attribute__((aligned(32)))
+#define HAVE_BOOTLOADER_USB_MODE
+#ifdef BOOTLOADER
+#define USBPOWER_BTN_IGNORE (~0)
+#endif
#define USB_READ_BUFFER_SIZE (1024*24)
+/* Serial */
+#ifdef BOOTLOADER
+#if 0 /* Enable/disable LOGF_SERIAL for bootloader */
+#define HAVE_SERIAL
+#define ROCKBOX_HAS_LOGF
+#define LOGF_SERIAL
+#endif
+#else /* !BOOTLOADER */
#define HAVE_SERIAL
/* Disable iAP when LOGF_SERIAL is enabled to avoid conflicts */
#ifndef LOGF_SERIAL
#define IPOD_ACCESSORY_PROTOCOL
#endif
+#endif
/* Define this if you can switch on/off the accessory power supply */
#define HAVE_ACCESSORY_SUPPLY
diff --git a/firmware/target/arm/s5l8702/boot.lds b/firmware/target/arm/s5l8702/boot.lds
index 2885f77eda..61f23b9c22 100644
--- a/firmware/target/arm/s5l8702/boot.lds
+++ b/firmware/target/arm/s5l8702/boot.lds
@@ -1,5 +1,6 @@
#define ASM
#include "config.h"
+#include "cpu.h"
ENTRY(start)
#ifdef ROCKBOX_LITTLE_ENDIAN
@@ -10,13 +11,11 @@ OUTPUT_FORMAT(elf32-bigarm)
OUTPUT_ARCH(arm)
STARTUP(target/arm/s5l8702/crt0.o)
+#define MAX_LOADSIZE 8M /* reserved for loading Rockbox binary */
+
#ifdef IPOD_NANO2G
#define DRAMORIG 0x08000000 + ((MEMORYSIZE - 1) * 0x100000)
#define DRAMSIZE 0x00100000
-#else
-#define DRAMORIG 0x08000000
-#define DRAMSIZE (DRAM_SIZE - TTB_SIZE)
-#endif
#define IRAMORIG 0x22000000
#define IRAMSIZE 256K
@@ -26,17 +25,47 @@ MEMORY
DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
}
-
#define LOAD_AREA IRAM
+#define VECT_AREA IRAM
+#define BSS_AREA DRAM
+
+#elif defined(IPOD_6G)
+MEMORY
+{
+ DRAM : ORIGIN = DRAM_ORIG, LENGTH = DRAM_SIZE
+ IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE
+
+ /* s5l8702 maps address 0 to ROM, IRAM or DRAM */
+ VECT_AREA : ORIGIN = 0, LENGTH = 1K
+
+ /* IRAM region where loaded IM3 body will be moved and executed,
+ preserving the loaded IM3 header (0x800 bytes) at IRAM1_ORIG */
+ MOVE_AREA : ORIGIN = IRAM1_ORIG + 0x800,
+ LENGTH = IRAM1_SIZE - 0x800
+
+ /* DRAM region for BSS */
+ BSS_AREA : ORIGIN = DRAM_ORIG + MAX_LOADSIZE,
+ LENGTH = DRAM_SIZE - MAX_LOADSIZE - TTB_SIZE
+}
+#define LOAD_AREA MOVE_AREA
+
+#else
+#error No target defined!
+#endif
+
SECTIONS
{
+ _dfuloadaddr = IRAM0_ORIG ;
+ _movestart = LOADADDR(.text) ;
+ _moveend = LOADADDR(.data) + SIZEOF(.data) ;
+
#ifdef NEEDS_INTVECT_COPYING
.intvect : {
_intvectstart = . ;
*(.intvect)
- _intvectend = _newstart ;
- } >IRAM AT> LOAD_AREA
+ _intvectend = _newstart ;
+ } >VECT_AREA AT> LOAD_AREA
_intvectcopy = LOADADDR(.intvect) ;
#endif
@@ -61,10 +90,9 @@ SECTIONS
*(.idata*)
*(.data*)
*(.ncdata*);
- . = ALIGN(0x4);
+ . = ALIGN(0x20); /* align move size */
_dataend = . ;
- } > IRAM AT> LOAD_AREA
- _datacopy = LOADADDR(.data) ;
+ } > LOAD_AREA
.stack (NOLOAD) :
{
@@ -80,7 +108,7 @@ SECTIONS
_fiqstackbegin = .;
. += 0x400;
_fiqstackend = .;
- } > IRAM
+ } > LOAD_AREA
.bss (NOLOAD) : {
_edata = .;
@@ -88,7 +116,7 @@ SECTIONS
*(.ibss*);
*(.ncbss*);
*(COMMON);
- . = ALIGN(0x4);
+ . = ALIGN(0x20); /* align bzero size */
_end = .;
- } > IRAM
+ } > BSS_AREA
}
diff --git a/firmware/target/arm/s5l8702/crt0.S b/firmware/target/arm/s5l8702/crt0.S
index 3d1ee2bdfd..915c3f680b 100644
--- a/firmware/target/arm/s5l8702/crt0.S
+++ b/firmware/target/arm/s5l8702/crt0.S
@@ -46,17 +46,20 @@ newstart2:
msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
#ifdef BOOTLOADER
- /* Relocate ourself to IRAM - we have been loaded to DRAM */
- mov r0, #0x08000000 /* source (DRAM) */
- mov r1, #0x22000000 /* dest (IRAM) */
- ldr r2, =_dataend
+ /* Relocate ourself to IRAM1 - we have been loaded to IRAM0 */
+ ldr r0, =_dfuloadaddr
+ ldr r1, =_movestart
+ ldr r2, =_moveend
1:
- cmp r2, r1
- ldrhi r3, [r0], #4
- strhi r3, [r1], #4
- bhi 1b
+ ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r1, r2
+ blt 1b
ldr pc, =start_loc /* jump to the relocated start_loc: */
+
+ .section .init.text,"ax",%progbits
+ .global start_loc
start_loc:
#endif
@@ -66,11 +69,11 @@ start_loc:
mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */
.cleancache:
- mrc p15, 0, r15,c7,c10,3
+ mrc p15, 0, r15, c7, c10, 3 /* test and clean dcache */
bne .cleancache
mov r0, #0
- mcr p15, 0, r0,c7,c10,4
- mcr p15, 0, r0,c7,c5,0
+ mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
/* reset VIC controller */
ldr r1, =0x38e00000
@@ -86,7 +89,15 @@ start_loc:
str r0, [r1,#0x14]
str r0, [r2,#0x14]
-#if !defined(BOOTLOADER)
+#if defined(BOOTLOADER)
+ /* SPI speed is limited when icache is not active. Not worth
+ * activating dcache, it is almost useless on pre-init stage
+ * and the TLB needs 16Kb in detriment of the bootloader.
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #1<<12 /* enable icache */
+ mcr p15, 0, r0, c1, c0, 0
+#else
bl memory_init
/* Copy interrupt vectors to iram */
@@ -98,7 +109,6 @@ start_loc:
ldrhi r1, [r4], #4
strhi r1, [r2], #4
bhi 1b
-#endif
/* Initialise bss section to zero */
ldr r2, =_edata
@@ -109,7 +119,6 @@ start_loc:
strhi r4, [r2], #4
bhi 1b
-#ifndef BOOTLOADER
/* Copy icode and data to ram */
ldr r2, =_iramstart
ldr r3, =_iramend
@@ -159,3 +168,33 @@ start_loc:
bhi 1b
b main
+
+#ifdef BOOTLOADER
+ /* Initialise bss section to zero */
+ .global bss_init
+ .type bss_init, %function
+
+bss_init:
+ stmfd sp!, {r4-r9,lr}
+
+ ldr r0, =_edata
+ ldr r1, =_end
+ mov r2, #0
+ mov r3, #0
+ mov r4, #0
+ mov r5, #0
+ mov r6, #0
+ mov r7, #0
+ mov r8, #0
+ mov r9, #0
+ b 2f
+ .align 5 /* cache line size */
+1:
+ stmia r0!, {r2-r9}
+2:
+ cmp r0, r1
+ blt 1b
+
+ ldmpc regs=r4-r9
+ .ltorg
+#endif