diff options
| author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-17 13:42:59 +0000 |
|---|---|---|
| committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-17 13:42:59 +0000 |
| commit | 182ad9bbc2d18d946240491cb52c088227815e8b (patch) | |
| tree | b3bd75876246d646376d3a0d6ee62654fd2739af /firmware | |
| parent | e69c2a97246da4a09fda6ba3cf234f8e38ff2583 (diff) | |
| download | rockbox-182ad9bbc2d18d946240491cb52c088227815e8b.tar.gz rockbox-182ad9bbc2d18d946240491cb52c088227815e8b.zip | |
iriver: Adjusted to optimal I2C bit rates
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7179 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/system.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/firmware/system.c b/firmware/system.c index 0c8c686388..1e42fab9e7 100644 --- a/firmware/system.c +++ b/firmware/system.c @@ -529,9 +529,9 @@ void set_cpu_frequency(long frequency) tick_start(1000/HZ); IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ - /* I2C Clock divisor = 1280 => 119.952 MHz / 1280 = 93,7 kHz */ - MFDR = 0x19; - MFDR2 = 0x19; + /* I2C Clock divisor = 576 => 119.952 MHz / 2 / 576 = 104.125 kHz */ + MFDR = 0x14; + MFDR2 = 0x14; break; case CPUFREQ_NORMAL: @@ -548,9 +548,9 @@ void set_cpu_frequency(long frequency) tick_start(1000/HZ); IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ - /* I2C Clock divisor = 480 => 47.9808 MHz / 480 = 99,9 kHz */ - MFDR = 0x13; - MFDR2 = 0x13; + /* I2C Clock divisor = 240 => 47.9808 MHz / 2 / 240 = 99.96 kHz */ + MFDR = 0x0f; + MFDR2 = 0x0f; break; default: DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass @@ -562,9 +562,9 @@ void set_cpu_frequency(long frequency) tick_start(1000/HZ); IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ - /* I2C Clock divisor = 480 => 47.9808 MHz / 480 = 99,9 kHz */ - MFDR = 0x13; - MFDR2 = 0x13; + /* I2C Clock divisor = 56 => 11.2896 MHz / 56 = 100.8 kHz */ + MFDR = 0x06; + MFDR2 = 0x06; break; } } |