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authorJens Arnold <amiconn@rockbox.org>2005-10-18 19:35:31 +0000
committerJens Arnold <amiconn@rockbox.org>2005-10-18 19:35:31 +0000
commit09b4743707ca2acb86abd96816f62663b79a99df (patch)
treef14afff05f11efba7918858823435bd411b29925 /firmware
parent127f0695457ca19d8d56bee8e33061132c75d646 (diff)
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H110/H115: Slightly longer initial SDRAM refresh cycle, correct comment.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7639 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/crt0.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S
index e903bc9ddf..6cec3ec3ce 100644
--- a/firmware/crt0.S
+++ b/firmware/crt0.S
@@ -191,7 +191,7 @@ irq_handler:
/* Set up the DRAM controller. The refresh is based on the 11.2896MHz
clock (5.6448MHz bus frequency). We haven't yet started the PLL */
#if MEM < 32
- move.w #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */
+ move.w #0x8204,%d0 /* DCR - Synchronous, 80 cycle refresh */
#else
move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */
#endif