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authorAidan MacDonald <amachronic@protonmail.com>2022-01-11 13:58:03 +0000
committerAidan MacDonald <amachronic@protonmail.com>2022-01-16 19:17:25 -0500
commit18b3e91707e42873eab833f0f3da709062207ba7 (patch)
tree7a5ebfc65961713243b607e83fba9e3758cbcc45 /firmware
parent15e3d37110f1674ec7d52c2f055ebfad1d77b5da (diff)
downloadrockbox-18b3e91707e42873eab833f0f3da709062207ba7.tar.gz
rockbox-18b3e91707e42873eab833f0f3da709062207ba7.zip
x1000: internal codec audio driver
Change-Id: I2eb551ec6b593951c33ae6b93df2a23dc6612c43
Diffstat (limited to 'firmware')
-rw-r--r--firmware/SOURCES4
-rw-r--r--firmware/drivers/audio/x1000-codec.c286
-rw-r--r--firmware/export/audiohw.h7
-rw-r--r--firmware/export/x1000-codec.h184
4 files changed, 481 insertions, 0 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 87db67d8fd..e8f9da1a07 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -1669,6 +1669,10 @@ target/mips/ingenic_x1000/spl-start.S
target/mips/ingenic_x1000/spl-x1000.c
common/ucl_decompress.c
#endif
+#if (defined(HAVE_X1000_ICODEC_PLAY) || defined(HAVE_X1000_ICODEC_REC)) \
+ && !defined(BOOTLOADER)
+drivers/audio/x1000-codec.c
+#endif
#endif /* CONFIG_CPU == X1000 */
#if defined(ONDA_VX747) || defined(ONDA_VX747P) || defined(ONDA_VX777)
diff --git a/firmware/drivers/audio/x1000-codec.c b/firmware/drivers/audio/x1000-codec.c
new file mode 100644
index 0000000000..c083882dab
--- /dev/null
+++ b/firmware/drivers/audio/x1000-codec.c
@@ -0,0 +1,286 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2021-2022 Aidan MacDonald
+ * Copyright 2014 Ingenic Semiconductor Co.,Ltd
+ * cscheng <shicheng.cheng@ingenic.com>
+ * sound/soc/ingenic/icodec/icdc_d3.c
+ * ALSA SoC Audio driver -- ingenic internal codec (icdc_d3) driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "x1000-codec.h"
+#include "audiohw.h"
+#include "pcm_sampr.h"
+#include "kernel.h"
+#include "x1000/aic.h"
+
+static const uint8_t fsel_to_hw[HW_NUM_FREQ] = {
+ [0 ... HW_NUM_FREQ-1] = 0,
+ HW_HAVE_8_([HW_FREQ_8] = 0,)
+ HW_HAVE_11_([HW_FREQ_11] = 1,)
+ HW_HAVE_12_([HW_FREQ_12] = 2,)
+ HW_HAVE_16_([HW_FREQ_16] = 3,)
+ HW_HAVE_22_([HW_FREQ_22] = 4,)
+ HW_HAVE_24_([HW_FREQ_24] = 5,)
+ HW_HAVE_32_([HW_FREQ_32] = 6,)
+ HW_HAVE_44_([HW_FREQ_44] = 7,)
+ HW_HAVE_48_([HW_FREQ_48] = 8,)
+ HW_HAVE_88_([HW_FREQ_88] = 9,)
+ HW_HAVE_96_([HW_FREQ_96] = 10,)
+ HW_HAVE_176_([HW_FREQ_176] = 11,)
+ HW_HAVE_192_([HW_FREQ_192] = 12,)
+};
+
+void x1000_icodec_open(void)
+{
+ /* Ingenic does not specify any timing constraints for reset,
+ * let's do a 1ms delay for fun */
+ jz_writef(AIC_RGADW, ICRST(1));
+ mdelay(1);
+ jz_writef(AIC_RGADW, ICRST(0));
+
+ /* Power-up and initial config sequence */
+ static const uint8_t init_config[] = {
+ JZCODEC_CR_VIC, 0x03, /* ensure codec is powered off */
+ JZCODEC_CR_CK, 0x40, /* MCLK_DIV=1, SHUTDOWN_CLK=0, CRYSTAL=12Mhz */
+ JZCODEC_AICR_DAC, 0x13, /* ADWL=0 (16bit word length)
+ * SLAVE=0 (i2s master mode)
+ * SB_DAC=1 (power down DAC)
+ * AUDIOIF=3 (i2s mode) */
+ JZCODEC_AICR_ADC, 0x13, /* ADWL=0 (16bit word length)
+ * SB_ADC=1 (power down ADC)
+ * AUDIOIF=3 (i2s mode)
+ */
+ JZCODEC_CR_DAC, 0x91, /* DAC mute, power down */
+ JZCODEC_CR_DAC2, 0x38, /* DAC power down */
+ JZCODEC_CR_DMIC, 0x00, /* DMIC clock off */
+ JZCODEC_CR_MIC1, 0x30, /* MIC1 power down */
+ JZCODEC_CR_MIC2, 0x30, /* MIC2 power down */
+ JZCODEC_CR_ADC, 0x90, /* ADC mute, power down */
+ JZCODEC_ICR, 0x00, /* INT_FORM=0 (high level IRQ) */
+ JZCODEC_IMR, 0xff, /* Mask all interrupts */
+ JZCODEC_IMR2, 0xff,
+ JZCODEC_IFR, 0xff, /* Clear all interrupt flags */
+ JZCODEC_IFR2, 0xff,
+ };
+
+ for(size_t i = 0; i < ARRAYLEN(init_config); i += 2)
+ x1000_icodec_write(init_config[i], init_config[i+1]);
+
+ /* SB -> 0 (power up) */
+ x1000_icodec_write(JZCODEC_CR_VIC, 0x02);
+ mdelay(250);
+
+ /* Initial gain setting. Apparently we need to set one gain and
+ * then set another after 10ms; afterward it can be changed freely. */
+ static const uint8_t gain_regs[] = {
+ JZCODEC_GCR_DACL,
+ JZCODEC_GCR_DACR,
+ JZCODEC_GCR_DACL2,
+ JZCODEC_GCR_DACR2,
+ JZCODEC_GCR_MIC1,
+ JZCODEC_GCR_MIC2,
+ JZCODEC_GCR_ADCL,
+ JZCODEC_GCR_ADCR,
+ };
+
+ for(size_t i = 0; i < ARRAYLEN(gain_regs); ++i)
+ x1000_icodec_write(gain_regs[i], 0);
+
+ mdelay(10);
+
+ for(size_t i = 0; i < ARRAYLEN(gain_regs); ++i)
+ x1000_icodec_write(gain_regs[i], 1);
+
+ /* SB_SLEEP -> 0 (exit sleep/standby mode) */
+ x1000_icodec_write(JZCODEC_CR_VIC, 0x00);
+ mdelay(200);
+}
+
+void x1000_icodec_close(void)
+{
+ /* SB_SLEEP -> 1 (enable sleep mode) */
+ x1000_icodec_write(JZCODEC_CR_VIC, 0x02);
+
+ /* SB -> 1 (power down) */
+ x1000_icodec_write(JZCODEC_CR_VIC, 0x03);
+}
+
+/*
+ * DAC configuration
+ */
+
+void x1000_icodec_dac_frequency(int fsel)
+{
+ x1000_icodec_update(JZCODEC_FCR_DAC, 0x0f, fsel_to_hw[fsel]);
+}
+
+/*
+ * ADC configuration
+ */
+
+void x1000_icodec_adc_enable(bool en)
+{
+ x1000_icodec_update(JZCODEC_AICR_ADC, 0x10, en ? 0x00 : 0x10);
+ x1000_icodec_update(JZCODEC_CR_ADC, 0x10, en ? 0x00 : 0x10);
+}
+
+void x1000_icodec_adc_mute(bool muted)
+{
+ x1000_icodec_update(JZCODEC_CR_ADC, 0x80, muted ? 0x80 : 0x00);
+}
+
+void x1000_icodec_adc_mic_sel(int sel)
+{
+ x1000_icodec_update(JZCODEC_CR_ADC, 0x40,
+ sel == JZCODEC_MIC_SEL_DIGITAL ? 0x40 : 0x00);
+}
+
+void x1000_icodec_adc_frequency(int fsel)
+{
+ x1000_icodec_update(JZCODEC_FCR_ADC, 0x0f, fsel_to_hw[fsel]);
+}
+
+void x1000_icodec_adc_highpass_filter(bool en)
+{
+ x1000_icodec_update(JZCODEC_FCR_ADC, 0x40, en ? 0x40 : 0x00);
+}
+
+void x1000_icodec_adc_gain(int gain_dB)
+{
+ if(gain_dB < X1000_ICODEC_ADC_GAIN_MIN)
+ gain_dB = X1000_ICODEC_ADC_GAIN_MIN;
+ else if(gain_dB > X1000_ICODEC_ADC_GAIN_MAX)
+ gain_dB = X1000_ICODEC_ADC_GAIN_MAX;
+
+ /* bit 7 = use the same gain for both channels */
+ x1000_icodec_write(JZCODEC_GCR_ADCL, 0x80 | gain_dB);
+}
+
+/*
+ * MIC1 configuration
+ */
+
+void x1000_icodec_mic1_enable(bool en)
+{
+ x1000_icodec_update(JZCODEC_CR_MIC1, 0x10, en ? 0x00 : 0x10);
+}
+
+void x1000_icodec_mic1_bias_enable(bool en)
+{
+ x1000_icodec_update(JZCODEC_CR_MIC1, 0x20, en ? 0x00 : 0x20);
+}
+
+void x1000_icodec_mic1_configure(int settings)
+{
+ x1000_icodec_update(JZCODEC_CR_MIC1, JZCODEC_MIC1_CONFIGURE_MASK,
+ settings & JZCODEC_MIC1_CONFIGURE_MASK);
+}
+
+void x1000_icodec_mic1_gain(int gain_dB)
+{
+ if(gain_dB < X1000_ICODEC_MIC_GAIN_MIN)
+ gain_dB = X1000_ICODEC_MIC_GAIN_MIN;
+ else if(gain_dB > X1000_ICODEC_MIC_GAIN_MAX)
+ gain_dB = X1000_ICODEC_MIC_GAIN_MAX;
+
+ x1000_icodec_write(JZCODEC_GCR_MIC1, gain_dB/X1000_ICODEC_MIC_GAIN_STEP);
+}
+
+/*
+ * Mixer configuration
+ */
+
+void x1000_icodec_mixer_enable(bool en)
+{
+ x1000_icodec_update(JZCODEC_CR_MIX, 0x80, en ? 0x80 : 0x00);
+}
+
+/*
+ * Register access
+ */
+
+static int x1000_icodec_read_direct(int reg)
+{
+ jz_writef(AIC_RGADW, ADDR(reg));
+ return jz_readf(AIC_RGDATA, DATA);
+}
+
+static void x1000_icodec_write_direct(int reg, int value)
+{
+ jz_writef(AIC_RGADW, ADDR(reg), DATA(value));
+ jz_writef(AIC_RGADW, RGWR(1));
+ while(jz_readf(AIC_RGADW, RGWR));
+}
+
+static void x1000_icodec_update_direct(int reg, int mask, int value)
+{
+ int x = x1000_icodec_read_direct(reg) & ~mask;
+ x |= value;
+ x1000_icodec_write_direct(reg, x);
+}
+
+static int x1000_icodec_read_indirect(int c_reg, int index)
+{
+ x1000_icodec_update_direct(c_reg, 0x7f, index & 0x3f);
+ return x1000_icodec_read_direct(c_reg+1);
+}
+
+static void x1000_icodec_write_indirect(int c_reg, int index, int value)
+{
+ /* NB: The X1000 programming manual says we should write the data
+ * register first, but in fact the control register needs to be
+ * written first (following Ingenic's Linux driver). */
+ x1000_icodec_update_direct(c_reg, 0x7f, 0x40 | (index & 0x3f));
+ x1000_icodec_write_direct(c_reg+1, value);
+}
+
+static void x1000_icodec_update_indirect(int c_reg, int index, int mask, int value)
+{
+ int x = x1000_icodec_read_indirect(c_reg, index) & ~mask;
+ x |= value;
+ x1000_icodec_write_indirect(c_reg, index, x);
+}
+
+int x1000_icodec_read(int reg)
+{
+ if(reg & JZCODEC_INDIRECT_BIT)
+ return x1000_icodec_read_indirect(JZCODEC_INDIRECT_CREG(reg),
+ JZCODEC_INDIRECT_INDEX(reg));
+ else
+ return x1000_icodec_read_direct(reg);
+}
+
+void x1000_icodec_write(int reg, int value)
+{
+ if(reg & JZCODEC_INDIRECT_BIT)
+ return x1000_icodec_write_indirect(JZCODEC_INDIRECT_CREG(reg),
+ JZCODEC_INDIRECT_INDEX(reg), value);
+ else
+ return x1000_icodec_write_direct(reg, value);
+}
+
+void x1000_icodec_update(int reg, int mask, int value)
+{
+ if(reg & JZCODEC_INDIRECT_BIT)
+ return x1000_icodec_update_indirect(JZCODEC_INDIRECT_CREG(reg),
+ JZCODEC_INDIRECT_INDEX(reg),
+ mask, value);
+ else
+ return x1000_icodec_update_direct(reg, mask, value);
+}
diff --git a/firmware/export/audiohw.h b/firmware/export/audiohw.h
index 3f1bcb6feb..a365b97828 100644
--- a/firmware/export/audiohw.h
+++ b/firmware/export/audiohw.h
@@ -192,6 +192,8 @@ struct sound_settings_info
#include "tsc2100.h"
#elif defined(HAVE_JZ4740_CODEC)
#include "jz4740-codec.h"
+#elif defined(HAVE_X1000_ICODEC_PLAY)
+#include "x1000-codec.h"
#elif defined(HAVE_AK4537)
#include "ak4537.h"
#elif defined(HAVE_AK4376)
@@ -237,6 +239,11 @@ struct sound_settings_info
#include "erosqlinux_codec.h"
#endif
+#if defined(HAVE_X1000_ICODEC_REC) && !defined(HAVE_X1000_ICODEC_PLAY)
+/* Targets may have an external DAC above, but use icodec for recording only */
+#include "x1000-codec.h"
+#endif
+
/* convert caps into defines */
#ifdef AUDIOHW_CAPS
/* Tone controls */
diff --git a/firmware/export/x1000-codec.h b/firmware/export/x1000-codec.h
new file mode 100644
index 0000000000..cfc71dbd60
--- /dev/null
+++ b/firmware/export/x1000-codec.h
@@ -0,0 +1,184 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2021-2022 Aidan MacDonald
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef __X1000_CODEC_H__
+#define __X1000_CODEC_H__
+
+#include "config.h"
+#include <stdbool.h>
+
+/* Note: the internal X1000 codec supports playback and record, but devices
+ * can employ an external codec for one and the internal codec for the other.
+ * The caveat, in this case, is that only one codec can be used at a time
+ * because the HW cannot mux playback/record independently.
+ *
+ * At present only recording is implemented, since all X1000 ports use an
+ * external DAC for playback.
+ */
+
+#ifdef HAVE_X1000_ICODEC_PLAY
+# error "X1000 icodec playback not implemented"
+#endif
+
+#define X1000_ICODEC_ADC_GAIN_MIN 0
+#define X1000_ICODEC_ADC_GAIN_MAX 43
+#define X1000_ICODEC_ADC_GAIN_STEP 1
+
+#define X1000_ICODEC_MIC_GAIN_MIN 0
+#define X1000_ICODEC_MIC_GAIN_MAX 20
+#define X1000_ICODEC_MIC_GAIN_STEP 4
+
+#ifdef HAVE_X1000_ICODEC_REC
+AUDIOHW_SETTING(MIC_GAIN, "dB", 0, 1, 0, 63, 12)
+#endif
+
+#define JZCODEC_INDIRECT_CREG(r) ((r) & 0xff)
+#define JZCODEC_INDIRECT_INDEX(r) (((r) >> 8) & 0x7)
+#define JZCODEC_INDIRECT_BIT 0x800
+
+#define JZCODEC_INDIRECT(c, i) (JZCODEC_INDIRECT_BIT | ((i) << 8) | (c))
+
+/* Codec registers from Ingenic's kernel sources. The datasheet is badly
+ * screwed up and the addresses listed cannot be trusted. */
+enum {
+ JZCODEC_SR = 0,
+ JZCODEC_SR2,
+ JZCODEC_SIGR,
+ JZCODEC_SIGR2,
+ JZCODEC_SIGR3,
+ JZCODEC_SIGR5,
+ JZCODEC_SIGR7,
+ JZCODEC_MR,
+ JZCODEC_AICR_DAC,
+ JZCODEC_AICR_ADC,
+ JZCODEC_CR_DMIC,
+ JZCODEC_CR_MIC1,
+ JZCODEC_CR_MIC2,
+ JZCODEC_CR_DAC,
+ JZCODEC_CR_DAC2,
+ JZCODEC_CR_ADC,
+ JZCODEC_CR_MIX,
+ JZCODEC_DR_MIX,
+ JZCODEC_CR_VIC,
+ JZCODEC_CR_CK,
+ JZCODEC_FCR_DAC,
+ JZCODEC_SFCCR_DAC,
+ JZCODEC_SFFCR_DAC,
+ JZCODEC_FCR_ADC,
+ JZCODEC_CR_TIMER_MSB,
+ JZCODEC_CR_TIMER_LSB,
+ JZCODEC_ICR,
+ JZCODEC_IMR,
+ JZCODEC_IFR,
+ JZCODEC_IMR2,
+ JZCODEC_IFR2,
+ JZCODEC_GCR_DACL,
+ JZCODEC_GCR_DACR,
+ JZCODEC_GCR_DACL2,
+ JZCODEC_GCR_DACR2,
+ JZCODEC_GCR_MIC1,
+ JZCODEC_GCR_MIC2,
+ JZCODEC_GCR_ADCL,
+ JZCODEC_GCR_ADCR,
+ JZCODEC_GCR_MIXDACL,
+ JZCODEC_GCR_MIXDACR,
+ JZCODEC_GCR_MIXADCL,
+ JZCODEC_GCR_MIXADCR,
+ JZCODEC_CR_DAC_AGC,
+ JZCODEC_DR_DAC_AGC,
+ JZCODEC_CR_DAC2_AGC,
+ JZCODEC_DR_DAC2_AGC,
+ JZCODEC_CR_ADC_AGC,
+ JZCODEC_DR_ADC_AGC,
+ JZCODEC_SR_ADC_AGCDGL,
+ JZCODEC_SR_ADC_AGCDGR,
+ JZCODEC_SR_ADC_AGCAGL,
+ JZCODEC_SR_ADC_AGCAGR,
+ JZCODEC_CR_TR,
+ JZCODEC_DR_TR,
+ JZCODEC_SR_TR1,
+ JZCODEC_SR_TR2,
+ JZCODEC_SR_TR_SRCDAC,
+
+ JZCODEC_MIX0 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 0),
+ JZCODEC_MIX1 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 1),
+ JZCODEC_MIX2 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 2),
+ JZCODEC_MIX3 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 3),
+ JZCODEC_MIX4 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 4),
+
+ JZCODEC_DAC_AGC0 = JZCODEC_INDIRECT(JZCODEC_CR_DAC_AGC, 0),
+ JZCODEC_DAC_AGC1 = JZCODEC_INDIRECT(JZCODEC_CR_DAC_AGC, 1),
+ JZCODEC_DAC_AGC2 = JZCODEC_INDIRECT(JZCODEC_CR_DAC_AGC, 2),
+ JZCODEC_DAC_AGC3 = JZCODEC_INDIRECT(JZCODEC_CR_DAC_AGC, 3),
+
+ JZCODEC_DAC2_AGC0 = JZCODEC_INDIRECT(JZCODEC_CR_DAC2_AGC, 0),
+ JZCODEC_DAC2_AGC1 = JZCODEC_INDIRECT(JZCODEC_CR_DAC2_AGC, 1),
+ JZCODEC_DAC2_AGC2 = JZCODEC_INDIRECT(JZCODEC_CR_DAC2_AGC, 2),
+ JZCODEC_DAC2_AGC3 = JZCODEC_INDIRECT(JZCODEC_CR_DAC2_AGC, 3),
+
+ JZCODEC_ADC_AGC0 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 0),
+ JZCODEC_ADC_AGC1 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 1),
+ JZCODEC_ADC_AGC2 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 2),
+ JZCODEC_ADC_AGC3 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 3),
+ JZCODEC_ADC_AGC4 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 4),
+};
+
+/* for use with x1000_icodec_mic1_configure() */
+enum {
+ JZCODEC_MIC1_SINGLE_ENDED = (0 << 6),
+ JZCODEC_MIC1_DIFFERENTIAL = (1 << 6),
+
+ JZCODEC_MIC1_BIAS_2_08V = (0 << 3),
+ JZCODEC_MIC1_BIAS_1_66V = (1 << 3),
+
+ JZCODEC_MIC1_CONFIGURE_MASK = (1 << 6) | (1 << 3),
+};
+
+/* for use with x1000_icodec_adc_mic_sel() */
+enum {
+ JZCODEC_MIC_SEL_ANALOG,
+ JZCODEC_MIC_SEL_DIGITAL,
+};
+
+extern void x1000_icodec_open(void);
+extern void x1000_icodec_close(void);
+
+extern void x1000_icodec_dac_frequency(int fsel);
+
+extern void x1000_icodec_adc_enable(bool en);
+extern void x1000_icodec_adc_mute(bool muted);
+extern void x1000_icodec_adc_mic_sel(int sel);
+extern void x1000_icodec_adc_frequency(int fsel);
+extern void x1000_icodec_adc_highpass_filter(bool en);
+extern void x1000_icodec_adc_gain(int gain_dB);
+
+extern void x1000_icodec_mic1_enable(bool en);
+extern void x1000_icodec_mic1_bias_enable(bool en);
+extern void x1000_icodec_mic1_configure(int settings);
+extern void x1000_icodec_mic1_gain(int gain_dB);
+
+extern void x1000_icodec_mixer_enable(bool en);
+
+extern int x1000_icodec_read(int reg);
+extern void x1000_icodec_write(int reg, int value);
+extern void x1000_icodec_update(int reg, int mask, int value);
+
+#endif /* __X1000_CODEC_H__ */