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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-06-04 11:57:43 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-06-04 11:57:43 +0000 |
commit | 48203093cee1bc23bc744026c12aa77a5c290362 (patch) | |
tree | bfb51130567c4d6a06cb7b4b8c46c37223603004 /firmware | |
parent | 398e1059c50a659b08b8a7bf997c24ee0217b8ee (diff) | |
download | rockbox-48203093cee1bc23bc744026c12aa77a5c290362.tar.gz rockbox-48203093cee1bc23bc744026c12aa77a5c290362.zip |
Fix RoLo on MIPS targets
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21185 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/rolo.c | 2 | ||||
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/firmware/rolo.c b/firmware/rolo.c index 2a352b4f72..316d23f8e1 100644 --- a/firmware/rolo.c +++ b/firmware/rolo.c @@ -181,7 +181,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest, : : "r"(dest) ); #elif defined(CPU_MIPS) - cpucache_invalidate(); + __dcache_writeback_all(); asm volatile( "jr %0 \n" : : "r"(dest) diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 2f7f19d3b3..92cdecdc85 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c @@ -189,6 +189,7 @@ void __dcache_invalidate_all(void) __CACHE_OP(DCIndexStTag, i); } +void __dcache_writeback_all(void) __attribute__ ((section(".icode"))); void __dcache_writeback_all(void) { unsigned int i; |