M:Robe 500: Use bit modifiers more.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29247 a1c6a512-1295-4272-9138-f99709370657

4 files changed, 28 insertions, 20 deletions

diff --git a/firmware/target/arm/tms320dm320/dsp-dm320.c b/firmware/target/arm/tms320dm320/dsp-dm320.c
index 5f0c997bd2..be9f8d8bd9 100644
--- a/firmware/target/arm/tms320dm320/dsp-dm320.c
+++ b/firmware/target/arm/tms320dm320/dsp-dm320.c
@@ -64,10 +64,10 @@ void dsp_reset(void)
 {
     DSP_(0x7fff) = 0xdead;
     
-    IO_DSPC_HPIB_CONTROL &= ~(1 << 8);
+    bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8);
     /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */
     nop; nop;
-    IO_DSPC_HPIB_CONTROL |= 1 << 8;
+    bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8);
     
     /* TODO: Timeout. */
     while (DSP_(0x7fff) != 0);
@@ -81,9 +81,9 @@ void dsp_wake(void)
     
     /* The first time you INT0 the DSP, the ROM loader will branch to your RST
        handler. Subsequent times, your INT0 handler will get executed. */
-    IO_DSPC_HPIB_CONTROL &= ~(1 << 7);
+    bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7);
     nop; nop;
-    IO_DSPC_HPIB_CONTROL |= 1 << 7;
+    bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7);
     
     restore_irq(old_level);
 }
diff --git a/firmware/target/arm/tms320dm320/kernel-dm320.c b/firmware/target/arm/tms320dm320/kernel-dm320.c
index 7c3805eb0e..08c50432e4 100644
--- a/firmware/target/arm/tms320dm320/kernel-dm320.c
+++ b/firmware/target/arm/tms320dm320/kernel-dm320.c
@@ -27,7 +27,7 @@
 
 void tick_start(unsigned int interval_in_ms)
 {
-    IO_CLK_MOD2 |= CLK_MOD2_TMR1; /* enable TIMER1 clock */
+    bitset16(&IO_CLK_MOD2, CLK_MOD2_TMR1); /* enable TIMER1 clock */
     IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP;
     
     /*  Setup the Prescalar (Divide by 10)
@@ -42,7 +42,7 @@ void tick_start(unsigned int interval_in_ms)
     IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_FREE_RUN;
     
     /* Enable the interrupt */
-    IO_INTC_EINT0 |= INTR_EINT0_TMR1;
+    bitset16(&IO_INTC_EINT0, INTR_EINT0_TMR1);
 }
 
 void TIMER1(void) __attribute__ ((section(".icode")));
diff --git a/firmware/target/arm/tms320dm320/timer-dm320.c b/firmware/target/arm/tms320dm320/timer-dm320.c
index 030d645664..0b7ad893d3 100644
--- a/firmware/target/arm/tms320dm320/timer-dm320.c
+++ b/firmware/target/arm/tms320dm320/timer-dm320.c
@@ -45,7 +45,7 @@ bool timer_set(long cycles, bool start)
 
     oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL);
     
-    IO_CLK_MOD2 |= CLK_MOD2_TMR0; //enable TIMER0 clock!!!!!!!!!
+    bitset16(&IO_CLK_MOD2, CLK_MOD2_TMR0); /* enable TIMER0 clock */
 
     IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP;
 
@@ -74,13 +74,16 @@ bool timer_set(long cycles, bool start)
 
 static void stop_timer(void)
 {
-    IO_INTC_EINT0 &= ~INTR_EINT0_TMR0; //disable TIMER0 interrupt
+    /* disable TIMER0 interrupt */
+    bitclr16(&IO_INTC_EINT0, INTR_EINT0_TMR0);
 
-    IO_INTC_IRQ0 = INTR_IRQ0_TMR0; //clear TIMER0 interrupt
+    /* clear TIMER0 interrupt */
+    IO_INTC_IRQ0 = INTR_IRQ0_TMR0;
     
     IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP;
     
-    IO_CLK_MOD2 &= ~CLK_MOD2_TMR0; //disable TIMER0 clock
+    /* disable TIMER0 clock */
+    bitclr16(&IO_CLK_MOD2, CLK_MOD2_TMR0);
 }
 
 bool timer_start(void)
@@ -89,12 +92,14 @@ bool timer_start(void)
     
     stop_timer();
     
-    IO_CLK_MOD2 |= CLK_MOD2_TMR0; //enable TIMER0 clock!!!!!!!!!
+    /* enable TIMER0 clock */
+    bitset16(&IO_CLK_MOD2, CLK_MOD2_TMR0);
 
     /* Turn Timer0 to Free Run mode */
     IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_FREE_RUN;
 
-    IO_INTC_EINT0 |= INTR_EINT0_TMR0; //enable TIMER0 interrupt
+    /* enable TIMER0 interrupt */
+    bitset16(&IO_INTC_EINT0, INTR_EINT0_TMR0);
 
     restore_interrupt(oldstatus);
 
diff --git a/firmware/target/arm/tms320dm320/uart-dm320.c b/firmware/target/arm/tms320dm320/uart-dm320.c
index 50e6998e2a..0aeb856027 100644
--- a/firmware/target/arm/tms320dm320/uart-dm320.c
+++ b/firmware/target/arm/tms320dm320/uart-dm320.c
@@ -39,7 +39,7 @@ static volatile int uart1_receive_count, uart1_receive_read, uart1_receive_write
 void uart_init(void)
 {
     /* Enable UART clock */
-    IO_CLK_MOD2 |= CLK_MOD2_UART1;
+    bitset16(&IO_CLK_MOD2, CLK_MOD2_UART1);
     
     // 8-N-1
     IO_UART1_MSR = 0xC400;
@@ -58,7 +58,7 @@ void uart_init(void)
     uart1_send_write=0;
 
     /* Enable the interrupt */
-    IO_INTC_EINT0 |= INTR_EINT0_UART1;
+    bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 }
 
 /* This function is not interrupt driven */
@@ -85,7 +85,7 @@ void uart1_puts(const char *str, int size)
     memcpy(uart1_send_buffer_ring, str, size);
     
     /* Disable interrupt while modifying the pointers */
-    IO_INTC_EINT0 &= ~INTR_EINT0_UART1;
+    bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
     
     uart1_send_count=size;
     uart1_send_read=0;
@@ -98,25 +98,27 @@ void uart1_puts(const char *str, int size)
     }
     
     /* Enable interrupt */
-    IO_INTC_EINT0 |= INTR_EINT0_UART1;
+    bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 }
 
 void uart1_clear_queue(void)
 {
     /* Disable interrupt while modifying the pointers */
-    IO_INTC_EINT0 &= ~INTR_EINT0_UART1;
+    bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
+
     uart1_receive_write=0;
     uart1_receive_count=0;
     uart1_receive_read=0;
+
     /* Enable interrupt */
-    IO_INTC_EINT0 |= INTR_EINT0_UART1;
+    bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 }
 
 /* This function returns the number of bytes left in the queue after a read is done (negative if fail)*/
 int uart1_gets_queue(char *str, int size)
 {
     /* Disable the interrupt while modifying the pointers */
-    IO_INTC_EINT0 &= ~INTR_EINT0_UART1;
+    bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
     int retval;
     
     if(uart1_receive_count<size)
@@ -146,7 +148,7 @@ int uart1_gets_queue(char *str, int size)
     }
 
     /* Enable the interrupt */
-    IO_INTC_EINT0 |= INTR_EINT0_UART1;
+    bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 
     return retval;
 }
@@ -176,3 +178,4 @@ void UART1(void)
         uart1_send_count--;
     }
 }
+