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authorTorne Wuff <torne@wolfpuppy.org.uk>2011-11-06 22:44:25 +0000
committerTorne Wuff <torne@wolfpuppy.org.uk>2011-11-06 22:44:25 +0000
commit569285794b9112f0134ddad4bb886308ea4a7be6 (patch)
treece702cb07829820261a682c471133c76d11c610e /firmware
parentd9b7d58fa6c9ceb136bea429adf6746cc7138208 (diff)
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Bulk convert all DOS line endings to UNIX.
For the git migration we want a nice clean repository with UNIX line endings. git does not use svn:eol-style, we just need the file contents to be sane. Sorry everybody. I know this messes up blame. Scumbag *NIX developer says migrating to git will make line ending issues go away; commits giant change to svn which changes line endings anyway. :) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30924 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/drivers/audio/cs42l55.c490
-rw-r--r--firmware/drivers/audio/dac3550a.c2
-rw-r--r--firmware/export/ata-defines.h116
-rw-r--r--firmware/export/config/rk27generic.h378
-rw-r--r--firmware/export/dac3550a.h2
-rw-r--r--firmware/export/mascodec.h2
-rw-r--r--firmware/export/s5l8702.h1660
-rw-r--r--firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c2
-rw-r--r--firmware/target/arm/s5l8700/postmortemstub.S616
-rw-r--r--firmware/target/arm/s5l8702/debug-s5l8702.c332
-rw-r--r--firmware/target/arm/s5l8702/debug-target.h66
-rw-r--r--firmware/target/arm/s5l8702/i2c-s5l8702.c392
-rw-r--r--firmware/target/arm/s5l8702/kernel-s5l8702.c112
-rw-r--r--firmware/target/arm/s5l8702/pcm-s5l8702.c456
-rw-r--r--firmware/target/arm/s5l8702/pcm-target.h80
-rw-r--r--firmware/target/arm/s5l8702/system-target.h94
-rw-r--r--firmware/target/arm/s5l8702/timer-s5l8702.c188
-rw-r--r--firmware/target/sh/archos/mascodec-archos.c2
18 files changed, 2495 insertions, 2495 deletions
diff --git a/firmware/drivers/audio/cs42l55.c b/firmware/drivers/audio/cs42l55.c
index c81a3fc012..38380d5a54 100644
--- a/firmware/drivers/audio/cs42l55.c
+++ b/firmware/drivers/audio/cs42l55.c
@@ -1,245 +1,245 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: wm8975.c 28572 2010-11-13 11:38:38Z theseven $
- *
- * Driver for Cirrus Logic CS42L55 audio codec
- *
- * Copyright (c) 2010 Michael Sparmann
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#include "logf.h"
-#include "system.h"
-#include "string.h"
-#include "audio.h"
-#include "sound.h"
-#include "audiohw.h"
-#include "cscodec.h"
-#include "cs42l55.h"
-
-const struct sound_settings_info audiohw_settings[] = {
- [SOUND_VOLUME] = {"dB", 0, 1, -60, 12, -25},
- [SOUND_BASS] = {"dB", 1, 15,-105, 120, 0},
- [SOUND_TREBLE] = {"dB", 1, 15,-105, 120, 0},
- [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
- [SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
- [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
- [SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 2},
- [SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1},
-};
-
-static int bass, treble;
-
-/* convert tenth of dB volume (-600..120) to master volume register value */
-int tenthdb2master(int db)
-{
- /* -60dB to +12dB in 1dB steps */
- /* 0001100 == +12dB (0xc) */
- /* 0000000 == 0dB (0x0) */
- /* 1000100 == -60dB (0x44, this is actually -58dB) */
-
- if (db < VOLUME_MIN) return HPACTL_HPAMUTE;
- return (db / 10) & HPACTL_HPAVOL_MASK;
-}
-
-static void cscodec_setbits(int reg, unsigned char off, unsigned char on)
-{
- unsigned char data = (cscodec_read(reg) & ~off) | on;
- cscodec_write(reg, data);
-}
-
-static void audiohw_mute(bool mute)
-{
- if (mute) cscodec_setbits(PLAYCTL, 0, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE);
- else cscodec_setbits(PLAYCTL, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE, 0);
-}
-
-void audiohw_preinit(void)
-{
- cscodec_power(true);
- cscodec_clock(true);
- cscodec_reset(true);
- sleep(HZ / 100);
- cscodec_reset(false);
-
- bass = 0;
- treble = 0;
-
- /* Ask Cirrus or maybe Apple what the hell this means */
- cscodec_write(HIDDENCTL, HIDDENCTL_UNLOCK);
- cscodec_write(HIDDEN2E, HIDDEN2E_DEFAULT);
- cscodec_write(HIDDEN32, HIDDEN32_DEFAULT);
- cscodec_write(HIDDEN33, HIDDEN33_DEFAULT);
- cscodec_write(HIDDEN34, HIDDEN34_DEFAULT);
- cscodec_write(HIDDEN35, HIDDEN35_DEFAULT);
- cscodec_write(HIDDEN36, HIDDEN36_DEFAULT);
- cscodec_write(HIDDEN37, HIDDEN37_DEFAULT);
- cscodec_write(HIDDEN3A, HIDDEN3A_DEFAULT);
- cscodec_write(HIDDEN3C, HIDDEN3C_DEFAULT);
- cscodec_write(HIDDEN3D, HIDDEN3D_DEFAULT);
- cscodec_write(HIDDEN3E, HIDDEN3E_DEFAULT);
- cscodec_write(HIDDEN3F, HIDDEN3F_DEFAULT);
- cscodec_write(HIDDENCTL, HIDDENCTL_LOCK);
-
- cscodec_write(PWRCTL2, PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS
- | PWRCTL2_PDN_HPA_NEVER | PWRCTL2_PDN_HPB_NEVER);
- cscodec_write(CLKCTL1, CLKCTL1_MASTER | CLKCTL1_SCLKMCLK_BEFORE
- | CLKCTL1_MCLKDIV2);
- cscodec_write(CLKCTL2, CLKCTL2_44100HZ);
- cscodec_write(MISCCTL, MISCCTL_UNDOC4 | MISCCTL_ANLGZC | MISCCTL_DIGSFT);
- cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
- | PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC);
- cscodec_write(PLAYCTL, PLAYCTL_PDN_DSP
- | PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE);
- cscodec_write(PGAACTL, 0);
- cscodec_write(PGABCTL, 0);
- cscodec_write(HPACTL, HPACTL_HPAMUTE);
- cscodec_write(HPBCTL, HPBCTL_HPBMUTE);
- cscodec_write(LINEACTL, LINEACTL_LINEAMUTE);
- cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE);
- cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
- | PWRCTL1_PDN_ADCB);
-}
-
-void audiohw_postinit(void)
-{
- cscodec_write(HPACTL, 0);
- cscodec_write(HPBCTL, 0);
- cscodec_write(LINEACTL, 0);
- cscodec_write(LINEBCTL, 0);
- cscodec_write(CLSHCTL, CLSHCTL_ADPTPWR_SIGNAL);
- audiohw_mute(false);
-}
-
-void audiohw_set_master_vol(int vol_l, int vol_r)
-{
- /* -60dB to +12dB in 1dB steps */
- /* 0001100 == +12dB (0xc) */
- /* 0000000 == 0dB (0x0) */
- /* 1000100 == -60dB (0x44, this is actually -58dB) */
-
- cscodec_setbits(HPACTL, HPACTL_HPAVOL_MASK | HPACTL_HPAMUTE,
- vol_l << HPACTL_HPAVOL_SHIFT);
- cscodec_setbits(HPBCTL, HPBCTL_HPBVOL_MASK | HPBCTL_HPBMUTE,
- vol_r << HPBCTL_HPBVOL_SHIFT);
-}
-
-void audiohw_set_lineout_vol(int vol_l, int vol_r)
-{
- /* -60dB to +12dB in 1dB steps */
- /* 0001100 == +12dB (0xc) */
- /* 0000000 == 0dB (0x0) */
- /* 1000100 == -60dB (0x44, this is actually -58dB) */
-
- cscodec_setbits(LINEACTL, LINEACTL_LINEAVOL_MASK | LINEACTL_LINEAMUTE,
- vol_l << LINEACTL_LINEAVOL_SHIFT);
- cscodec_setbits(LINEBCTL, LINEBCTL_LINEBVOL_MASK | LINEBCTL_LINEBMUTE,
- vol_r << LINEBCTL_LINEBVOL_SHIFT);
-}
-
-void audiohw_enable_lineout(bool enable)
-{
- if (enable)
- cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK,
- PWRCTL2_PDN_LINA_NEVER | PWRCTL2_PDN_LINB_NEVER);
- else
- cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK,
- PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS);
-}
-
-static void handle_dsp_power(void)
-{
- if (bass || treble)
- {
- cscodec_setbits(PLAYCTL, PLAYCTL_PDN_DSP, 0);
- cscodec_setbits(BTCTL, 0, BTCTL_TCEN);
- }
- else
- {
- cscodec_setbits(BTCTL, BTCTL_TCEN, 0);
- cscodec_setbits(PLAYCTL, 0, PLAYCTL_PDN_DSP);
- }
-}
-
-void audiohw_set_bass(int value)
-{
- bass = value;
- handle_dsp_power();
- if (value >= -105 && value <= 120)
- cscodec_setbits(TONECTL, TONECTL_BASS_MASK,
- (8 - value / 15) << TONECTL_BASS_SHIFT);
-}
-
-void audiohw_set_treble(int value)
-{
- treble = value;
- handle_dsp_power();
- if (value >= -105 && value <= 120)
- cscodec_setbits(TONECTL, TONECTL_TREB_MASK,
- (8 - value / 15) << TONECTL_TREB_SHIFT);
-}
-
-void audiohw_set_bass_cutoff(int value)
-{
- cscodec_setbits(BTCTL, BTCTL_BASSCF_MASK,
- (value - 1) << BTCTL_BASSCF_SHIFT);
-}
-
-void audiohw_set_treble_cutoff(int value)
-{
- cscodec_setbits(BTCTL, BTCTL_TREBCF_MASK,
- (value - 1) << BTCTL_TREBCF_SHIFT);
-}
-
-void audiohw_set_prescaler(int value)
-{
- cscodec_setbits(MSTAVOL, MSTAVOL_VOLUME_MASK,
- (-value / 5) << MSTAVOL_VOLUME_SHIFT);
- cscodec_setbits(MSTBVOL, MSTBVOL_VOLUME_MASK,
- (-value / 5) << MSTBVOL_VOLUME_SHIFT);
-}
-
-/* Nice shutdown of CS42L55 codec */
-void audiohw_close(void)
-{
- audiohw_mute(true);
- cscodec_write(HPACTL, HPACTL_HPAMUTE);
- cscodec_write(HPBCTL, HPBCTL_HPBMUTE);
- cscodec_write(LINEACTL, LINEACTL_LINEAMUTE);
- cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE);
- cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
- | PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC);
- cscodec_reset(true);
- cscodec_clock(false);
- cscodec_power(false);
-}
-
-/* Note: Disable output before calling this function */
-void audiohw_set_frequency(int fsel)
-{
- if (fsel == HW_FREQ_8) cscodec_write(CLKCTL2, CLKCTL2_8000HZ);
- else if (fsel == HW_FREQ_11) cscodec_write(CLKCTL2, CLKCTL2_11025HZ);
- else if (fsel == HW_FREQ_12) cscodec_write(CLKCTL2, CLKCTL2_12000HZ);
- else if (fsel == HW_FREQ_16) cscodec_write(CLKCTL2, CLKCTL2_16000HZ);
- else if (fsel == HW_FREQ_22) cscodec_write(CLKCTL2, CLKCTL2_22050HZ);
- else if (fsel == HW_FREQ_24) cscodec_write(CLKCTL2, CLKCTL2_24000HZ);
- else if (fsel == HW_FREQ_32) cscodec_write(CLKCTL2, CLKCTL2_32000HZ);
- else if (fsel == HW_FREQ_44) cscodec_write(CLKCTL2, CLKCTL2_44100HZ);
- else if (fsel == HW_FREQ_48) cscodec_write(CLKCTL2, CLKCTL2_48000HZ);
-}
-
-#ifdef HAVE_RECORDING
-//TODO: Implement
-#endif /* HAVE_RECORDING */
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: wm8975.c 28572 2010-11-13 11:38:38Z theseven $
+ *
+ * Driver for Cirrus Logic CS42L55 audio codec
+ *
+ * Copyright (c) 2010 Michael Sparmann
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "logf.h"
+#include "system.h"
+#include "string.h"
+#include "audio.h"
+#include "sound.h"
+#include "audiohw.h"
+#include "cscodec.h"
+#include "cs42l55.h"
+
+const struct sound_settings_info audiohw_settings[] = {
+ [SOUND_VOLUME] = {"dB", 0, 1, -60, 12, -25},
+ [SOUND_BASS] = {"dB", 1, 15,-105, 120, 0},
+ [SOUND_TREBLE] = {"dB", 1, 15,-105, 120, 0},
+ [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
+ [SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
+ [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
+ [SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 2},
+ [SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1},
+};
+
+static int bass, treble;
+
+/* convert tenth of dB volume (-600..120) to master volume register value */
+int tenthdb2master(int db)
+{
+ /* -60dB to +12dB in 1dB steps */
+ /* 0001100 == +12dB (0xc) */
+ /* 0000000 == 0dB (0x0) */
+ /* 1000100 == -60dB (0x44, this is actually -58dB) */
+
+ if (db < VOLUME_MIN) return HPACTL_HPAMUTE;
+ return (db / 10) & HPACTL_HPAVOL_MASK;
+}
+
+static void cscodec_setbits(int reg, unsigned char off, unsigned char on)
+{
+ unsigned char data = (cscodec_read(reg) & ~off) | on;
+ cscodec_write(reg, data);
+}
+
+static void audiohw_mute(bool mute)
+{
+ if (mute) cscodec_setbits(PLAYCTL, 0, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE);
+ else cscodec_setbits(PLAYCTL, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE, 0);
+}
+
+void audiohw_preinit(void)
+{
+ cscodec_power(true);
+ cscodec_clock(true);
+ cscodec_reset(true);
+ sleep(HZ / 100);
+ cscodec_reset(false);
+
+ bass = 0;
+ treble = 0;
+
+ /* Ask Cirrus or maybe Apple what the hell this means */
+ cscodec_write(HIDDENCTL, HIDDENCTL_UNLOCK);
+ cscodec_write(HIDDEN2E, HIDDEN2E_DEFAULT);
+ cscodec_write(HIDDEN32, HIDDEN32_DEFAULT);
+ cscodec_write(HIDDEN33, HIDDEN33_DEFAULT);
+ cscodec_write(HIDDEN34, HIDDEN34_DEFAULT);
+ cscodec_write(HIDDEN35, HIDDEN35_DEFAULT);
+ cscodec_write(HIDDEN36, HIDDEN36_DEFAULT);
+ cscodec_write(HIDDEN37, HIDDEN37_DEFAULT);
+ cscodec_write(HIDDEN3A, HIDDEN3A_DEFAULT);
+ cscodec_write(HIDDEN3C, HIDDEN3C_DEFAULT);
+ cscodec_write(HIDDEN3D, HIDDEN3D_DEFAULT);
+ cscodec_write(HIDDEN3E, HIDDEN3E_DEFAULT);
+ cscodec_write(HIDDEN3F, HIDDEN3F_DEFAULT);
+ cscodec_write(HIDDENCTL, HIDDENCTL_LOCK);
+
+ cscodec_write(PWRCTL2, PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS
+ | PWRCTL2_PDN_HPA_NEVER | PWRCTL2_PDN_HPB_NEVER);
+ cscodec_write(CLKCTL1, CLKCTL1_MASTER | CLKCTL1_SCLKMCLK_BEFORE
+ | CLKCTL1_MCLKDIV2);
+ cscodec_write(CLKCTL2, CLKCTL2_44100HZ);
+ cscodec_write(MISCCTL, MISCCTL_UNDOC4 | MISCCTL_ANLGZC | MISCCTL_DIGSFT);
+ cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
+ | PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC);
+ cscodec_write(PLAYCTL, PLAYCTL_PDN_DSP
+ | PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE);
+ cscodec_write(PGAACTL, 0);
+ cscodec_write(PGABCTL, 0);
+ cscodec_write(HPACTL, HPACTL_HPAMUTE);
+ cscodec_write(HPBCTL, HPBCTL_HPBMUTE);
+ cscodec_write(LINEACTL, LINEACTL_LINEAMUTE);
+ cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE);
+ cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
+ | PWRCTL1_PDN_ADCB);
+}
+
+void audiohw_postinit(void)
+{
+ cscodec_write(HPACTL, 0);
+ cscodec_write(HPBCTL, 0);
+ cscodec_write(LINEACTL, 0);
+ cscodec_write(LINEBCTL, 0);
+ cscodec_write(CLSHCTL, CLSHCTL_ADPTPWR_SIGNAL);
+ audiohw_mute(false);
+}
+
+void audiohw_set_master_vol(int vol_l, int vol_r)
+{
+ /* -60dB to +12dB in 1dB steps */
+ /* 0001100 == +12dB (0xc) */
+ /* 0000000 == 0dB (0x0) */
+ /* 1000100 == -60dB (0x44, this is actually -58dB) */
+
+ cscodec_setbits(HPACTL, HPACTL_HPAVOL_MASK | HPACTL_HPAMUTE,
+ vol_l << HPACTL_HPAVOL_SHIFT);
+ cscodec_setbits(HPBCTL, HPBCTL_HPBVOL_MASK | HPBCTL_HPBMUTE,
+ vol_r << HPBCTL_HPBVOL_SHIFT);
+}
+
+void audiohw_set_lineout_vol(int vol_l, int vol_r)
+{
+ /* -60dB to +12dB in 1dB steps */
+ /* 0001100 == +12dB (0xc) */
+ /* 0000000 == 0dB (0x0) */
+ /* 1000100 == -60dB (0x44, this is actually -58dB) */
+
+ cscodec_setbits(LINEACTL, LINEACTL_LINEAVOL_MASK | LINEACTL_LINEAMUTE,
+ vol_l << LINEACTL_LINEAVOL_SHIFT);
+ cscodec_setbits(LINEBCTL, LINEBCTL_LINEBVOL_MASK | LINEBCTL_LINEBMUTE,
+ vol_r << LINEBCTL_LINEBVOL_SHIFT);
+}
+
+void audiohw_enable_lineout(bool enable)
+{
+ if (enable)
+ cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK,
+ PWRCTL2_PDN_LINA_NEVER | PWRCTL2_PDN_LINB_NEVER);
+ else
+ cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK,
+ PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS);
+}
+
+static void handle_dsp_power(void)
+{
+ if (bass || treble)
+ {
+ cscodec_setbits(PLAYCTL, PLAYCTL_PDN_DSP, 0);
+ cscodec_setbits(BTCTL, 0, BTCTL_TCEN);
+ }
+ else
+ {
+ cscodec_setbits(BTCTL, BTCTL_TCEN, 0);
+ cscodec_setbits(PLAYCTL, 0, PLAYCTL_PDN_DSP);
+ }
+}
+
+void audiohw_set_bass(int value)
+{
+ bass = value;
+ handle_dsp_power();
+ if (value >= -105 && value <= 120)
+ cscodec_setbits(TONECTL, TONECTL_BASS_MASK,
+ (8 - value / 15) << TONECTL_BASS_SHIFT);
+}
+
+void audiohw_set_treble(int value)
+{
+ treble = value;
+ handle_dsp_power();
+ if (value >= -105 && value <= 120)
+ cscodec_setbits(TONECTL, TONECTL_TREB_MASK,
+ (8 - value / 15) << TONECTL_TREB_SHIFT);
+}
+
+void audiohw_set_bass_cutoff(int value)
+{
+ cscodec_setbits(BTCTL, BTCTL_BASSCF_MASK,
+ (value - 1) << BTCTL_BASSCF_SHIFT);
+}
+
+void audiohw_set_treble_cutoff(int value)
+{
+ cscodec_setbits(BTCTL, BTCTL_TREBCF_MASK,
+ (value - 1) << BTCTL_TREBCF_SHIFT);
+}
+
+void audiohw_set_prescaler(int value)
+{
+ cscodec_setbits(MSTAVOL, MSTAVOL_VOLUME_MASK,
+ (-value / 5) << MSTAVOL_VOLUME_SHIFT);
+ cscodec_setbits(MSTBVOL, MSTBVOL_VOLUME_MASK,
+ (-value / 5) << MSTBVOL_VOLUME_SHIFT);
+}
+
+/* Nice shutdown of CS42L55 codec */
+void audiohw_close(void)
+{
+ audiohw_mute(true);
+ cscodec_write(HPACTL, HPACTL_HPAMUTE);
+ cscodec_write(HPBCTL, HPBCTL_HPBMUTE);
+ cscodec_write(LINEACTL, LINEACTL_LINEAMUTE);
+ cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE);
+ cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
+ | PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC);
+ cscodec_reset(true);
+ cscodec_clock(false);
+ cscodec_power(false);
+}
+
+/* Note: Disable output before calling this function */
+void audiohw_set_frequency(int fsel)
+{
+ if (fsel == HW_FREQ_8) cscodec_write(CLKCTL2, CLKCTL2_8000HZ);
+ else if (fsel == HW_FREQ_11) cscodec_write(CLKCTL2, CLKCTL2_11025HZ);
+ else if (fsel == HW_FREQ_12) cscodec_write(CLKCTL2, CLKCTL2_12000HZ);
+ else if (fsel == HW_FREQ_16) cscodec_write(CLKCTL2, CLKCTL2_16000HZ);
+ else if (fsel == HW_FREQ_22) cscodec_write(CLKCTL2, CLKCTL2_22050HZ);
+ else if (fsel == HW_FREQ_24) cscodec_write(CLKCTL2, CLKCTL2_24000HZ);
+ else if (fsel == HW_FREQ_32) cscodec_write(CLKCTL2, CLKCTL2_32000HZ);
+ else if (fsel == HW_FREQ_44) cscodec_write(CLKCTL2, CLKCTL2_44100HZ);
+ else if (fsel == HW_FREQ_48) cscodec_write(CLKCTL2, CLKCTL2_48000HZ);
+}
+
+#ifdef HAVE_RECORDING
+//TODO: Implement
+#endif /* HAVE_RECORDING */
diff --git a/firmware/drivers/audio/dac3550a.c b/firmware/drivers/audio/dac3550a.c
index e13602e481..9c6dfbb292 100644
--- a/firmware/drivers/audio/dac3550a.c
+++ b/firmware/drivers/audio/dac3550a.c
@@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
- * $Id: dac.c 17847 2008-06-28 18:10:04Z bagder $
+ * $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*
diff --git a/firmware/export/ata-defines.h b/firmware/export/ata-defines.h
index 1650c9fa47..70249ed0a0 100644
--- a/firmware/export/ata-defines.h
+++ b/firmware/export/ata-defines.h
@@ -1,58 +1,58 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: ata.h 28951 2011-01-02 23:02:55Z theseven $
- *
- * Copyright (C) 2011 by Michael Sparmann
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __ATA_DEFINES_H__
-#define __ATA_DEFINES_H__
-
-#ifndef ATA_OUT8
-#define ATA_OUT8(reg, data) (reg) = (data)
-#endif
-#ifndef ATA_OUT16
-#define ATA_OUT16(reg, data) (reg) = (data)
-#endif
-#ifndef ATA_IN8
-#define ATA_IN8(reg) (reg)
-#endif
-#ifndef ATA_IN16
-#define ATA_IN16(reg) (reg)
-#endif
-#ifndef ATA_SWAP_IDENTIFY
-#define ATA_SWAP_IDENTIFY(word) (word)
-#endif
-
-#define STATUS_BSY 0x80
-#define STATUS_RDY 0x40
-#define STATUS_DRQ 0x08
-#define STATUS_ERR 0x01
-#define STATUS_DF 0x20
-#define ERROR_IDNF 0x10
-#define ERROR_ABRT 0x04
-
-#define TEST_PATTERN1 0xa5
-#define TEST_PATTERN2 0x5a
-#define TEST_PATTERN3 0xaa
-#define TEST_PATTERN4 0x55
-
-#define ATA_FEATURE ATA_ERROR
-
-#define ATA_STATUS ATA_COMMAND
-#define ATA_ALT_STATUS ATA_CONTROL
-
-#endif
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: ata.h 28951 2011-01-02 23:02:55Z theseven $
+ *
+ * Copyright (C) 2011 by Michael Sparmann
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __ATA_DEFINES_H__
+#define __ATA_DEFINES_H__
+
+#ifndef ATA_OUT8
+#define ATA_OUT8(reg, data) (reg) = (data)
+#endif
+#ifndef ATA_OUT16
+#define ATA_OUT16(reg, data) (reg) = (data)
+#endif
+#ifndef ATA_IN8
+#define ATA_IN8(reg) (reg)
+#endif
+#ifndef ATA_IN16
+#define ATA_IN16(reg) (reg)
+#endif
+#ifndef ATA_SWAP_IDENTIFY
+#define ATA_SWAP_IDENTIFY(word) (word)
+#endif
+
+#define STATUS_BSY 0x80
+#define STATUS_RDY 0x40
+#define STATUS_DRQ 0x08
+#define STATUS_ERR 0x01
+#define STATUS_DF 0x20
+#define ERROR_IDNF 0x10
+#define ERROR_ABRT 0x04
+
+#define TEST_PATTERN1 0xa5
+#define TEST_PATTERN2 0x5a
+#define TEST_PATTERN3 0xaa
+#define TEST_PATTERN4 0x55
+
+#define ATA_FEATURE ATA_ERROR
+
+#define ATA_STATUS ATA_COMMAND
+#define ATA_ALT_STATUS ATA_CONTROL
+
+#endif
diff --git a/firmware/export/config/rk27generic.h b/firmware/export/config/rk27generic.h
index b2c74bd937..d7b63f0ac2 100644
--- a/firmware/export/config/rk27generic.h
+++ b/firmware/export/config/rk27generic.h
@@ -1,189 +1,189 @@
-/*
- * This config file is for Rockchip rk27xx reference design
- */
-#define TARGET_TREE /* this target is using the target tree system */
-
-/* For Rolo and boot loader */
-#define MODEL_NUMBER 78
-
-#define MODEL_NAME "Rockchip 27xx generic"
-
-/* define this if you have recording possibility */
-/* #define HAVE_RECORDING */
-
-/* Define bitmask of input sources - recordable bitmask can be defined
- explicitly if different */
-/* #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_FM) */
-
-/* define the bitmask of hardware sample rates */
-#define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
- | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
- | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
-
-/* define the bitmask of recording sample rates */
-#define REC_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
- | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
- | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
-
-/* define this if you have a bitmap LCD display */
-#define HAVE_LCD_BITMAP
-
-/* define this if you can flip your LCD */
-/* #define HAVE_LCD_FLIP */
-
-/* define this if you have a colour LCD */
-#define HAVE_LCD_COLOR
-
-/* define this if you want album art for this target */
-#define HAVE_ALBUMART
-
-/* define this to enable bitmap scaling */
-#define HAVE_BMP_SCALING
-
-/* define this to enable JPEG decoding */
-#define HAVE_JPEG
-
-/* define this if you can invert the colours on your LCD */
-/* #define HAVE_LCD_INVERT */
-
-/* define this if you have access to the quickscreen */
-#define HAVE_QUICKSCREEN
-
-/* define this if you have access to the pitchscreen */
-#define HAVE_PITCHSCREEN
-
-/* define this if you would like tagcache to build on this target */
-#define HAVE_TAGCACHE
-
-/* define this if you have a flash memory storage */
-#define HAVE_FLASH_STORAGE
-
-#define CONFIG_STORAGE (STORAGE_SD | STORAGE_NAND)
-
-#define CONFIG_NAND NAND_RK27XX
-#define HAVE_SW_TONE_CONTROLS
-
-/* commented for now */
-/* #define HAVE_HOTSWAP */
-
-#define NUM_DRIVES 2
-#define SECTOR_SIZE 512
-
-/* for small(ish) SD cards */
-#define HAVE_FAT16SUPPORT
-
-/* LCD dimensions */
-#define LCD_WIDTH 400
-#define LCD_HEIGHT 240
-#define LCD_DEPTH 16 /* pseudo 262.144 colors */
-#define LCD_PIXELFORMAT RGB565 /* rgb565 */
-
-/* Define this if the LCD can shut down */
-/* #define HAVE_LCD_SHUTDOWN */
-
-/* Define this if your LCD can be enabled/disabled */
-/* #define HAVE_LCD_ENABLE */
-
-/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
- should be defined as well. */
-#ifndef BOOTLOADER
-/* TODO: #define HAVE_LCD_SLEEP */
-/* TODO: #define HAVE_LCD_SLEEP_SETTING */
-#endif
-
-#define CONFIG_KEYPAD RK27XX_GENERIC_PAD
-
-/* Define this to enable morse code input */
-#define HAVE_MORSE_INPUT
-
-/* Define this if you do software codec */
-#define CONFIG_CODEC SWCODEC
-
-/* define this if you have a real-time clock */
-/* #define CONFIG_RTC RTC_NANO2G */
-
-/* Define if the device can wake from an RTC alarm */
-/* #define HAVE_RTC_ALARM */
-
-#define CONFIG_LCD LCD_SPFD5420A
-
-/* Define the type of audio codec */
-#define HAVE_RK27XX_CODEC
-
-/* #define HAVE_PCM_DMA_ADDRESS */
-
-/* Define this for LCD backlight available */
-#define HAVE_BACKLIGHT
-#define HAVE_BACKLIGHT_BRIGHTNESS
-#define MIN_BRIGHTNESS_SETTING 0
-#define MAX_BRIGHTNESS_SETTING 31
-#define DEFAULT_BRIGHTNESS_SETTING 20
-#define CONFIG_BACKLIGHT_FADING BACKLIGHT_FADING_SW_HW_REG
-
-/* Define this if you have a software controlled poweroff */
-#define HAVE_SW_POWEROFF
-
-/* The number of bytes reserved for loadable codecs */
-#define CODEC_SIZE 0x100000
-
-/* The number of bytes reserved for loadable plugins */
-#define PLUGIN_BUFFER_SIZE 0x80000
-
-/* TODO: Figure out real values */
-#define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */
-#define BATTERY_CAPACITY_MIN 300 /* min. capacity selectable */
-#define BATTERY_CAPACITY_MAX 500 /* max. capacity selectable */
-#define BATTERY_CAPACITY_INC 10 /* capacity increment */
-#define BATTERY_TYPES_COUNT 1 /* only one type */
-
-/* Hardware controlled charging with monitoring */
-#define CONFIG_CHARGING CHARGING_MONITOR
-
-/* define current usage levels */
-/* TODO: #define CURRENT_NORMAL
- * TODO: #define CURRENT_BACKLIGHT 23
- */
-
-/* define this if the unit can be powered or charged via USB */
-#define HAVE_USB_POWER
-
-/* USB On-the-go */
-#define CONFIG_USBOTG USBOTG_RK27XX
-
-/* enable these for the experimental usb stack */
-#define HAVE_USBSTACK
-
-#define USE_ROCKBOX_USB
-#define USB_VENDOR_ID 0x071b
-#define USB_PRODUCT_ID 0x3202
-#define HAVE_BOOTLOADER_USB_MODE
-
-/* Define this if your LCD can set contrast */
-/* #define HAVE_LCD_CONTRAST */
-
-/* The exact type of CPU */
-#define CONFIG_CPU RK27XX
-
-/* I2C interface */
-#define CONFIG_I2C I2C_RK27XX
-
-/* Define this to the CPU frequency */
-#define CPU_FREQ 200000000
-
-/* define this if the hardware can be powered off while charging */
-/* #define HAVE_POWEROFF_WHILE_CHARGING */
-
-/* Offset ( in the firmware file's header ) to the file CRC */
-#define FIRMWARE_OFFSET_FILE_CRC 0
-
-/* Offset ( in the firmware file's header ) to the real data */
-#define FIRMWARE_OFFSET_FILE_DATA 8
-
-#define STORAGE_NEEDS_ALIGN
-
-/* Define this if you have adjustable CPU frequency */
-/* #define HAVE_ADJUSTABLE_CPU_FREQ */
-
-#define BOOTFILE_EXT "rk27"
-#define BOOTFILE "rockbox." BOOTFILE_EXT
-#define BOOTDIR "/.rockbox"
+/*
+ * This config file is for Rockchip rk27xx reference design
+ */
+#define TARGET_TREE /* this target is using the target tree system */
+
+/* For Rolo and boot loader */
+#define MODEL_NUMBER 78
+
+#define MODEL_NAME "Rockchip 27xx generic"
+
+/* define this if you have recording possibility */
+/* #define HAVE_RECORDING */
+
+/* Define bitmask of input sources - recordable bitmask can be defined
+ explicitly if different */
+/* #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_FM) */
+
+/* define the bitmask of hardware sample rates */
+#define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
+ | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
+ | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
+
+/* define the bitmask of recording sample rates */
+#define REC_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
+ | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
+ | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
+
+/* define this if you have a bitmap LCD display */
+#define HAVE_LCD_BITMAP
+
+/* define this if you can flip your LCD */
+/* #define HAVE_LCD_FLIP */
+
+/* define this if you have a colour LCD */
+#define HAVE_LCD_COLOR
+
+/* define this if you want album art for this target */
+#define HAVE_ALBUMART
+
+/* define this to enable bitmap scaling */
+#define HAVE_BMP_SCALING
+
+/* define this to enable JPEG decoding */
+#define HAVE_JPEG
+
+/* define this if you can invert the colours on your LCD */
+/* #define HAVE_LCD_INVERT */
+
+/* define this if you have access to the quickscreen */
+#define HAVE_QUICKSCREEN
+
+/* define this if you have access to the pitchscreen */
+#define HAVE_PITCHSCREEN
+
+/* define this if you would like tagcache to build on this target */
+#define HAVE_TAGCACHE
+
+/* define this if you have a flash memory storage */
+#define HAVE_FLASH_STORAGE
+
+#define CONFIG_STORAGE (STORAGE_SD | STORAGE_NAND)
+
+#define CONFIG_NAND NAND_RK27XX
+#define HAVE_SW_TONE_CONTROLS
+
+/* commented for now */
+/* #define HAVE_HOTSWAP */
+
+#define NUM_DRIVES 2
+#define SECTOR_SIZE 512
+
+/* for small(ish) SD cards */
+#define HAVE_FAT16SUPPORT
+
+/* LCD dimensions */
+#define LCD_WIDTH 400
+#define LCD_HEIGHT 240
+#define LCD_DEPTH 16 /* pseudo 262.144 colors */
+#define LCD_PIXELFORMAT RGB565 /* rgb565 */
+
+/* Define this if the LCD can shut down */
+/* #define HAVE_LCD_SHUTDOWN */
+
+/* Define this if your LCD can be enabled/disabled */
+/* #define HAVE_LCD_ENABLE */
+
+/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
+ should be defined as well. */
+#ifndef BOOTLOADER
+/* TODO: #define HAVE_LCD_SLEEP */
+/* TODO: #define HAVE_LCD_SLEEP_SETTING */
+#endif
+
+#define CONFIG_KEYPAD RK27XX_GENERIC_PAD
+
+/* Define this to enable morse code input */
+#define HAVE_MORSE_INPUT
+
+/* Define this if you do software codec */
+#define CONFIG_CODEC SWCODEC
+
+/* define this if you have a real-time clock */
+/* #define CONFIG_RTC RTC_NANO2G */
+
+/* Define if the device can wake from an RTC alarm */
+/* #define HAVE_RTC_ALARM */
+
+#define CONFIG_LCD LCD_SPFD5420A
+
+/* Define the type of audio codec */
+#define HAVE_RK27XX_CODEC
+
+/* #define HAVE_PCM_DMA_ADDRESS */
+
+/* Define this for LCD backlight available */
+#define HAVE_BACKLIGHT
+#define HAVE_BACKLIGHT_BRIGHTNESS
+#define MIN_BRIGHTNESS_SETTING 0
+#define MAX_BRIGHTNESS_SETTING 31
+#define DEFAULT_BRIGHTNESS_SETTING 20
+#define CONFIG_BACKLIGHT_FADING BACKLIGHT_FADING_SW_HW_REG
+
+/* Define this if you have a software controlled poweroff */
+#define HAVE_SW_POWEROFF
+
+/* The number of bytes reserved for loadable codecs */
+#define CODEC_SIZE 0x100000
+
+/* The number of bytes reserved for loadable plugins */
+#define PLUGIN_BUFFER_SIZE 0x80000
+
+/* TODO: Figure out real values */
+#define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */
+#define BATTERY_CAPACITY_MIN 300 /* min. capacity selectable */
+#define BATTERY_CAPACITY_MAX 500 /* max. capacity selectable */
+#define BATTERY_CAPACITY_INC 10 /* capacity increment */
+#define BATTERY_TYPES_COUNT 1 /* only one type */
+
+/* Hardware controlled charging with monitoring */
+#define CONFIG_CHARGING CHARGING_MONITOR
+
+/* define current usage levels */
+/* TODO: #define CURRENT_NORMAL
+ * TODO: #define CURRENT_BACKLIGHT 23
+ */
+
+/* define this if the unit can be powered or charged via USB */
+#define HAVE_USB_POWER
+
+/* USB On-the-go */
+#define CONFIG_USBOTG USBOTG_RK27XX
+
+/* enable these for the experimental usb stack */
+#define HAVE_USBSTACK
+
+#define USE_ROCKBOX_USB
+#define USB_VENDOR_ID 0x071b
+#define USB_PRODUCT_ID 0x3202
+#define HAVE_BOOTLOADER_USB_MODE
+
+/* Define this if your LCD can set contrast */
+/* #define HAVE_LCD_CONTRAST */
+
+/* The exact type of CPU */
+#define CONFIG_CPU RK27XX
+
+/* I2C interface */
+#define CONFIG_I2C I2C_RK27XX
+
+/* Define this to the CPU frequency */
+#define CPU_FREQ 200000000
+
+/* define this if the hardware can be powered off while charging */
+/* #define HAVE_POWEROFF_WHILE_CHARGING */
+
+/* Offset ( in the firmware file's header ) to the file CRC */
+#define FIRMWARE_OFFSET_FILE_CRC 0
+
+/* Offset ( in the firmware file's header ) to the real data */
+#define FIRMWARE_OFFSET_FILE_DATA 8
+
+#define STORAGE_NEEDS_ALIGN
+
+/* Define this if you have adjustable CPU frequency */
+/* #define HAVE_ADJUSTABLE_CPU_FREQ */
+
+#define BOOTFILE_EXT "rk27"
+#define BOOTFILE "rockbox." BOOTFILE_EXT
+#define BOOTDIR "/.rockbox"
diff --git a/firmware/export/dac3550a.h b/firmware/export/dac3550a.h
index 3744b221ed..23c4db9cbc 100644
--- a/firmware/export/dac3550a.h
+++ b/firmware/export/dac3550a.h
@@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
- * $Id: dac.h 24158 2010-01-03 11:31:14Z Buschel $
+ * $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*
diff --git a/firmware/export/mascodec.h b/firmware/export/mascodec.h
index 82a71e30c8..f10dc3f1ca 100644
--- a/firmware/export/mascodec.h
+++ b/firmware/export/mascodec.h
@@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
- * $Id: mas.h 24154 2010-01-03 10:27:43Z Buschel $
+ * $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*
diff --git a/firmware/export/s5l8702.h b/firmware/export/s5l8702.h
index 338d7a5e16..31e6a63dbc 100644
--- a/firmware/export/s5l8702.h
+++ b/firmware/export/s5l8702.h
@@ -1,830 +1,830 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: s5l8700.h 28791 2010-12-11 09:39:33Z Buschel $
- *
- * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-
-#ifndef __S5L8702_H__
-#define __S5L8702_H__
-
-#include <inttypes.h>
-
-#define REG8_PTR_T volatile uint8_t *
-#define REG16_PTR_T volatile uint16_t *
-#define REG32_PTR_T volatile uint32_t *
-
-#define TIMER_FREQ 54000000
-
-#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
-
-#define DRAM_ORIG 0x08000000
-#define IRAM_ORIG 0
-
-#define DRAM_SIZE (MEMORYSIZE * 0x100000)
-#define IRAM_SIZE 0x40000
-
-#define TTB_SIZE 0x4000
-#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
-
-/////SYSTEM CONTROLLER/////
-#define CLKCON0 (*((volatile uint32_t*)(0x3C500000)))
-#define CLKCON1 (*((volatile uint32_t*)(0x3C500004)))
-#define CLKCON2 (*((volatile uint32_t*)(0x3C500008)))
-#define CLKCON3 (*((volatile uint32_t*)(0x3C50000C)))
-#define CLKCON4 (*((volatile uint32_t*)(0x3C500010)))
-#define CLKCON5 (*((volatile uint32_t*)(0x3C500014)))
-#define PLL0PMS (*((volatile uint32_t*)(0x3C500020)))
-#define PLL1PMS (*((volatile uint32_t*)(0x3C500024)))
-#define PLL2PMS (*((volatile uint32_t*)(0x3C500028)))
-#define PLL0LCNT (*((volatile uint32_t*)(0x3C500030)))
-#define PLL1LCNT (*((volatile uint32_t*)(0x3C500034)))
-#define PLL2LCNT (*((volatile uint32_t*)(0x3C500038)))
-#define PLLLOCK (*((volatile uint32_t*)(0x3C500040)))
-#define PLLMODE (*((volatile uint32_t*)(0x3C500044)))
-#define PWRCON(i) (*((uint32_t volatile*)(0x3C500000 \
- + ((i) == 4 ? 0x6C : \
- ((i) == 3 ? 0x68 : \
- ((i) == 2 ? 0x58 : \
- ((i) == 1 ? 0x4C : \
- 0x48)))))))
-
-
-/////TIMER/////
-#define TACON (*((uint32_t volatile*)(0x3C700000)))
-#define TACMD (*((uint32_t volatile*)(0x3C700004)))
-#define TADATA0 (*((uint32_t volatile*)(0x3C700008)))
-#define TADATA1 (*((uint32_t volatile*)(0x3C70000C)))
-#define TAPRE (*((uint32_t volatile*)(0x3C700010)))
-#define TACNT (*((uint32_t volatile*)(0x3C700014)))
-#define TBCON (*((uint32_t volatile*)(0x3C700020)))
-#define TBCMD (*((uint32_t volatile*)(0x3C700024)))
-#define TBDATA0 (*((uint32_t volatile*)(0x3C700028)))
-#define TBDATA1 (*((uint32_t volatile*)(0x3C70002C)))
-#define TBPRE (*((uint32_t volatile*)(0x3C700030)))
-#define TBCNT (*((uint32_t volatile*)(0x3C700034)))
-#define TCCON (*((uint32_t volatile*)(0x3C700040)))
-#define TCCMD (*((uint32_t volatile*)(0x3C700044)))
-#define TCDATA0 (*((uint32_t volatile*)(0x3C700048)))
-#define TCDATA1 (*((uint32_t volatile*)(0x3C70004C)))
-#define TCPRE (*((uint32_t volatile*)(0x3C700050)))
-#define TCCNT (*((uint32_t volatile*)(0x3C700054)))
-#define TDCON (*((uint32_t volatile*)(0x3C700060)))
-#define TDCMD (*((uint32_t volatile*)(0x3C700064)))
-#define TDDATA0 (*((uint32_t volatile*)(0x3C700068)))
-#define TDDATA1 (*((uint32_t volatile*)(0x3C70006C)))
-#define TDPRE (*((uint32_t volatile*)(0x3C700070)))
-#define TDCNT (*((uint32_t volatile*)(0x3C700074)))
-#define TECON (*((uint32_t volatile*)(0x3C7000A0)))
-#define TECMD (*((uint32_t volatile*)(0x3C7000A4)))
-#define TEDATA0 (*((uint32_t volatile*)(0x3C7000A8)))
-#define TEDATA1 (*((uint32_t volatile*)(0x3C7000AC)))
-#define TEPRE (*((uint32_t volatile*)(0x3C7000B0)))
-#define TECNT (*((uint32_t volatile*)(0x3C7000B4)))
-#define TFCON (*((uint32_t volatile*)(0x3C7000C0)))
-#define TFCMD (*((uint32_t volatile*)(0x3C7000C4)))
-#define TFDATA0 (*((uint32_t volatile*)(0x3C7000C8)))
-#define TFDATA1 (*((uint32_t volatile*)(0x3C7000CC)))
-#define TFPRE (*((uint32_t volatile*)(0x3C7000D0)))
-#define TFCNT (*((uint32_t volatile*)(0x3C7000D4)))
-#define TGCON (*((uint32_t volatile*)(0x3C7000E0)))
-#define TGCMD (*((uint32_t volatile*)(0x3C7000E4)))
-#define TGDATA0 (*((uint32_t volatile*)(0x3C7000E8)))
-#define TGDATA1 (*((uint32_t volatile*)(0x3C7000EC)))
-#define TGPRE (*((uint32_t volatile*)(0x3C7000F0)))
-#define TGCNT (*((uint32_t volatile*)(0x3C7000F4)))
-#define THCON (*((uint32_t volatile*)(0x3C700100)))
-#define THCMD (*((uint32_t volatile*)(0x3C700104)))
-#define THDATA0 (*((uint32_t volatile*)(0x3C700108)))
-#define THDATA1 (*((uint32_t volatile*)(0x3C70010C)))
-#define THPRE (*((uint32_t volatile*)(0x3C700110)))
-#define THCNT (*((uint32_t volatile*)(0x3C700114)))
-#define USEC_TIMER TECNT
-
-
-/////USB/////
-#define OTGBASE 0x38400000
-#define PHYBASE 0x3C400000
-#define SYNOPSYSOTG_CLOCK 0
-#define SYNOPSYSOTG_AHBCFG 0x2B
-
-
-/////I2C/////
-#define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
-#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
-#define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
-#define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
-
-
-/////INTERRUPT CONTROLLERS/////
-#define VICIRQSTATUS(v) (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v))))
-#define VICFIQSTATUS(v) (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v))))
-#define VICRAWINTR(v) (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v))))
-#define VICINTSELECT(v) (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v))))
-#define VICINTENABLE(v) (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v))))
-#define VICINTENCLEAR(v) (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v))))
-#define VICSOFTINT(v) (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v))))
-#define VICSOFTINTCLEAR(v) (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v))))
-#define VICPROTECTION(v) (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v))))
-#define VICSWPRIORITYMASK(v) (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v))))
-#define VICPRIORITYDAISY(v) (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v))))
-#define VICVECTADDR(v, i) (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
-#define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
-#define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v))))
-#define VIC0IRQSTATUS (*((uint32_t volatile*)(0x38E00000)))
-#define VIC0FIQSTATUS (*((uint32_t volatile*)(0x38E00004)))
-#define VIC0RAWINTR (*((uint32_t volatile*)(0x38E00008)))
-#define VIC0INTSELECT (*((uint32_t volatile*)(0x38E0000C)))
-#define VIC0INTENABLE (*((uint32_t volatile*)(0x38E00010)))
-#define VIC0INTENCLEAR (*((uint32_t volatile*)(0x38E00014)))
-#define VIC0SOFTINT (*((uint32_t volatile*)(0x38E00018)))
-#define VIC0SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0001C)))
-#define VIC0PROTECTION (*((uint32_t volatile*)(0x38E00020)))
-#define VIC0SWPRIORITYMASK (*((uint32_t volatile*)(0x38E00024)))
-#define VIC0PRIORITYDAISY (*((uint32_t volatile*)(0x38E00028)))
-#define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i))))
-#define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100)))
-#define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104)))
-#define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108)))
-#define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C)))
-#define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110)))
-#define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114)))
-#define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118)))
-#define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C)))
-#define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120)))
-#define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124)))
-#define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128)))
-#define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C)))
-#define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130)))
-#define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134)))
-#define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138)))
-#define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C)))
-#define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140)))
-#define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144)))
-#define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148)))
-#define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C)))
-#define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150)))
-#define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154)))
-#define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158)))
-#define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C)))
-#define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160)))
-#define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164)))
-#define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168)))
-#define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C)))
-#define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170)))
-#define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174)))
-#define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178)))
-#define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C)))
-#define VIC0VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E00200 + 4 * (i))))
-#define VIC0VECTPRIORITY0 (*((uint32_t volatile*)(0x38E00200)))
-#define VIC0VECTPRIORITY1 (*((uint32_t volatile*)(0x38E00204)))
-#define VIC0VECTPRIORITY2 (*((uint32_t volatile*)(0x38E00208)))
-#define VIC0VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0020C)))
-#define VIC0VECTPRIORITY4 (*((uint32_t volatile*)(0x38E00210)))
-#define VIC0VECTPRIORITY5 (*((uint32_t volatile*)(0x38E00214)))
-#define VIC0VECTPRIORITY6 (*((uint32_t volatile*)(0x38E00218)))
-#define VIC0VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0021C)))
-#define VIC0VECTPRIORITY8 (*((uint32_t volatile*)(0x38E00220)))
-#define VIC0VECTPRIORITY9 (*((uint32_t volatile*)(0x38E00224)))
-#define VIC0VECTPRIORITY10 (*((uint32_t volatile*)(0x38E00228)))
-#define VIC0VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0022C)))
-#define VIC0VECTPRIORITY12 (*((uint32_t volatile*)(0x38E00230)))
-#define VIC0VECTPRIORITY13 (*((uint32_t volatile*)(0x38E00234)))
-#define VIC0VECTPRIORITY14 (*((uint32_t volatile*)(0x38E00238)))
-#define VIC0VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0023C)))
-#define VIC0VECTPRIORITY16 (*((uint32_t volatile*)(0x38E00240)))
-#define VIC0VECTPRIORITY17 (*((uint32_t volatile*)(0x38E00244)))
-#define VIC0VECTPRIORITY18 (*((uint32_t volatile*)(0x38E00248)))
-#define VIC0VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0024C)))
-#define VIC0VECTPRIORITY20 (*((uint32_t volatile*)(0x38E00250)))
-#define VIC0VECTPRIORITY21 (*((uint32_t volatile*)(0x38E00254)))
-#define VIC0VECTPRIORITY22 (*((uint32_t volatile*)(0x38E00258)))
-#define VIC0VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0025C)))
-#define VIC0VECTPRIORITY24 (*((uint32_t volatile*)(0x38E00260)))
-#define VIC0VECTPRIORITY25 (*((uint32_t volatile*)(0x38E00264)))
-#define VIC0VECTPRIORITY26 (*((uint32_t volatile*)(0x38E00268)))
-#define VIC0VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0026C)))
-#define VIC0VECTPRIORITY28 (*((uint32_t volatile*)(0x38E00270)))
-#define VIC0VECTPRIORITY29 (*((uint32_t volatile*)(0x38E00274)))
-#define VIC0VECTPRIORITY30 (*((uint32_t volatile*)(0x38E00278)))
-#define VIC0VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0027C)))
-#define VIC0ADDRESS (*((void* volatile*)(0x38E00F00)))
-#define VIC1IRQSTATUS (*((uint32_t volatile*)(0x38E01000)))
-#define VIC1FIQSTATUS (*((uint32_t volatile*)(0x38E01004)))
-#define VIC1RAWINTR (*((uint32_t volatile*)(0x38E01008)))
-#define VIC1INTSELECT (*((uint32_t volatile*)(0x38E0100C)))
-#define VIC1INTENABLE (*((uint32_t volatile*)(0x38E01010)))
-#define VIC1INTENCLEAR (*((uint32_t volatile*)(0x38E01014)))
-#define VIC1SOFTINT (*((uint32_t volatile*)(0x38E01018)))
-#define VIC1SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0101C)))
-#define VIC1PROTECTION (*((uint32_t volatile*)(0x38E01020)))
-#define VIC1SWPRIORITYMASK (*((uint32_t volatile*)(0x38E01024)))
-#define VIC1PRIORITYDAISY (*((uint32_t volatile*)(0x38E01028)))
-#define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i))))
-#define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100)))
-#define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104)))
-#define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108)))
-#define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C)))
-#define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110)))
-#define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114)))
-#define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118)))
-#define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C)))
-#define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120)))
-#define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124)))
-#define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128)))
-#define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C)))
-#define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130)))
-#define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134)))
-#define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138)))
-#define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C)))
-#define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140)))
-#define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144)))
-#define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148)))
-#define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C)))
-#define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150)))
-#define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154)))
-#define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158)))
-#define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C)))
-#define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160)))
-#define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164)))
-#define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168)))
-#define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C)))
-#define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170)))
-#define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174)))
-#define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178)))
-#define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C)))
-#define VIC1VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E01200 + 4 * (i))))
-#define VIC1VECTPRIORITY0 (*((uint32_t volatile*)(0x38E01200)))
-#define VIC1VECTPRIORITY1 (*((uint32_t volatile*)(0x38E01204)))
-#define VIC1VECTPRIORITY2 (*((uint32_t volatile*)(0x38E01208)))
-#define VIC1VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0120C)))
-#define VIC1VECTPRIORITY4 (*((uint32_t volatile*)(0x38E01210)))
-#define VIC1VECTPRIORITY5 (*((uint32_t volatile*)(0x38E01214)))
-#define VIC1VECTPRIORITY6 (*((uint32_t volatile*)(0x38E01218)))
-#define VIC1VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0121C)))
-#define VIC1VECTPRIORITY8 (*((uint32_t volatile*)(0x38E01220)))
-#define VIC1VECTPRIORITY9 (*((uint32_t volatile*)(0x38E01224)))
-#define VIC1VECTPRIORITY10 (*((uint32_t volatile*)(0x38E01228)))
-#define VIC1VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0122C)))
-#define VIC1VECTPRIORITY12 (*((uint32_t volatile*)(0x38E01230)))
-#define VIC1VECTPRIORITY13 (*((uint32_t volatile*)(0x38E01234)))
-#define VIC1VECTPRIORITY14 (*((uint32_t volatile*)(0x38E01238)))
-#define VIC1VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0123C)))
-#define VIC1VECTPRIORITY16 (*((uint32_t volatile*)(0x38E01240)))
-#define VIC1VECTPRIORITY17 (*((uint32_t volatile*)(0x38E01244)))
-#define VIC1VECTPRIORITY18 (*((uint32_t volatile*)(0x38E01248)))
-#define VIC1VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0124C)))
-#define VIC1VECTPRIORITY20 (*((uint32_t volatile*)(0x38E01250)))
-#define VIC1VECTPRIORITY21 (*((uint32_t volatile*)(0x38E01254)))
-#define VIC1VECTPRIORITY22 (*((uint32_t volatile*)(0x38E01258)))
-#define VIC1VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0125C)))
-#define VIC1VECTPRIORITY24 (*((uint32_t volatile*)(0x38E01260)))
-#define VIC1VECTPRIORITY25 (*((uint32_t volatile*)(0x38E01264)))
-#define VIC1VECTPRIORITY26 (*((uint32_t volatile*)(0x38E01268)))
-#define VIC1VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0126C)))
-#define VIC1VECTPRIORITY28 (*((uint32_t volatile*)(0x38E01270)))
-#define VIC1VECTPRIORITY29 (*((uint32_t volatile*)(0x38E01274)))
-#define VIC1VECTPRIORITY30 (*((uint32_t volatile*)(0x38E01278)))
-#define VIC1VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0127C)))
-#define VIC1ADDRESS (*((void* volatile*)(0x38E01F00)))
-
-
-/////GPIO/////
-#define PCON(i) (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5))))
-#define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
-#define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
-#define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
-#define PCON0 (*((uint32_t volatile*)(0x3cf00000)))
-#define PDAT0 (*((uint32_t volatile*)(0x3cf00004)))
-#define PCON1 (*((uint32_t volatile*)(0x3cf00020)))
-#define PDAT1 (*((uint32_t volatile*)(0x3cf00024)))
-#define PCON2 (*((uint32_t volatile*)(0x3cf00040)))
-#define PDAT2 (*((uint32_t volatile*)(0x3cf00044)))
-#define PCON3 (*((uint32_t volatile*)(0x3cf00060)))
-#define PDAT3 (*((uint32_t volatile*)(0x3cf00064)))
-#define PCON4 (*((uint32_t volatile*)(0x3cf00080)))
-#define PDAT4 (*((uint32_t volatile*)(0x3cf00084)))
-#define PCON5 (*((uint32_t volatile*)(0x3cf000a0)))
-#define PDAT5 (*((uint32_t volatile*)(0x3cf000a4)))
-#define PCON6 (*((uint32_t volatile*)(0x3cf000c0)))
-#define PDAT6 (*((uint32_t volatile*)(0x3cf000c4)))
-#define PCON7 (*((uint32_t volatile*)(0x3cf000e0)))
-#define PDAT7 (*((uint32_t volatile*)(0x3cf000e4)))
-#define PCON8 (*((uint32_t volatile*)(0x3cf00100)))
-#define PDAT8 (*((uint32_t volatile*)(0x3cf00104)))
-#define PCON9 (*((uint32_t volatile*)(0x3cf00120)))
-#define PDAT9 (*((uint32_t volatile*)(0x3cf00124)))
-#define PCONA (*((uint32_t volatile*)(0x3cf00140)))
-#define PDATA (*((uint32_t volatile*)(0x3cf00144)))
-#define PCONB (*((uint32_t volatile*)(0x3cf00160)))
-#define PDATB (*((uint32_t volatile*)(0x3cf00164)))
-#define PCONC (*((uint32_t volatile*)(0x3cf00180)))
-#define PDATC (*((uint32_t volatile*)(0x3cf00184)))
-#define PCOND (*((uint32_t volatile*)(0x3cf001a0)))
-#define PDATD (*((uint32_t volatile*)(0x3cf001a4)))
-#define PCONE (*((uint32_t volatile*)(0x3cf001c0)))
-#define PDATE (*((uint32_t volatile*)(0x3cf001c4)))
-#define PCONF (*((uint32_t volatile*)(0x3cf001e0)))
-#define PDATF (*((uint32_t volatile*)(0x3cf001e4)))
-#define GPIOCMD (*((uint32_t volatile*)(0x3cf00200)))
-
-
-/////SPI/////
-#define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \
- (i) == 1 ? 0x3ce00000 : \
- 0x3c300000)
-#define SPICLKGATE(i) ((i) == 2 ? 0x2f : \
- (i) == 1 ? 0x2b : \
- 0x22)
-#define SPIDMA(i) ((i) == 2 ? 0xd : \
- (i) == 1 ? 0xf : \
- 0x5)
-#define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i))))
-#define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
-#define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
-#define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
-#define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
-#define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
-#define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
-#define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
-#define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38)))
-
-
-/////AES/////
-#define AESCONTROL (*((uint32_t volatile*)(0x38c00000)))
-#define AESGO (*((uint32_t volatile*)(0x38c00004)))
-#define AESUNKREG0 (*((uint32_t volatile*)(0x38c00008)))
-#define AESSTATUS (*((uint32_t volatile*)(0x38c0000c)))
-#define AESUNKREG1 (*((uint32_t volatile*)(0x38c00010)))
-#define AESKEYLEN (*((uint32_t volatile*)(0x38c00014)))
-#define AESOUTSIZE (*((uint32_t volatile*)(0x38c00018)))
-#define AESOUTADDR (*((void* volatile*)(0x38c00020)))
-#define AESINSIZE (*((uint32_t volatile*)(0x38c00024)))
-#define AESINADDR (*((const void* volatile*)(0x38c00028)))
-#define AESAUXSIZE (*((uint32_t volatile*)(0x38c0002c)))
-#define AESAUXADDR (*((void* volatile*)(0x38c00030)))
-#define AESSIZE3 (*((uint32_t volatile*)(0x38c00034)))
-#define AESKEY ((uint32_t volatile*)(0x38c0004c))
-#define AESTYPE (*((uint32_t volatile*)(0x38c0006c)))
-#define AESIV ((uint32_t volatile*)(0x38c00074))
-#define AESTYPE2 (*((uint32_t volatile*)(0x38c00088)))
-#define AESUNKREG2 (*((uint32_t volatile*)(0x38c0008c)))
-
-
-/////SHA1/////
-#define SHA1CONFIG (*((uint32_t volatile*)(0x38000000)))
-#define SHA1RESET (*((uint32_t volatile*)(0x38000004)))
-#define SHA1RESULT ((uint32_t volatile*)(0x38000020))
-#define SHA1DATAIN ((uint32_t volatile*)(0x38000040))
-
-
-/////DMA/////
-#ifndef ASM
-struct dma_lli
-{
- const void* srcaddr;
- void* dstaddr;
- const struct dma_lli* nextlli;
- uint32_t control;
-};
-#endif
-#define DMACINTSTS(d) (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d))))
-#define DMACINTTCSTS(d) (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d))))
-#define DMACINTTCCLR(d) (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d))))
-#define DMACINTERRSTS(d) (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d))))
-#define DMACINTERRCLR(d) (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d))))
-#define DMACRAWINTTCSTS(d) (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d))))
-#define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d))))
-#define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d))))
-#define DMACSOFTBREQ(d) (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d))))
-#define DMACSOFTSREQ(d) (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d))))
-#define DMACSOFTLBREQ(d) (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d))))
-#define DMACSOFTLSREQ(d) (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d))))
-#define DMACCONFIG(d) (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d))))
-#define DMACSYNC(d) (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d))))
-#define DMACCLLI(d, c) (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCSRCADDR(d, c) (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCNEXTLLI(d, c) (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCCONTROL(d, c) (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCCONFIG(d, c) (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMAC0INTSTS (*((uint32_t volatile*)(0x38200000)))
-#define DMAC0INTTCSTS (*((uint32_t volatile*)(0x38200004)))
-#define DMAC0INTTCCLR (*((uint32_t volatile*)(0x38200008)))
-#define DMAC0INTERRSTS (*((uint32_t volatile*)(0x3820000c)))
-#define DMAC0INTERRCLR (*((uint32_t volatile*)(0x38200010)))
-#define DMAC0RAWINTTCSTS (*((uint32_t volatile*)(0x38200014)))
-#define DMAC0RAWINTERRSTS (*((uint32_t volatile*)(0x38200018)))
-#define DMAC0ENABLEDCHANS (*((uint32_t volatile*)(0x3820001c)))
-#define DMAC0SOFTBREQ (*((uint32_t volatile*)(0x38200020)))
-#define DMAC0SOFTSREQ (*((uint32_t volatile*)(0x38200024)))
-#define DMAC0SOFTLBREQ (*((uint32_t volatile*)(0x38200028)))
-#define DMAC0SOFTLSREQ (*((uint32_t volatile*)(0x3820002c)))
-#define DMAC0CONFIG (*((uint32_t volatile*)(0x38200030)))
-#define DMAC0SYNC (*((uint32_t volatile*)(0x38200034)))
-#define DMAC0CLLI(c) (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c))))
-#define DMAC0CSRCADDR(c) (*((const void* volatile*)(0x38200100 + 0x20 * (c))))
-#define DMAC0CDESTADDR(c) (*((void* volatile*)(0x38200104 + 0x20 * (c))))
-#define DMAC0CNEXTLLI(c) (*((const void* volatile*)(0x38200108 + 0x20 * (c))))
-#define DMAC0CCONTROL(c) (*((uint32_t volatile*)(0x3820010c + 0x20 * (c))))
-#define DMAC0CCONFIG(c) (*((uint32_t volatile*)(0x38200110 + 0x20 * (c))))
-#define DMAC0C0LLI (*((struct dma_lli volatile*)(0x38200100)))
-#define DMAC0C0SRCADDR (*((const void* volatile*)(0x38200100)))
-#define DMAC0C0DESTADDR (*((void* volatile*)(0x38200104)))
-#define DMAC0C0NEXTLLI (*((const struct dma_lli* volatile*)(0x38200108)))
-#define DMAC0C0CONTROL (*((uint32_t volatile*)(0x3820010c)))
-#define DMAC0C0CONFIG (*((uint32_t volatile*)(0x38200110)))
-#define DMAC0C1LLI (*((struct dma_lli volatile*)(0x38200120)))
-#define DMAC0C1SRCADDR (*((const void* volatile*)(0x38200120)))
-#define DMAC0C1DESTADDR (*((void* volatile*)(0x38200124)))
-#define DMAC0C1NEXTLLI (*((const struct dma_lli* volatile*)(0x38200128)))
-#define DMAC0C1CONTROL (*((uint32_t volatile*)(0x3820012c)))
-#define DMAC0C1CONFIG (*((uint32_t volatile*)(0x38200130)))
-#define DMAC0C2LLI (*((struct dma_lli volatile*)(0x38200140)))
-#define DMAC0C2SRCADDR (*((const void* volatile*)(0x38200140)))
-#define DMAC0C2DESTADDR (*((void* volatile*)(0x38200144)))
-#define DMAC0C2NEXTLLI (*((const struct dma_lli* volatile*)(0x38200148)))
-#define DMAC0C2CONTROL (*((uint32_t volatile*)(0x3820014c)))
-#define DMAC0C2CONFIG (*((uint32_t volatile*)(0x38200150)))
-#define DMAC0C3LLI (*((struct dma_lli volatile*)(0x38200160)))
-#define DMAC0C3SRCADDR (*((const void* volatile*)(0x38200160)))
-#define DMAC0C3DESTADDR (*((void* volatile*)(0x38200164)))
-#define DMAC0C3NEXTLLI (*((const struct dma_lli* volatile*)(0x38200168)))
-#define DMAC0C3CONTROL (*((uint32_t volatile*)(0x3820016c)))
-#define DMAC0C3CONFIG (*((uint32_t volatile*)(0x38200170)))
-#define DMAC0C4LLI (*((struct dma_lli volatile*)(0x38200180)))
-#define DMAC0C4SRCADDR (*((const void* volatile*)(0x38200180)))
-#define DMAC0C4DESTADDR (*((void* volatile*)(0x38200184)))
-#define DMAC0C4NEXTLLI (*((const struct dma_lli* volatile*)(0x38200188)))
-#define DMAC0C4CONTROL (*((uint32_t volatile*)(0x3820018c)))
-#define DMAC0C4CONFIG (*((uint32_t volatile*)(0x38200190)))
-#define DMAC0C5LLI (*((struct dma_lli volatile*)(0x382001a0)))
-#define DMAC0C5SRCADDR (*((const void* volatile*)(0x382001a0)))
-#define DMAC0C5DESTADDR (*((void* volatile*)(0x382001a4)))
-#define DMAC0C5NEXTLLI (*((const struct dma_lli* volatile*)(0x382001a8)))
-#define DMAC0C5CONTROL (*((uint32_t volatile*)(0x382001ac)))
-#define DMAC0C5CONFIG (*((uint32_t volatile*)(0x382001b0)))
-#define DMAC0C6LLI (*((struct dma_lli volatile*)(0x382001c0)))
-#define DMAC0C6SRCADDR (*((const void* volatile*)(0x382001c0)))
-#define DMAC0C6DESTADDR (*((void* volatile*)(0x382001c4)))
-#define DMAC0C6NEXTLLI (*((const struct dma_lli* volatile*)(0x382001c8)))
-#define DMAC0C6CONTROL (*((uint32_t volatile*)(0x382001cc)))
-#define DMAC0C6CONFIG (*((uint32_t volatile*)(0x382001d0)))
-#define DMAC0C7LLI (*((struct dma_lli volatile*)(0x382001e0)))
-#define DMAC0C7SRCADDR (*((const void* volatile*)(0x382001e0)))
-#define DMAC0C7DESTADDR (*((void* volatile*)(0x382001e4)))
-#define DMAC0C7NEXTLLI (*((const struct dma_lli* volatile*)(0x382001e8)))
-#define DMAC0C7CONTROL (*((uint32_t volatile*)(0x382001ec)))
-#define DMAC0C7CONFIG (*((uint32_t volatile*)(0x382001f0)))
-#define DMAC1INTSTS (*((uint32_t volatile*)(0x39900000)))
-#define DMAC1INTTCSTS (*((uint32_t volatile*)(0x39900004)))
-#define DMAC1INTTCCLR (*((uint32_t volatile*)(0x39900008)))
-#define DMAC1INTERRSTS (*((uint32_t volatile*)(0x3990000c)))
-#define DMAC1INTERRCLR (*((uint32_t volatile*)(0x39900010)))
-#define DMAC1RAWINTTCSTS (*((uint32_t volatile*)(0x39900014)))
-#define DMAC1RAWINTERRSTS (*((uint32_t volatile*)(0x39900018)))
-#define DMAC1ENABLEDCHANS (*((uint32_t volatile*)(0x3990001c)))
-#define DMAC1SOFTBREQ (*((uint32_t volatile*)(0x39900020)))
-#define DMAC1SOFTSREQ (*((uint32_t volatile*)(0x39900024)))
-#define DMAC1SOFTLBREQ (*((uint32_t volatile*)(0x39900028)))
-#define DMAC1SOFTLSREQ (*((uint32_t volatile*)(0x3990002c)))
-#define DMAC1CONFIG (*((uint32_t volatile*)(0x39900030)))
-#define DMAC1SYNC (*((uint32_t volatile*)(0x39900034)))
-#define DMAC1CLLI(c) (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c))))
-#define DMAC1CSRCADDR(c) (*((const void* volatile*)(0x39900100 + 0x20 * (c))))
-#define DMAC1CDESTADDR(c) (*((void* volatile*)(0x39900104 + 0x20 * (c))))
-#define DMAC1CNEXTLLI(c) (*((const void* volatile*)(0x39900108 + 0x20 * (c))))
-#define DMAC1CCONTROL(c) (*((uint32_t volatile*)(0x3990010c + 0x20 * (c))))
-#define DMAC1CCONFIG(c) (*((uint32_t volatile*)(0x39900110 + 0x20 * (c))))
-#define DMAC1C0LLI (*((struct dma_lli volatile*)(0x39900100)))
-#define DMAC1C0SRCADDR (*((const void* volatile*)(0x39900100)))
-#define DMAC1C0DESTADDR (*((void* volatile*)(0x39900104)))
-#define DMAC1C0NEXTLLI (*((const struct dma_lli* volatile*)(0x39900108)))
-#define DMAC1C0CONTROL (*((uint32_t volatile*)(0x3990010c)))
-#define DMAC1C0CONFIG (*((uint32_t volatile*)(0x39900110)))
-#define DMAC1C1LLI (*((struct dma_lli volatile*)(0x39900120)))
-#define DMAC1C1SRCADDR (*((const void* volatile*)(0x39900120)))
-#define DMAC1C1DESTADDR (*((void* volatile*)(0x39900124)))
-#define DMAC1C1NEXTLLI (*((const struct dma_lli* volatile*)(0x39900128)))
-#define DMAC1C1CONTROL (*((uint32_t volatile*)(0x3990012c)))
-#define DMAC1C1CONFIG (*((uint32_t volatile*)(0x39900130)))
-#define DMAC1C2LLI (*((struct dma_lli volatile*)(0x39900140)))
-#define DMAC1C2SRCADDR (*((const void* volatile*)(0x39900140)))
-#define DMAC1C2DESTADDR (*((void* volatile*)(0x39900144)))
-#define DMAC1C2NEXTLLI (*((const struct dma_lli* volatile*)(0x39900148)))
-#define DMAC1C2CONTROL (*((uint32_t volatile*)(0x3990014c)))
-#define DMAC1C2CONFIG (*((uint32_t volatile*)(0x39900150)))
-#define DMAC1C3LLI (*((struct dma_lli volatile*)(0x39900160)))
-#define DMAC1C3SRCADDR (*((const void* volatile*)(0x39900160)))
-#define DMAC1C3DESTADDR (*((void* volatile*)(0x39900164)))
-#define DMAC1C3NEXTLLI (*((volatile void**)(0x39900168)))
-#define DMAC1C3CONTROL (*((uint32_t volatile*)(0x3990016c)))
-#define DMAC1C3CONFIG (*((uint32_t volatile*)(0x39900170)))
-#define DMAC1C4LLI (*((struct dma_lli volatile*)(0x39900180)))
-#define DMAC1C4SRCADDR (*((const void* volatile*)(0x39900180)))
-#define DMAC1C4DESTADDR (*((void* volatile*)(0x39900184)))
-#define DMAC1C4NEXTLLI (*((const struct dma_lli* volatile*)(0x39900188)))
-#define DMAC1C4CONTROL (*((uint32_t volatile*)(0x3990018c)))
-#define DMAC1C4CONFIG (*((uint32_t volatile*)(0x39900190)))
-#define DMAC1C5LLI (*((struct dma_lli volatile*)(0x399001a0)))
-#define DMAC1C5SRCADDR (*((const void* volatile*)(0x399001a0)))
-#define DMAC1C5DESTADDR (*((void* volatile*)(0x399001a4)))
-#define DMAC1C5NEXTLLI (*((const struct dma_lli* volatile*)(0x399001a8)))
-#define DMAC1C5CONTROL (*((uint32_t volatile*)(0x399001ac)))
-#define DMAC1C5CONFIG (*((uint32_t volatile*)(0x399001b0)))
-#define DMAC1C6LLI (*((struct dma_lli volatile*)(0x399001c0)))
-#define DMAC1C6SRCADDR (*((const void* volatile*)(0x399001c0)))
-#define DMAC1C6DESTADDR (*((void* volatile*)(0x399001c4)))
-#define DMAC1C6NEXTLLI (*((const struct dma_lli* volatile*)(0x399001c8)))
-#define DMAC1C6CONTROL (*((uint32_t volatile*)(0x399001cc)))
-#define DMAC1C6CONFIG (*((uint32_t volatile*)(0x399001d0)))
-#define DMAC1C7LLI (*((struct dma_lli volatile*)(0x399001e0)))
-#define DMAC1C7SRCADDR (*((const void* volatile*)(0x399001e0)))
-#define DMAC1C7DESTADDR (*((void* volatile*)(0x399001e4)))
-#define DMAC1C7NEXTLLI (*((const struct dma_lli* volatile*)(0x399001e8)))
-#define DMAC1C7CONTROL (*((uint32_t volatile*)(0x399001ec)))
-#define DMAC1C7CONFIG (*((uint32_t volatile*)(0x399001f0)))
-
-
-/////LCD/////
-#define LCD_BASE (0x38300000)
-#define LCD_CONFIG (*((uint32_t volatile*)(0x38300000)))
-#define LCD_WCMD (*((uint32_t volatile*)(0x38300004)))
-#define LCD_STATUS (*((uint32_t volatile*)(0x3830001c)))
-#define LCD_WDATA (*((uint32_t volatile*)(0x38300040)))
-
-
-/////ATA/////
-#define ATA_CONTROL (*((uint32_t volatile*)(0x38700000)))
-#define ATA_STATUS (*((uint32_t volatile*)(0x38700004)))
-#define ATA_COMMAND (*((uint32_t volatile*)(0x38700008)))
-#define ATA_SWRST (*((uint32_t volatile*)(0x3870000c)))
-#define ATA_IRQ (*((uint32_t volatile*)(0x38700010)))
-#define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014)))
-#define ATA_CFG (*((uint32_t volatile*)(0x38700018)))
-#define ATA_MDMA_TIME (*((uint32_t volatile*)(0x38700028)))
-#define ATA_PIO_TIME (*((uint32_t volatile*)(0x3870002c)))
-#define ATA_UDMA_TIME (*((uint32_t volatile*)(0x38700030)))
-#define ATA_XFR_NUM (*((uint32_t volatile*)(0x38700034)))
-#define ATA_XFR_CNT (*((uint32_t volatile*)(0x38700038)))
-#define ATA_TBUF_START (*((void* volatile*)(0x3870003c)))
-#define ATA_TBUF_SIZE (*((uint32_t volatile*)(0x38700040)))
-#define ATA_SBUF_START (*((void* volatile*)(0x38700044)))
-#define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048)))
-#define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c)))
-#define ATA_CADR_SBUF (*((void* volatile*)(0x38700050)))
-#define ATA_PIO_DTR (*((uint32_t volatile*)(0x38700054)))
-#define ATA_PIO_FED (*((uint32_t volatile*)(0x38700058)))
-#define ATA_PIO_SCR (*((uint32_t volatile*)(0x3870005c)))
-#define ATA_PIO_LLR (*((uint32_t volatile*)(0x38700060)))
-#define ATA_PIO_LMR (*((uint32_t volatile*)(0x38700064)))
-#define ATA_PIO_LHR (*((uint32_t volatile*)(0x38700068)))
-#define ATA_PIO_DVR (*((uint32_t volatile*)(0x3870006c)))
-#define ATA_PIO_CSD (*((uint32_t volatile*)(0x38700070)))
-#define ATA_PIO_DAD (*((uint32_t volatile*)(0x38700074)))
-#define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078)))
-#define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c)))
-#define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
-#define ATA_FIFO_STATUS (*((uint32_t volatile*)(0x38700084)))
-#define ATA_DMA_ADDR (*((void* volatile*)(0x38700088)))
-
-
-/////SDCI/////
-#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
-#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
-#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
-#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
-#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
-#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
-#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
-#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
-#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
-#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
-#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
-#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
-#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
-#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
-#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
-#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
-#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
-#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
-#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
-#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
-#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
-
-#define SDCI_CTRL_SDCIEN BIT(0)
-#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
-#define SDCI_CTRL_CARD_TYPE_SD 0
-#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
-#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
-#define SDCI_CTRL_BUS_WIDTH_1BIT 0
-#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
-#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
-#define SDCI_CTRL_DMA_EN BIT(4)
-#define SDCI_CTRL_L_ENDIAN BIT(5)
-#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
-#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
-#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
-#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
-#define SDCI_CTRL_CLK_SEL_PCLK 0
-#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
-#define SDCI_CTRL_BIT_8 BIT(8)
-#define SDCI_CTRL_BIT_14 BIT(14)
-
-#define SDCI_DCTRL_TXFIFORST BIT(0)
-#define SDCI_DCTRL_RXFIFORST BIT(1)
-#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
-#define SDCI_DCTRL_TRCONT_TX BIT(4)
-#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
-#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
-#define SDCI_DCTRL_BUS_TEST_RX BIT(7)
-
-#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
-#define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
-#define SDCI_CDIV_CLKDIV_2 BIT(0)
-#define SDCI_CDIV_CLKDIV_4 BIT(1)
-#define SDCI_CDIV_CLKDIV_8 BIT(2)
-#define SDCI_CDIV_CLKDIV_16 BIT(3)
-#define SDCI_CDIV_CLKDIV_32 BIT(4)
-#define SDCI_CDIV_CLKDIV_64 BIT(5)
-#define SDCI_CDIV_CLKDIV_128 BIT(6)
-#define SDCI_CDIV_CLKDIV_256 BIT(7)
-
-#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
-#define SDCI_CMD_CMD_NUM_SHIFT 0
-#define SDCI_CMD_CMD_NUM(x) (x)
-#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
-#define SDCI_CMD_CMD_TYPE_BC 0
-#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
-#define SDCI_CMD_CMD_TYPE_AC BIT(7)
-#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
-#define SDCI_CMD_CMD_RD_WR BIT(8)
-#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
-#define SDCI_CMD_RES_TYPE_NONE 0
-#define SDCI_CMD_RES_TYPE_R1 BIT(16)
-#define SDCI_CMD_RES_TYPE_R2 BIT(17)
-#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
-#define SDCI_CMD_RES_TYPE_R4 BIT(18)
-#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
-#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
-#define SDCI_CMD_RES_BUSY BIT(19)
-#define SDCI_CMD_RES_SIZE_MASK BIT(20)
-#define SDCI_CMD_RES_SIZE_48 0
-#define SDCI_CMD_RES_SIZE_136 BIT(20)
-#define SDCI_CMD_NCR_NID_MASK BIT(21)
-#define SDCI_CMD_NCR_NID_NCR 0
-#define SDCI_CMD_NCR_NID_NID BIT(21)
-#define SDCI_CMD_CMDSTR BIT(31)
-
-#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
-#define SDCI_STATE_DAT_STATE_IDLE 0
-#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
-#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
-#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
-#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
-#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
-#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
-#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
-#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
-#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
-#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
-#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
-#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
-#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
-#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
-#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
-#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
-#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
-#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
-#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
-
-#define SDCI_STAC_CLR_CMDEND BIT(2)
-#define SDCI_STAC_CLR_BIT_3 BIT(3)
-#define SDCI_STAC_CLR_RESEND BIT(4)
-#define SDCI_STAC_CLR_DATEND BIT(6)
-#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
-#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
-#define SDCI_STAC_CLR_RESTOUTE BIT(15)
-#define SDCI_STAC_CLR_RESENDE BIT(16)
-#define SDCI_STAC_CLR_RESINDE BIT(17)
-#define SDCI_STAC_CLR_RESCRCE BIT(18)
-#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
-#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
-#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
-#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
-#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
-#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
-#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
-#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
-#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
-#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
-
-#define SDCI_DSTA_CMDRDY BIT(0)
-#define SDCI_DSTA_CMDPRO BIT(1)
-#define SDCI_DSTA_CMDEND BIT(2)
-#define SDCI_DSTA_RESPRO BIT(3)
-#define SDCI_DSTA_RESEND BIT(4)
-#define SDCI_DSTA_DATPRO BIT(5)
-#define SDCI_DSTA_DATEND BIT(6)
-#define SDCI_DSTA_DAT_CRCEND BIT(7)
-#define SDCI_DSTA_CRC_STAEND BIT(8)
-#define SDCI_DSTA_DAT_BUSY BIT(9)
-#define SDCI_DSTA_SDCLK_HOLD BIT(12)
-#define SDCI_DSTA_DAT0_STATUS BIT(13)
-#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
-#define SDCI_DSTA_RESTOUTE BIT(15)
-#define SDCI_DSTA_RESENDE BIT(16)
-#define SDCI_DSTA_RESINDE BIT(17)
-#define SDCI_DSTA_RESCRCE BIT(18)
-#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
-#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
-#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
-#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
-#define SDCI_DSTA_WR_DATCRCE BIT(22)
-#define SDCI_DSTA_RD_DATCRCE BIT(23)
-#define SDCI_DSTA_RD_DATENDE0 BIT(24)
-#define SDCI_DSTA_RD_DATENDE1 BIT(25)
-#define SDCI_DSTA_RD_DATENDE2 BIT(26)
-#define SDCI_DSTA_RD_DATENDE3 BIT(27)
-#define SDCI_DSTA_RD_DATENDE4 BIT(28)
-#define SDCI_DSTA_RD_DATENDE5 BIT(29)
-#define SDCI_DSTA_RD_DATENDE6 BIT(30)
-#define SDCI_DSTA_RD_DATENDE7 BIT(31)
-
-#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
-#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
-#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
-#define SDCI_FSTA_TX_FIFO_FULL BIT(3)
-
-#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
-#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
-#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
-#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
-#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
-#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
-#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
-
-#define SDCI_IRQ_DAT_DONE_INT BIT(0)
-#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
-#define SDCI_IRQ_READ_WAIT_INT BIT(2)
-
-#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
-#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
-#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
-
-
-/////CLICKWHEEL/////
-#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
-#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
-#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
-#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
-#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
-#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
-#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
-#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
-
-
-/////I2S/////
-#define I2SCLKCON (*((volatile uint32_t*)(0x3CA00000)))
-#define I2STXCON (*((volatile uint32_t*)(0x3CA00004)))
-#define I2STXCOM (*((volatile uint32_t*)(0x3CA00008)))
-#define I2STXDB0 (*((volatile uint32_t*)(0x3CA00010)))
-#define I2SRXCON (*((volatile uint32_t*)(0x3CA00030)))
-#define I2SRXCOM (*((volatile uint32_t*)(0x3CA00034)))
-#define I2SRXDB (*((volatile uint32_t*)(0x3CA00038)))
-#define I2SSTATUS (*((volatile uint32_t*)(0x3CA0003C)))
-#define I2S40 (*((volatile uint32_t*)(0x3CA00040)))
-
-
-/////CLOCK GATES/////
-#define CLOCKGATE_USB_1 2
-#define CLOCKGATE_USB_2 35
-
-
-/////INTERRUPTS/////
-#define IRQ_TIMER 8
-#define IRQ_USB_FUNC 19
-#define IRQ_DMAC(d) 16 + d
-#define IRQ_DMAC0 16
-#define IRQ_DMAC1 17
-#define IRQ_WHEEL 23
-#define IRQ_ATA 29
-#define IRQ_MMC 44
-
-
-#endif
-
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: s5l8700.h 28791 2010-12-11 09:39:33Z Buschel $
+ *
+ * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef __S5L8702_H__
+#define __S5L8702_H__
+
+#include <inttypes.h>
+
+#define REG8_PTR_T volatile uint8_t *
+#define REG16_PTR_T volatile uint16_t *
+#define REG32_PTR_T volatile uint32_t *
+
+#define TIMER_FREQ 54000000
+
+#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
+
+#define DRAM_ORIG 0x08000000
+#define IRAM_ORIG 0
+
+#define DRAM_SIZE (MEMORYSIZE * 0x100000)
+#define IRAM_SIZE 0x40000
+
+#define TTB_SIZE 0x4000
+#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
+
+/////SYSTEM CONTROLLER/////
+#define CLKCON0 (*((volatile uint32_t*)(0x3C500000)))
+#define CLKCON1 (*((volatile uint32_t*)(0x3C500004)))
+#define CLKCON2 (*((volatile uint32_t*)(0x3C500008)))
+#define CLKCON3 (*((volatile uint32_t*)(0x3C50000C)))
+#define CLKCON4 (*((volatile uint32_t*)(0x3C500010)))
+#define CLKCON5 (*((volatile uint32_t*)(0x3C500014)))
+#define PLL0PMS (*((volatile uint32_t*)(0x3C500020)))
+#define PLL1PMS (*((volatile uint32_t*)(0x3C500024)))
+#define PLL2PMS (*((volatile uint32_t*)(0x3C500028)))
+#define PLL0LCNT (*((volatile uint32_t*)(0x3C500030)))
+#define PLL1LCNT (*((volatile uint32_t*)(0x3C500034)))
+#define PLL2LCNT (*((volatile uint32_t*)(0x3C500038)))
+#define PLLLOCK (*((volatile uint32_t*)(0x3C500040)))
+#define PLLMODE (*((volatile uint32_t*)(0x3C500044)))
+#define PWRCON(i) (*((uint32_t volatile*)(0x3C500000 \
+ + ((i) == 4 ? 0x6C : \
+ ((i) == 3 ? 0x68 : \
+ ((i) == 2 ? 0x58 : \
+ ((i) == 1 ? 0x4C : \
+ 0x48)))))))
+
+
+/////TIMER/////
+#define TACON (*((uint32_t volatile*)(0x3C700000)))
+#define TACMD (*((uint32_t volatile*)(0x3C700004)))
+#define TADATA0 (*((uint32_t volatile*)(0x3C700008)))
+#define TADATA1 (*((uint32_t volatile*)(0x3C70000C)))
+#define TAPRE (*((uint32_t volatile*)(0x3C700010)))
+#define TACNT (*((uint32_t volatile*)(0x3C700014)))
+#define TBCON (*((uint32_t volatile*)(0x3C700020)))
+#define TBCMD (*((uint32_t volatile*)(0x3C700024)))
+#define TBDATA0 (*((uint32_t volatile*)(0x3C700028)))
+#define TBDATA1 (*((uint32_t volatile*)(0x3C70002C)))
+#define TBPRE (*((uint32_t volatile*)(0x3C700030)))
+#define TBCNT (*((uint32_t volatile*)(0x3C700034)))
+#define TCCON (*((uint32_t volatile*)(0x3C700040)))
+#define TCCMD (*((uint32_t volatile*)(0x3C700044)))
+#define TCDATA0 (*((uint32_t volatile*)(0x3C700048)))
+#define TCDATA1 (*((uint32_t volatile*)(0x3C70004C)))
+#define TCPRE (*((uint32_t volatile*)(0x3C700050)))
+#define TCCNT (*((uint32_t volatile*)(0x3C700054)))
+#define TDCON (*((uint32_t volatile*)(0x3C700060)))
+#define TDCMD (*((uint32_t volatile*)(0x3C700064)))
+#define TDDATA0 (*((uint32_t volatile*)(0x3C700068)))
+#define TDDATA1 (*((uint32_t volatile*)(0x3C70006C)))
+#define TDPRE (*((uint32_t volatile*)(0x3C700070)))
+#define TDCNT (*((uint32_t volatile*)(0x3C700074)))
+#define TECON (*((uint32_t volatile*)(0x3C7000A0)))
+#define TECMD (*((uint32_t volatile*)(0x3C7000A4)))
+#define TEDATA0 (*((uint32_t volatile*)(0x3C7000A8)))
+#define TEDATA1 (*((uint32_t volatile*)(0x3C7000AC)))
+#define TEPRE (*((uint32_t volatile*)(0x3C7000B0)))
+#define TECNT (*((uint32_t volatile*)(0x3C7000B4)))
+#define TFCON (*((uint32_t volatile*)(0x3C7000C0)))
+#define TFCMD (*((uint32_t volatile*)(0x3C7000C4)))
+#define TFDATA0 (*((uint32_t volatile*)(0x3C7000C8)))
+#define TFDATA1 (*((uint32_t volatile*)(0x3C7000CC)))
+#define TFPRE (*((uint32_t volatile*)(0x3C7000D0)))
+#define TFCNT (*((uint32_t volatile*)(0x3C7000D4)))
+#define TGCON (*((uint32_t volatile*)(0x3C7000E0)))
+#define TGCMD (*((uint32_t volatile*)(0x3C7000E4)))
+#define TGDATA0 (*((uint32_t volatile*)(0x3C7000E8)))
+#define TGDATA1 (*((uint32_t volatile*)(0x3C7000EC)))
+#define TGPRE (*((uint32_t volatile*)(0x3C7000F0)))
+#define TGCNT (*((uint32_t volatile*)(0x3C7000F4)))
+#define THCON (*((uint32_t volatile*)(0x3C700100)))
+#define THCMD (*((uint32_t volatile*)(0x3C700104)))
+#define THDATA0 (*((uint32_t volatile*)(0x3C700108)))
+#define THDATA1 (*((uint32_t volatile*)(0x3C70010C)))
+#define THPRE (*((uint32_t volatile*)(0x3C700110)))
+#define THCNT (*((uint32_t volatile*)(0x3C700114)))
+#define USEC_TIMER TECNT
+
+
+/////USB/////
+#define OTGBASE 0x38400000
+#define PHYBASE 0x3C400000
+#define SYNOPSYSOTG_CLOCK 0
+#define SYNOPSYSOTG_AHBCFG 0x2B
+
+
+/////I2C/////
+#define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
+#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
+#define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
+#define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
+
+
+/////INTERRUPT CONTROLLERS/////
+#define VICIRQSTATUS(v) (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v))))
+#define VICFIQSTATUS(v) (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v))))
+#define VICRAWINTR(v) (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v))))
+#define VICINTSELECT(v) (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v))))
+#define VICINTENABLE(v) (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v))))
+#define VICINTENCLEAR(v) (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v))))
+#define VICSOFTINT(v) (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v))))
+#define VICSOFTINTCLEAR(v) (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v))))
+#define VICPROTECTION(v) (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v))))
+#define VICSWPRIORITYMASK(v) (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v))))
+#define VICPRIORITYDAISY(v) (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v))))
+#define VICVECTADDR(v, i) (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
+#define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
+#define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v))))
+#define VIC0IRQSTATUS (*((uint32_t volatile*)(0x38E00000)))
+#define VIC0FIQSTATUS (*((uint32_t volatile*)(0x38E00004)))
+#define VIC0RAWINTR (*((uint32_t volatile*)(0x38E00008)))
+#define VIC0INTSELECT (*((uint32_t volatile*)(0x38E0000C)))
+#define VIC0INTENABLE (*((uint32_t volatile*)(0x38E00010)))
+#define VIC0INTENCLEAR (*((uint32_t volatile*)(0x38E00014)))
+#define VIC0SOFTINT (*((uint32_t volatile*)(0x38E00018)))
+#define VIC0SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0001C)))
+#define VIC0PROTECTION (*((uint32_t volatile*)(0x38E00020)))
+#define VIC0SWPRIORITYMASK (*((uint32_t volatile*)(0x38E00024)))
+#define VIC0PRIORITYDAISY (*((uint32_t volatile*)(0x38E00028)))
+#define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i))))
+#define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100)))
+#define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104)))
+#define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108)))
+#define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C)))
+#define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110)))
+#define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114)))
+#define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118)))
+#define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C)))
+#define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120)))
+#define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124)))
+#define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128)))
+#define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C)))
+#define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130)))
+#define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134)))
+#define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138)))
+#define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C)))
+#define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140)))
+#define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144)))
+#define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148)))
+#define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C)))
+#define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150)))
+#define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154)))
+#define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158)))
+#define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C)))
+#define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160)))
+#define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164)))
+#define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168)))
+#define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C)))
+#define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170)))
+#define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174)))
+#define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178)))
+#define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C)))
+#define VIC0VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E00200 + 4 * (i))))
+#define VIC0VECTPRIORITY0 (*((uint32_t volatile*)(0x38E00200)))
+#define VIC0VECTPRIORITY1 (*((uint32_t volatile*)(0x38E00204)))
+#define VIC0VECTPRIORITY2 (*((uint32_t volatile*)(0x38E00208)))
+#define VIC0VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0020C)))
+#define VIC0VECTPRIORITY4 (*((uint32_t volatile*)(0x38E00210)))
+#define VIC0VECTPRIORITY5 (*((uint32_t volatile*)(0x38E00214)))
+#define VIC0VECTPRIORITY6 (*((uint32_t volatile*)(0x38E00218)))
+#define VIC0VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0021C)))
+#define VIC0VECTPRIORITY8 (*((uint32_t volatile*)(0x38E00220)))
+#define VIC0VECTPRIORITY9 (*((uint32_t volatile*)(0x38E00224)))
+#define VIC0VECTPRIORITY10 (*((uint32_t volatile*)(0x38E00228)))
+#define VIC0VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0022C)))
+#define VIC0VECTPRIORITY12 (*((uint32_t volatile*)(0x38E00230)))
+#define VIC0VECTPRIORITY13 (*((uint32_t volatile*)(0x38E00234)))
+#define VIC0VECTPRIORITY14 (*((uint32_t volatile*)(0x38E00238)))
+#define VIC0VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0023C)))
+#define VIC0VECTPRIORITY16 (*((uint32_t volatile*)(0x38E00240)))
+#define VIC0VECTPRIORITY17 (*((uint32_t volatile*)(0x38E00244)))
+#define VIC0VECTPRIORITY18 (*((uint32_t volatile*)(0x38E00248)))
+#define VIC0VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0024C)))
+#define VIC0VECTPRIORITY20 (*((uint32_t volatile*)(0x38E00250)))
+#define VIC0VECTPRIORITY21 (*((uint32_t volatile*)(0x38E00254)))
+#define VIC0VECTPRIORITY22 (*((uint32_t volatile*)(0x38E00258)))
+#define VIC0VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0025C)))
+#define VIC0VECTPRIORITY24 (*((uint32_t volatile*)(0x38E00260)))
+#define VIC0VECTPRIORITY25 (*((uint32_t volatile*)(0x38E00264)))
+#define VIC0VECTPRIORITY26 (*((uint32_t volatile*)(0x38E00268)))
+#define VIC0VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0026C)))
+#define VIC0VECTPRIORITY28 (*((uint32_t volatile*)(0x38E00270)))
+#define VIC0VECTPRIORITY29 (*((uint32_t volatile*)(0x38E00274)))
+#define VIC0VECTPRIORITY30 (*((uint32_t volatile*)(0x38E00278)))
+#define VIC0VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0027C)))
+#define VIC0ADDRESS (*((void* volatile*)(0x38E00F00)))
+#define VIC1IRQSTATUS (*((uint32_t volatile*)(0x38E01000)))
+#define VIC1FIQSTATUS (*((uint32_t volatile*)(0x38E01004)))
+#define VIC1RAWINTR (*((uint32_t volatile*)(0x38E01008)))
+#define VIC1INTSELECT (*((uint32_t volatile*)(0x38E0100C)))
+#define VIC1INTENABLE (*((uint32_t volatile*)(0x38E01010)))
+#define VIC1INTENCLEAR (*((uint32_t volatile*)(0x38E01014)))
+#define VIC1SOFTINT (*((uint32_t volatile*)(0x38E01018)))
+#define VIC1SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0101C)))
+#define VIC1PROTECTION (*((uint32_t volatile*)(0x38E01020)))
+#define VIC1SWPRIORITYMASK (*((uint32_t volatile*)(0x38E01024)))
+#define VIC1PRIORITYDAISY (*((uint32_t volatile*)(0x38E01028)))
+#define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i))))
+#define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100)))
+#define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104)))
+#define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108)))
+#define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C)))
+#define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110)))
+#define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114)))
+#define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118)))
+#define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C)))
+#define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120)))
+#define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124)))
+#define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128)))
+#define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C)))
+#define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130)))
+#define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134)))
+#define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138)))
+#define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C)))
+#define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140)))
+#define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144)))
+#define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148)))
+#define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C)))
+#define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150)))
+#define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154)))
+#define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158)))
+#define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C)))
+#define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160)))
+#define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164)))
+#define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168)))
+#define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C)))
+#define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170)))
+#define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174)))
+#define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178)))
+#define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C)))
+#define VIC1VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E01200 + 4 * (i))))
+#define VIC1VECTPRIORITY0 (*((uint32_t volatile*)(0x38E01200)))
+#define VIC1VECTPRIORITY1 (*((uint32_t volatile*)(0x38E01204)))
+#define VIC1VECTPRIORITY2 (*((uint32_t volatile*)(0x38E01208)))
+#define VIC1VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0120C)))
+#define VIC1VECTPRIORITY4 (*((uint32_t volatile*)(0x38E01210)))
+#define VIC1VECTPRIORITY5 (*((uint32_t volatile*)(0x38E01214)))
+#define VIC1VECTPRIORITY6 (*((uint32_t volatile*)(0x38E01218)))
+#define VIC1VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0121C)))
+#define VIC1VECTPRIORITY8 (*((uint32_t volatile*)(0x38E01220)))
+#define VIC1VECTPRIORITY9 (*((uint32_t volatile*)(0x38E01224)))
+#define VIC1VECTPRIORITY10 (*((uint32_t volatile*)(0x38E01228)))
+#define VIC1VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0122C)))
+#define VIC1VECTPRIORITY12 (*((uint32_t volatile*)(0x38E01230)))
+#define VIC1VECTPRIORITY13 (*((uint32_t volatile*)(0x38E01234)))
+#define VIC1VECTPRIORITY14 (*((uint32_t volatile*)(0x38E01238)))
+#define VIC1VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0123C)))
+#define VIC1VECTPRIORITY16 (*((uint32_t volatile*)(0x38E01240)))
+#define VIC1VECTPRIORITY17 (*((uint32_t volatile*)(0x38E01244)))
+#define VIC1VECTPRIORITY18 (*((uint32_t volatile*)(0x38E01248)))
+#define VIC1VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0124C)))
+#define VIC1VECTPRIORITY20 (*((uint32_t volatile*)(0x38E01250)))
+#define VIC1VECTPRIORITY21 (*((uint32_t volatile*)(0x38E01254)))
+#define VIC1VECTPRIORITY22 (*((uint32_t volatile*)(0x38E01258)))
+#define VIC1VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0125C)))
+#define VIC1VECTPRIORITY24 (*((uint32_t volatile*)(0x38E01260)))
+#define VIC1VECTPRIORITY25 (*((uint32_t volatile*)(0x38E01264)))
+#define VIC1VECTPRIORITY26 (*((uint32_t volatile*)(0x38E01268)))
+#define VIC1VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0126C)))
+#define VIC1VECTPRIORITY28 (*((uint32_t volatile*)(0x38E01270)))
+#define VIC1VECTPRIORITY29 (*((uint32_t volatile*)(0x38E01274)))
+#define VIC1VECTPRIORITY30 (*((uint32_t volatile*)(0x38E01278)))
+#define VIC1VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0127C)))
+#define VIC1ADDRESS (*((void* volatile*)(0x38E01F00)))
+
+
+/////GPIO/////
+#define PCON(i) (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5))))
+#define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
+#define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
+#define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
+#define PCON0 (*((uint32_t volatile*)(0x3cf00000)))
+#define PDAT0 (*((uint32_t volatile*)(0x3cf00004)))
+#define PCON1 (*((uint32_t volatile*)(0x3cf00020)))
+#define PDAT1 (*((uint32_t volatile*)(0x3cf00024)))
+#define PCON2 (*((uint32_t volatile*)(0x3cf00040)))
+#define PDAT2 (*((uint32_t volatile*)(0x3cf00044)))
+#define PCON3 (*((uint32_t volatile*)(0x3cf00060)))
+#define PDAT3 (*((uint32_t volatile*)(0x3cf00064)))
+#define PCON4 (*((uint32_t volatile*)(0x3cf00080)))
+#define PDAT4 (*((uint32_t volatile*)(0x3cf00084)))
+#define PCON5 (*((uint32_t volatile*)(0x3cf000a0)))
+#define PDAT5 (*((uint32_t volatile*)(0x3cf000a4)))
+#define PCON6 (*((uint32_t volatile*)(0x3cf000c0)))
+#define PDAT6 (*((uint32_t volatile*)(0x3cf000c4)))
+#define PCON7 (*((uint32_t volatile*)(0x3cf000e0)))
+#define PDAT7 (*((uint32_t volatile*)(0x3cf000e4)))
+#define PCON8 (*((uint32_t volatile*)(0x3cf00100)))
+#define PDAT8 (*((uint32_t volatile*)(0x3cf00104)))
+#define PCON9 (*((uint32_t volatile*)(0x3cf00120)))
+#define PDAT9 (*((uint32_t volatile*)(0x3cf00124)))
+#define PCONA (*((uint32_t volatile*)(0x3cf00140)))
+#define PDATA (*((uint32_t volatile*)(0x3cf00144)))
+#define PCONB (*((uint32_t volatile*)(0x3cf00160)))
+#define PDATB (*((uint32_t volatile*)(0x3cf00164)))
+#define PCONC (*((uint32_t volatile*)(0x3cf00180)))
+#define PDATC (*((uint32_t volatile*)(0x3cf00184)))
+#define PCOND (*((uint32_t volatile*)(0x3cf001a0)))
+#define PDATD (*((uint32_t volatile*)(0x3cf001a4)))
+#define PCONE (*((uint32_t volatile*)(0x3cf001c0)))
+#define PDATE (*((uint32_t volatile*)(0x3cf001c4)))
+#define PCONF (*((uint32_t volatile*)(0x3cf001e0)))
+#define PDATF (*((uint32_t volatile*)(0x3cf001e4)))
+#define GPIOCMD (*((uint32_t volatile*)(0x3cf00200)))
+
+
+/////SPI/////
+#define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \
+ (i) == 1 ? 0x3ce00000 : \
+ 0x3c300000)
+#define SPICLKGATE(i) ((i) == 2 ? 0x2f : \
+ (i) == 1 ? 0x2b : \
+ 0x22)
+#define SPIDMA(i) ((i) == 2 ? 0xd : \
+ (i) == 1 ? 0xf : \
+ 0x5)
+#define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i))))
+#define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
+#define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
+#define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
+#define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
+#define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
+#define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
+#define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
+#define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38)))
+
+
+/////AES/////
+#define AESCONTROL (*((uint32_t volatile*)(0x38c00000)))
+#define AESGO (*((uint32_t volatile*)(0x38c00004)))
+#define AESUNKREG0 (*((uint32_t volatile*)(0x38c00008)))
+#define AESSTATUS (*((uint32_t volatile*)(0x38c0000c)))
+#define AESUNKREG1 (*((uint32_t volatile*)(0x38c00010)))
+#define AESKEYLEN (*((uint32_t volatile*)(0x38c00014)))
+#define AESOUTSIZE (*((uint32_t volatile*)(0x38c00018)))
+#define AESOUTADDR (*((void* volatile*)(0x38c00020)))
+#define AESINSIZE (*((uint32_t volatile*)(0x38c00024)))
+#define AESINADDR (*((const void* volatile*)(0x38c00028)))
+#define AESAUXSIZE (*((uint32_t volatile*)(0x38c0002c)))
+#define AESAUXADDR (*((void* volatile*)(0x38c00030)))
+#define AESSIZE3 (*((uint32_t volatile*)(0x38c00034)))
+#define AESKEY ((uint32_t volatile*)(0x38c0004c))
+#define AESTYPE (*((uint32_t volatile*)(0x38c0006c)))
+#define AESIV ((uint32_t volatile*)(0x38c00074))
+#define AESTYPE2 (*((uint32_t volatile*)(0x38c00088)))
+#define AESUNKREG2 (*((uint32_t volatile*)(0x38c0008c)))
+
+
+/////SHA1/////
+#define SHA1CONFIG (*((uint32_t volatile*)(0x38000000)))
+#define SHA1RESET (*((uint32_t volatile*)(0x38000004)))
+#define SHA1RESULT ((uint32_t volatile*)(0x38000020))
+#define SHA1DATAIN ((uint32_t volatile*)(0x38000040))
+
+
+/////DMA/////
+#ifndef ASM
+struct dma_lli
+{
+ const void* srcaddr;
+ void* dstaddr;
+ const struct dma_lli* nextlli;
+ uint32_t control;
+};
+#endif
+#define DMACINTSTS(d) (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d))))
+#define DMACINTTCSTS(d) (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d))))
+#define DMACINTTCCLR(d) (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d))))
+#define DMACINTERRSTS(d) (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d))))
+#define DMACINTERRCLR(d) (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d))))
+#define DMACRAWINTTCSTS(d) (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d))))
+#define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d))))
+#define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d))))
+#define DMACSOFTBREQ(d) (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d))))
+#define DMACSOFTSREQ(d) (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d))))
+#define DMACSOFTLBREQ(d) (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d))))
+#define DMACSOFTLSREQ(d) (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d))))
+#define DMACCONFIG(d) (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d))))
+#define DMACSYNC(d) (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d))))
+#define DMACCLLI(d, c) (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCSRCADDR(d, c) (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCNEXTLLI(d, c) (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCCONTROL(d, c) (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCCONFIG(d, c) (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMAC0INTSTS (*((uint32_t volatile*)(0x38200000)))
+#define DMAC0INTTCSTS (*((uint32_t volatile*)(0x38200004)))
+#define DMAC0INTTCCLR (*((uint32_t volatile*)(0x38200008)))
+#define DMAC0INTERRSTS (*((uint32_t volatile*)(0x3820000c)))
+#define DMAC0INTERRCLR (*((uint32_t volatile*)(0x38200010)))
+#define DMAC0RAWINTTCSTS (*((uint32_t volatile*)(0x38200014)))
+#define DMAC0RAWINTERRSTS (*((uint32_t volatile*)(0x38200018)))
+#define DMAC0ENABLEDCHANS (*((uint32_t volatile*)(0x3820001c)))
+#define DMAC0SOFTBREQ (*((uint32_t volatile*)(0x38200020)))
+#define DMAC0SOFTSREQ (*((uint32_t volatile*)(0x38200024)))
+#define DMAC0SOFTLBREQ (*((uint32_t volatile*)(0x38200028)))
+#define DMAC0SOFTLSREQ (*((uint32_t volatile*)(0x3820002c)))
+#define DMAC0CONFIG (*((uint32_t volatile*)(0x38200030)))
+#define DMAC0SYNC (*((uint32_t volatile*)(0x38200034)))
+#define DMAC0CLLI(c) (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c))))
+#define DMAC0CSRCADDR(c) (*((const void* volatile*)(0x38200100 + 0x20 * (c))))
+#define DMAC0CDESTADDR(c) (*((void* volatile*)(0x38200104 + 0x20 * (c))))
+#define DMAC0CNEXTLLI(c) (*((const void* volatile*)(0x38200108 + 0x20 * (c))))
+#define DMAC0CCONTROL(c) (*((uint32_t volatile*)(0x3820010c + 0x20 * (c))))
+#define DMAC0CCONFIG(c) (*((uint32_t volatile*)(0x38200110 + 0x20 * (c))))
+#define DMAC0C0LLI (*((struct dma_lli volatile*)(0x38200100)))
+#define DMAC0C0SRCADDR (*((const void* volatile*)(0x38200100)))
+#define DMAC0C0DESTADDR (*((void* volatile*)(0x38200104)))
+#define DMAC0C0NEXTLLI (*((const struct dma_lli* volatile*)(0x38200108)))
+#define DMAC0C0CONTROL (*((uint32_t volatile*)(0x3820010c)))
+#define DMAC0C0CONFIG (*((uint32_t volatile*)(0x38200110)))
+#define DMAC0C1LLI (*((struct dma_lli volatile*)(0x38200120)))
+#define DMAC0C1SRCADDR (*((const void* volatile*)(0x38200120)))
+#define DMAC0C1DESTADDR (*((void* volatile*)(0x38200124)))
+#define DMAC0C1NEXTLLI (*((const struct dma_lli* volatile*)(0x38200128)))
+#define DMAC0C1CONTROL (*((uint32_t volatile*)(0x3820012c)))
+#define DMAC0C1CONFIG (*((uint32_t volatile*)(0x38200130)))
+#define DMAC0C2LLI (*((struct dma_lli volatile*)(0x38200140)))
+#define DMAC0C2SRCADDR (*((const void* volatile*)(0x38200140)))
+#define DMAC0C2DESTADDR (*((void* volatile*)(0x38200144)))
+#define DMAC0C2NEXTLLI (*((const struct dma_lli* volatile*)(0x38200148)))
+#define DMAC0C2CONTROL (*((uint32_t volatile*)(0x3820014c)))
+#define DMAC0C2CONFIG (*((uint32_t volatile*)(0x38200150)))
+#define DMAC0C3LLI (*((struct dma_lli volatile*)(0x38200160)))
+#define DMAC0C3SRCADDR (*((const void* volatile*)(0x38200160)))
+#define DMAC0C3DESTADDR (*((void* volatile*)(0x38200164)))
+#define DMAC0C3NEXTLLI (*((const struct dma_lli* volatile*)(0x38200168)))
+#define DMAC0C3CONTROL (*((uint32_t volatile*)(0x3820016c)))
+#define DMAC0C3CONFIG (*((uint32_t volatile*)(0x38200170)))
+#define DMAC0C4LLI (*((struct dma_lli volatile*)(0x38200180)))
+#define DMAC0C4SRCADDR (*((const void* volatile*)(0x38200180)))
+#define DMAC0C4DESTADDR (*((void* volatile*)(0x38200184)))
+#define DMAC0C4NEXTLLI (*((const struct dma_lli* volatile*)(0x38200188)))
+#define DMAC0C4CONTROL (*((uint32_t volatile*)(0x3820018c)))
+#define DMAC0C4CONFIG (*((uint32_t volatile*)(0x38200190)))
+#define DMAC0C5LLI (*((struct dma_lli volatile*)(0x382001a0)))
+#define DMAC0C5SRCADDR (*((const void* volatile*)(0x382001a0)))
+#define DMAC0C5DESTADDR (*((void* volatile*)(0x382001a4)))
+#define DMAC0C5NEXTLLI (*((const struct dma_lli* volatile*)(0x382001a8)))
+#define DMAC0C5CONTROL (*((uint32_t volatile*)(0x382001ac)))
+#define DMAC0C5CONFIG (*((uint32_t volatile*)(0x382001b0)))
+#define DMAC0C6LLI (*((struct dma_lli volatile*)(0x382001c0)))
+#define DMAC0C6SRCADDR (*((const void* volatile*)(0x382001c0)))
+#define DMAC0C6DESTADDR (*((void* volatile*)(0x382001c4)))
+#define DMAC0C6NEXTLLI (*((const struct dma_lli* volatile*)(0x382001c8)))
+#define DMAC0C6CONTROL (*((uint32_t volatile*)(0x382001cc)))
+#define DMAC0C6CONFIG (*((uint32_t volatile*)(0x382001d0)))
+#define DMAC0C7LLI (*((struct dma_lli volatile*)(0x382001e0)))
+#define DMAC0C7SRCADDR (*((const void* volatile*)(0x382001e0)))
+#define DMAC0C7DESTADDR (*((void* volatile*)(0x382001e4)))
+#define DMAC0C7NEXTLLI (*((const struct dma_lli* volatile*)(0x382001e8)))
+#define DMAC0C7CONTROL (*((uint32_t volatile*)(0x382001ec)))
+#define DMAC0C7CONFIG (*((uint32_t volatile*)(0x382001f0)))
+#define DMAC1INTSTS (*((uint32_t volatile*)(0x39900000)))
+#define DMAC1INTTCSTS (*((uint32_t volatile*)(0x39900004)))
+#define DMAC1INTTCCLR (*((uint32_t volatile*)(0x39900008)))
+#define DMAC1INTERRSTS (*((uint32_t volatile*)(0x3990000c)))
+#define DMAC1INTERRCLR (*((uint32_t volatile*)(0x39900010)))
+#define DMAC1RAWINTTCSTS (*((uint32_t volatile*)(0x39900014)))
+#define DMAC1RAWINTERRSTS (*((uint32_t volatile*)(0x39900018)))
+#define DMAC1ENABLEDCHANS (*((uint32_t volatile*)(0x3990001c)))
+#define DMAC1SOFTBREQ (*((uint32_t volatile*)(0x39900020)))
+#define DMAC1SOFTSREQ (*((uint32_t volatile*)(0x39900024)))
+#define DMAC1SOFTLBREQ (*((uint32_t volatile*)(0x39900028)))
+#define DMAC1SOFTLSREQ (*((uint32_t volatile*)(0x3990002c)))
+#define DMAC1CONFIG (*((uint32_t volatile*)(0x39900030)))
+#define DMAC1SYNC (*((uint32_t volatile*)(0x39900034)))
+#define DMAC1CLLI(c) (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c))))
+#define DMAC1CSRCADDR(c) (*((const void* volatile*)(0x39900100 + 0x20 * (c))))
+#define DMAC1CDESTADDR(c) (*((void* volatile*)(0x39900104 + 0x20 * (c))))
+#define DMAC1CNEXTLLI(c) (*((const void* volatile*)(0x39900108 + 0x20 * (c))))
+#define DMAC1CCONTROL(c) (*((uint32_t volatile*)(0x3990010c + 0x20 * (c))))
+#define DMAC1CCONFIG(c) (*((uint32_t volatile*)(0x39900110 + 0x20 * (c))))
+#define DMAC1C0LLI (*((struct dma_lli volatile*)(0x39900100)))
+#define DMAC1C0SRCADDR (*((const void* volatile*)(0x39900100)))
+#define DMAC1C0DESTADDR (*((void* volatile*)(0x39900104)))
+#define DMAC1C0NEXTLLI (*((const struct dma_lli* volatile*)(0x39900108)))
+#define DMAC1C0CONTROL (*((uint32_t volatile*)(0x3990010c)))
+#define DMAC1C0CONFIG (*((uint32_t volatile*)(0x39900110)))
+#define DMAC1C1LLI (*((struct dma_lli volatile*)(0x39900120)))
+#define DMAC1C1SRCADDR (*((const void* volatile*)(0x39900120)))
+#define DMAC1C1DESTADDR (*((void* volatile*)(0x39900124)))
+#define DMAC1C1NEXTLLI (*((const struct dma_lli* volatile*)(0x39900128)))
+#define DMAC1C1CONTROL (*((uint32_t volatile*)(0x3990012c)))
+#define DMAC1C1CONFIG (*((uint32_t volatile*)(0x39900130)))
+#define DMAC1C2LLI (*((struct dma_lli volatile*)(0x39900140)))
+#define DMAC1C2SRCADDR (*((const void* volatile*)(0x39900140)))
+#define DMAC1C2DESTADDR (*((void* volatile*)(0x39900144)))
+#define DMAC1C2NEXTLLI (*((const struct dma_lli* volatile*)(0x39900148)))
+#define DMAC1C2CONTROL (*((uint32_t volatile*)(0x3990014c)))
+#define DMAC1C2CONFIG (*((uint32_t volatile*)(0x39900150)))
+#define DMAC1C3LLI (*((struct dma_lli volatile*)(0x39900160)))
+#define DMAC1C3SRCADDR (*((const void* volatile*)(0x39900160)))
+#define DMAC1C3DESTADDR (*((void* volatile*)(0x39900164)))
+#define DMAC1C3NEXTLLI (*((volatile void**)(0x39900168)))
+#define DMAC1C3CONTROL (*((uint32_t volatile*)(0x3990016c)))
+#define DMAC1C3CONFIG (*((uint32_t volatile*)(0x39900170)))
+#define DMAC1C4LLI (*((struct dma_lli volatile*)(0x39900180)))
+#define DMAC1C4SRCADDR (*((const void* volatile*)(0x39900180)))
+#define DMAC1C4DESTADDR (*((void* volatile*)(0x39900184)))
+#define DMAC1C4NEXTLLI (*((const struct dma_lli* volatile*)(0x39900188)))
+#define DMAC1C4CONTROL (*((uint32_t volatile*)(0x3990018c)))
+#define DMAC1C4CONFIG (*((uint32_t volatile*)(0x39900190)))
+#define DMAC1C5LLI (*((struct dma_lli volatile*)(0x399001a0)))
+#define DMAC1C5SRCADDR (*((const void* volatile*)(0x399001a0)))
+#define DMAC1C5DESTADDR (*((void* volatile*)(0x399001a4)))
+#define DMAC1C5NEXTLLI (*((const struct dma_lli* volatile*)(0x399001a8)))
+#define DMAC1C5CONTROL (*((uint32_t volatile*)(0x399001ac)))
+#define DMAC1C5CONFIG (*((uint32_t volatile*)(0x399001b0)))
+#define DMAC1C6LLI (*((struct dma_lli volatile*)(0x399001c0)))
+#define DMAC1C6SRCADDR (*((const void* volatile*)(0x399001c0)))
+#define DMAC1C6DESTADDR (*((void* volatile*)(0x399001c4)))
+#define DMAC1C6NEXTLLI (*((const struct dma_lli* volatile*)(0x399001c8)))
+#define DMAC1C6CONTROL (*((uint32_t volatile*)(0x399001cc)))
+#define DMAC1C6CONFIG (*((uint32_t volatile*)(0x399001d0)))
+#define DMAC1C7LLI (*((struct dma_lli volatile*)(0x399001e0)))
+#define DMAC1C7SRCADDR (*((const void* volatile*)(0x399001e0)))
+#define DMAC1C7DESTADDR (*((void* volatile*)(0x399001e4)))
+#define DMAC1C7NEXTLLI (*((const struct dma_lli* volatile*)(0x399001e8)))
+#define DMAC1C7CONTROL (*((uint32_t volatile*)(0x399001ec)))
+#define DMAC1C7CONFIG (*((uint32_t volatile*)(0x399001f0)))
+
+
+/////LCD/////
+#define LCD_BASE (0x38300000)
+#define LCD_CONFIG (*((uint32_t volatile*)(0x38300000)))
+#define LCD_WCMD (*((uint32_t volatile*)(0x38300004)))
+#define LCD_STATUS (*((uint32_t volatile*)(0x3830001c)))
+#define LCD_WDATA (*((uint32_t volatile*)(0x38300040)))
+
+
+/////ATA/////
+#define ATA_CONTROL (*((uint32_t volatile*)(0x38700000)))
+#define ATA_STATUS (*((uint32_t volatile*)(0x38700004)))
+#define ATA_COMMAND (*((uint32_t volatile*)(0x38700008)))
+#define ATA_SWRST (*((uint32_t volatile*)(0x3870000c)))
+#define ATA_IRQ (*((uint32_t volatile*)(0x38700010)))
+#define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014)))
+#define ATA_CFG (*((uint32_t volatile*)(0x38700018)))
+#define ATA_MDMA_TIME (*((uint32_t volatile*)(0x38700028)))
+#define ATA_PIO_TIME (*((uint32_t volatile*)(0x3870002c)))
+#define ATA_UDMA_TIME (*((uint32_t volatile*)(0x38700030)))
+#define ATA_XFR_NUM (*((uint32_t volatile*)(0x38700034)))
+#define ATA_XFR_CNT (*((uint32_t volatile*)(0x38700038)))
+#define ATA_TBUF_START (*((void* volatile*)(0x3870003c)))
+#define ATA_TBUF_SIZE (*((uint32_t volatile*)(0x38700040)))
+#define ATA_SBUF_START (*((void* volatile*)(0x38700044)))
+#define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048)))
+#define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c)))
+#define ATA_CADR_SBUF (*((void* volatile*)(0x38700050)))
+#define ATA_PIO_DTR (*((uint32_t volatile*)(0x38700054)))
+#define ATA_PIO_FED (*((uint32_t volatile*)(0x38700058)))
+#define ATA_PIO_SCR (*((uint32_t volatile*)(0x3870005c)))
+#define ATA_PIO_LLR (*((uint32_t volatile*)(0x38700060)))
+#define ATA_PIO_LMR (*((uint32_t volatile*)(0x38700064)))
+#define ATA_PIO_LHR (*((uint32_t volatile*)(0x38700068)))
+#define ATA_PIO_DVR (*((uint32_t volatile*)(0x3870006c)))
+#define ATA_PIO_CSD (*((uint32_t volatile*)(0x38700070)))
+#define ATA_PIO_DAD (*((uint32_t volatile*)(0x38700074)))
+#define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078)))
+#define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c)))
+#define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
+#define ATA_FIFO_STATUS (*((uint32_t volatile*)(0x38700084)))
+#define ATA_DMA_ADDR (*((void* volatile*)(0x38700088)))
+
+
+/////SDCI/////
+#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
+#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
+#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
+#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
+#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
+#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
+#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
+#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
+#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
+#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
+#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
+#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
+#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
+#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
+#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
+#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
+#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
+#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
+#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
+#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
+#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
+
+#define SDCI_CTRL_SDCIEN BIT(0)
+#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
+#define SDCI_CTRL_CARD_TYPE_SD 0
+#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
+#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
+#define SDCI_CTRL_BUS_WIDTH_1BIT 0
+#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
+#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
+#define SDCI_CTRL_DMA_EN BIT(4)
+#define SDCI_CTRL_L_ENDIAN BIT(5)
+#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
+#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
+#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
+#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
+#define SDCI_CTRL_CLK_SEL_PCLK 0
+#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
+#define SDCI_CTRL_BIT_8 BIT(8)
+#define SDCI_CTRL_BIT_14 BIT(14)
+
+#define SDCI_DCTRL_TXFIFORST BIT(0)
+#define SDCI_DCTRL_RXFIFORST BIT(1)
+#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
+#define SDCI_DCTRL_TRCONT_TX BIT(4)
+#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
+#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
+#define SDCI_DCTRL_BUS_TEST_RX BIT(7)
+
+#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
+#define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
+#define SDCI_CDIV_CLKDIV_2 BIT(0)
+#define SDCI_CDIV_CLKDIV_4 BIT(1)
+#define SDCI_CDIV_CLKDIV_8 BIT(2)
+#define SDCI_CDIV_CLKDIV_16 BIT(3)
+#define SDCI_CDIV_CLKDIV_32 BIT(4)
+#define SDCI_CDIV_CLKDIV_64 BIT(5)
+#define SDCI_CDIV_CLKDIV_128 BIT(6)
+#define SDCI_CDIV_CLKDIV_256 BIT(7)
+
+#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
+#define SDCI_CMD_CMD_NUM_SHIFT 0
+#define SDCI_CMD_CMD_NUM(x) (x)
+#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
+#define SDCI_CMD_CMD_TYPE_BC 0
+#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
+#define SDCI_CMD_CMD_TYPE_AC BIT(7)
+#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
+#define SDCI_CMD_CMD_RD_WR BIT(8)
+#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
+#define SDCI_CMD_RES_TYPE_NONE 0
+#define SDCI_CMD_RES_TYPE_R1 BIT(16)
+#define SDCI_CMD_RES_TYPE_R2 BIT(17)
+#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
+#define SDCI_CMD_RES_TYPE_R4 BIT(18)
+#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
+#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
+#define SDCI_CMD_RES_BUSY BIT(19)
+#define SDCI_CMD_RES_SIZE_MASK BIT(20)
+#define SDCI_CMD_RES_SIZE_48 0
+#define SDCI_CMD_RES_SIZE_136 BIT(20)
+#define SDCI_CMD_NCR_NID_MASK BIT(21)
+#define SDCI_CMD_NCR_NID_NCR 0
+#define SDCI_CMD_NCR_NID_NID BIT(21)
+#define SDCI_CMD_CMDSTR BIT(31)
+
+#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
+#define SDCI_STATE_DAT_STATE_IDLE 0
+#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
+#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
+#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
+#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
+#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
+#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
+#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
+#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
+#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
+#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
+#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
+#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
+#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
+#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
+#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
+#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
+#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
+#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
+#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
+
+#define SDCI_STAC_CLR_CMDEND BIT(2)
+#define SDCI_STAC_CLR_BIT_3 BIT(3)
+#define SDCI_STAC_CLR_RESEND BIT(4)
+#define SDCI_STAC_CLR_DATEND BIT(6)
+#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
+#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
+#define SDCI_STAC_CLR_RESTOUTE BIT(15)
+#define SDCI_STAC_CLR_RESENDE BIT(16)
+#define SDCI_STAC_CLR_RESINDE BIT(17)
+#define SDCI_STAC_CLR_RESCRCE BIT(18)
+#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
+#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
+#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
+#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
+#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
+#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
+#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
+#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
+#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
+#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
+
+#define SDCI_DSTA_CMDRDY BIT(0)
+#define SDCI_DSTA_CMDPRO BIT(1)
+#define SDCI_DSTA_CMDEND BIT(2)
+#define SDCI_DSTA_RESPRO BIT(3)
+#define SDCI_DSTA_RESEND BIT(4)
+#define SDCI_DSTA_DATPRO BIT(5)
+#define SDCI_DSTA_DATEND BIT(6)
+#define SDCI_DSTA_DAT_CRCEND BIT(7)
+#define SDCI_DSTA_CRC_STAEND BIT(8)
+#define SDCI_DSTA_DAT_BUSY BIT(9)
+#define SDCI_DSTA_SDCLK_HOLD BIT(12)
+#define SDCI_DSTA_DAT0_STATUS BIT(13)
+#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
+#define SDCI_DSTA_RESTOUTE BIT(15)
+#define SDCI_DSTA_RESENDE BIT(16)
+#define SDCI_DSTA_RESINDE BIT(17)
+#define SDCI_DSTA_RESCRCE BIT(18)
+#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
+#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
+#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
+#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
+#define SDCI_DSTA_WR_DATCRCE BIT(22)
+#define SDCI_DSTA_RD_DATCRCE BIT(23)
+#define SDCI_DSTA_RD_DATENDE0 BIT(24)
+#define SDCI_DSTA_RD_DATENDE1 BIT(25)
+#define SDCI_DSTA_RD_DATENDE2 BIT(26)
+#define SDCI_DSTA_RD_DATENDE3 BIT(27)
+#define SDCI_DSTA_RD_DATENDE4 BIT(28)
+#define SDCI_DSTA_RD_DATENDE5 BIT(29)
+#define SDCI_DSTA_RD_DATENDE6 BIT(30)
+#define SDCI_DSTA_RD_DATENDE7 BIT(31)
+
+#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
+#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
+#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
+#define SDCI_FSTA_TX_FIFO_FULL BIT(3)
+
+#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
+#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
+#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
+#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
+#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
+#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
+#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
+
+#define SDCI_IRQ_DAT_DONE_INT BIT(0)
+#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
+#define SDCI_IRQ_READ_WAIT_INT BIT(2)
+
+#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
+#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
+#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
+
+
+/////CLICKWHEEL/////
+#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
+#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
+#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
+#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
+#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
+#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
+#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
+#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
+
+
+/////I2S/////
+#define I2SCLKCON (*((volatile uint32_t*)(0x3CA00000)))
+#define I2STXCON (*((volatile uint32_t*)(0x3CA00004)))
+#define I2STXCOM (*((volatile uint32_t*)(0x3CA00008)))
+#define I2STXDB0 (*((volatile uint32_t*)(0x3CA00010)))
+#define I2SRXCON (*((volatile uint32_t*)(0x3CA00030)))
+#define I2SRXCOM (*((volatile uint32_t*)(0x3CA00034)))
+#define I2SRXDB (*((volatile uint32_t*)(0x3CA00038)))
+#define I2SSTATUS (*((volatile uint32_t*)(0x3CA0003C)))
+#define I2S40 (*((volatile uint32_t*)(0x3CA00040)))
+
+
+/////CLOCK GATES/////
+#define CLOCKGATE_USB_1 2
+#define CLOCKGATE_USB_2 35
+
+
+/////INTERRUPTS/////
+#define IRQ_TIMER 8
+#define IRQ_USB_FUNC 19
+#define IRQ_DMAC(d) 16 + d
+#define IRQ_DMAC0 16
+#define IRQ_DMAC1 17
+#define IRQ_WHEEL 23
+#define IRQ_ATA 29
+#define IRQ_MMC 44
+
+
+#endif
+
diff --git a/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c b/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
index 4650913ce3..2d8d25cf31 100644
--- a/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
+++ b/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
@@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
- * $Id: lcd-clipzip.c 30465 2011-09-06 16:55:52Z bertrik $
+ * $Id$
*
* Copyright (C) 2011 Bertrik Sikken
*
diff --git a/firmware/target/arm/s5l8700/postmortemstub.S b/firmware/target/arm/s5l8700/postmortemstub.S
index 73f192a553..d0874c418b 100644
--- a/firmware/target/arm/s5l8700/postmortemstub.S
+++ b/firmware/target/arm/s5l8700/postmortemstub.S
@@ -1,308 +1,308 @@
-.section .text.post_mortem_stub, "ax", %progbits
-.align 4
-.global post_mortem_stub
-.type post_mortem_stub, %function
-post_mortem_stub:
-MSR CPSR_c, #0xD3 @ Supervisor mode, no IRQs, no FIQs
-MRC p15, 0, R0,c1,c0
-BIC R0, R0, #5
-MCR p15, 0, R0,c1,c0 @ Disable the Protection Unit and DCache
-MOV R13, #0
-pms_flushcache_loop:
- MCR p15, 0, R13,c7,c14,2
- ADD R0, R13, #0x10
- MCR p15, 0, R0,c7,c14,2
- ADD R0, R0, #0x10
- MCR p15, 0, R0,c7,c14,2
- ADD R0, R0, #0x10
- MCR p15, 0, R0,c7,c14,2
- ADDS R13, R13, #0x04000000
-BNE pms_flushcache_loop
-MCR p15, 0, R13,c7,c10,4
-
-LDR R7, pms_00080200
-ORR R8, R7, #0x8000
-ADR R9, pms_recvbuf
-LDR R10, pms_20080040
-MOV R11, #0x38800000
-MOV R12, #1
-
-MOV R2, #0x3C400000
-ADD R1, R2, #0x00100000 @ Enable USB clocks
-LDR R0, [R1,#0x28]
-BIC R0, R0, #0x4000
-STR R0, [R1,#0x28]
-LDR R0, [R1,#0x40]
-BIC R0, R0, #0x800
-STR R0, [R1,#0x40]
-LDR R0, pms_20803180 @ Clocking config
-STR R0, [R1]
-MOV R0, #0x280
-STR R0, [R1,#0x3C]
-MRC p15, 0, R0,c1,c0
-ORR R0, R0, #0xc0000000
-MCR p15, 0, R0,c1,c0 @ Asynchronous mode
-
-STR R13, [R11,#0xE00] @ PHY clock enable
-
-MOV R1, #0x800
-ORR R0, R2, #2
-STR R0, [R11,#0x804] @ USB2 Gadget: Soft disconnect
-
-STR R13, [R2] @ USB2 PHY: Power on
-STR R12, [R2,#0x08] @ USB2 PHY: Assert Software Reset
-MOV R0, #0x10000
-pms_wait:
-SUBS R0, R0, #1
-BNE pms_wait
-STR R13, [R2,#0x08] @ USB2 PHY: Deassert Software Reset
-STR R13, [R2,#0x04] @ USB2 PHY: Clock is 48MHz
-
-STR R12, [R11,#0x10] @ USB2 Gadget: Assert Core Software Reset
-pms_waitcorereset:
-LDR R0, [R11,#0x10] @ USB2 Gadget: Wait for Core to reset
-TST R0, #1
-BNE pms_waitcorereset
-TST R0, #0x80000000 @ USB2 Gadget: Wait for AHB IDLE
-BEQ pms_waitcorereset
-
-MOV R0, #0x200
-STR R0, [R11,#0x24] @ USB2 Gadget: RX FIFO size: 512 bytes
-ORR R0, R0, #0x2000000
-STR R0, [R11,#0x28] @ USB2 Gadget: Non-periodic TX FIFO size: 512 bytes
-MOV R0, #0x26
-STR R0, [R11,#0x08] @ USB2 Gadget: DMA Enable, Burst Length: 4, Mask Interrupts
-MOV R0, #0x1400
-ADD R0, R0, #8
-STR R0, [R11,#0x0C] @ USB2 Gadget: PHY IF is 16bit, Turnaround 5
-STR R1, [R11,#0x804] @ USB2 Gadget: Soft reconnect
-
-ADR R14, pms_ctrlbuf
-ORR R5, R8, #0x84000000
-@ fallthrough
-
-pms_mainloop:
- LDR R3, [R11,#0x14] @ Global USB interrupts
- TST R3, #0x00001000 @ BUS reset
- BEQ pms_noreset
- MOV R0, #0x500
- STR R0, [R11,#0x804]
- MOV R0, #4
- STR R0, [R11,#0x800] @ USB2 Gadget: Device Address 0, STALL on non-zero length status stage
- MOV R0, #0x8000
- STR R0, [R11,#0x900] @ USB2 Gadget: Endpoint 0 IN Control: ACTIVE
- STR R10, [R11,#0xB10] @ USB2 Gadget: Endpoint 0 OUT Transfer Size: 64 Bytes, 1 Packet, 1 Setup Packet
- STR R14, [R11,#0xB14] @ USB2 Gadget: Endpoint 0 OUT DMA Address: pms_ctrlbuf
- ORR R6, R0, #0x84000000
- STR R6, [R11,#0xB00] @ USB2 Gadget: Endpoint 0 OUT Control: ENABLE CLEARNAK
- STR R8, [R11,#0x960] @ USB2 Gadget: Endpoint 3 IN Control: ACTIVE BULK, 512 byte packets
- STR R8, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ACTIVE BULK, 512 byte packets
- STR R7, [R11,#0xB90] @ USB2 Gadget: Endpoint 4 OUT Transfer Size: 512 Bytes, 1 Packet
- STR R9, [R11,#0xB94] @ USB2 Gadget: Endpoint 4 OUT DMA Address: pms_recvbuf
- ORR R4, R5, #0x10000000
- STR R4, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ENABLE CLEARNAK DATA0
- pms_noreset:
- LDR R0, [R11,#0x908] @ Just ACK all IN events...
- STR R0, [R11,#0x908]
- LDR R0, [R11,#0x968]
- STR R0, [R11,#0x968]
- LDR R2, [R11,#0xB08]
- MOVS R2, R2 @ Event on OUT EP0
- BEQ pms_noep0out
- TST R2, #8 @ SETUP phase done
- BEQ pms_controldone
- LDRB R0, [R14,#1] @ Get request type
- CMP R0, #0
- BEQ pms_GET_STATUS
- CMP R0, #1
- BEQ pms_CLEAR_FEATURE
- CMP R0, #3
- BEQ pms_SET_FEATURE
- CMP R0, #5
- BEQ pms_SET_ADDRESS
- CMP R0, #6
- BEQ pms_GET_DESCRIPTOR
- CMP R0, #8
- BEQ pms_GET_CONFIGURATION
- CMP R0, #9
- BEQ pms_SET_CONFIGURATION
- pms_ctrlstall:
- LDR R0, [R11,#0x900]
- ORR R0, R0, #0x00200000
- STR R0, [R11,#0x900] @ Stall IN EP0
- LDR R0, [R11,#0xB00]
- ORR R0, R0, #0x00200000
- STR R0, [R11,#0xB00] @ Stall OUT EP0
- pms_controldone:
- STR R10, [R11,#0xB10] @ OUT EP0: 64 Bytes, 1 Packet, 1 Setup Packet
- STR R14, [R11,#0xB14] @ OUT EP0: DMA address
- STR R6, [R11,#0xB00] @ OUT EP0: Enable ClearNAK
- pms_noep0out:
- STR R2, [R11,#0xB08] @ ACK it, whatever it was...
- LDR R2, [R11,#0xB88]
- MOVS R2, R2 @ Event on OUT EP4
- BEQ pms_noep1out
- TST R2, #1 @ XFER complete
- BEQ pms_datadone
- LDR R0, pms_000001FF
- LDR R1, pms_recvbuf+4
- ADD R0, R0, R1
- MOV R0, R0,LSR#9
- ORR R1, R1, R0,LSL#19 @ Number of packets
- LDR R0, pms_recvbuf
- STR R1, [R11,#0x970] @ EP3 IN: Number of packets, size
- STR R0, [R11,#0x974] @ EP3 IN: DMA address
- STR R5, [R11,#0x960] @ EP3 IN: Enable ClearNAK
- pms_datadone:
- STR R7, [R11,#0xB90] @ OUT EP4: 512 Bytes, 1 Packet
- STR R9, [R11,#0xB94] @ Out EP4: DMA address
- STR R5, [R11,#0xB80] @ Out EP4: Enable ClearNAK
- pms_noep1out:
- STR R2, [R11,#0xB88] @ ACK it, whatever it was...
- STR R3, [R11,#0x14] @ ACK global ints
-B pms_mainloop
-
-pms_CLEAR_FEATURE:
- LDRB R0, [R14]
- CMP R0, #2
- LDREQ R0, [R14,#2]
- BICEQ R0, R0, #0x00800000
- CMPEQ R0, #0x00010000
-@ fallthrough
-
-pms_SET_CONFIGURATION:
- ORREQ R0, R8, #0x10000000
- STREQ R0, [R11,#0x960] @ EP3 IN: Set DATA0 PID
- STREQ R4, [R11,#0xB80] @ EP4 OUT: Set DATA0 PID
-B pms_SET_FEATURE @ zero-length ACK
-
-pms_GET_CONFIGURATION:
- MOV R1, #1
- STR R1, [R14]
-@ fallthrough
-
-pms_ctrlsend:
- ORR R0, R1, #0x00080000 @ 1 Packet
- STR R0, [R11,#0x910] @ EP0 IN: 1 Packet, Size as in R1
- STR R14, [R11,#0x914] @ EP0 IN: DMA address
- ORR R0, R6, #0x1800
- STR R0, [R11,#0x900] @ EP0 IN: Enable ClearNAK
- ADR R14, pms_ctrlbuf
-B pms_controldone
-
-pms_GET_DESCRIPTOR:
- LDRB R0, [R14,#3] @ Descriptor type
- CMP R0, #1
- ADREQ R14, pms_devicedescriptor
- BEQ pms_senddescriptor
- CMP R0, #2
- ADREQ R14, pms_configurationdescriptor
- MOVEQ R1, #0x20
- BEQ pms_senddescriptorcustomsize
- CMP R0, #3
- BNE pms_ctrlstall
- LDRB R0, [R14,#2] @ String descriptor index
- CMP R0, #0
- LDREQ R0, pms_langstringdescriptor
- STREQ R0, [R14]
- BEQ pms_senddescriptor
- CMP R0, #1
- CMPNE R0, #2
- ADREQ R14, pms_devnamestringdescriptor
- BNE pms_ctrlstall
-@ fallthrough
-
-pms_senddescriptor:
- LDRB R1, [R14] @ Descriptor length
-@ fallthrough
-
-pms_senddescriptorcustomsize:
- LDRH R0, pms_ctrlbuf+6 @ Requested length
- CMP R0, R1
- MOVLO R1, R0
-B pms_ctrlsend
-
-pms_SET_ADDRESS:
- LDRH R1, [R14,#2] @ new address
- LDR R0, [R11,#0x800]
- BIC R0, R0, #0x000007F0
- ORR R0, R0, R1,LSL#4
- STR R0, [R11,#0x800] @ set new address
-@ fallthrough
-
-pms_SET_FEATURE:
- MOV R1, #0 @ zero-length ACK
-B pms_ctrlsend
-
-pms_20803180:
-.word 0x20803180
-
-.ltorg
-
-.align 4
-
-pms_configurationdescriptor:
-.word 0x00200209
-.word 0xC0000101
-.word 0x00040932
-.word 0xFFFF0200
-.word 0x050700FF
-.word 0x02000204
-.word 0x83050701
-.word 0x01020002
-
-pms_devicedescriptor:
-.word 0x02000112
-.word 0x40FFFFFF
-.word 0xA112FFFF
-.word 0x02010001
-.word 0x00010100
-
-pms_00080200:
-.word 0x00080200
-
-pms_20080040:
-.word 0x20080040
-
-pms_000001FF:
-.word 0x000001FF
-
-pms_devnamestringdescriptor:
-.word 0x0052030C
-.word 0x00500042
-.word 0x0053004D
-
-pms_langstringdescriptor:
-.word 0x04090304
-
-pms_ctrlbuf:
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-.word 0
-
-pms_recvbuf:
-.word 0
-.word 0
-
-pms_GET_STATUS:
- LDRB R0, [R14]
- CMP R0, #0x80
- STREQ R12, [R14]
- STRNE R13, [R14]
- MOV R1, #2
-B pms_ctrlsend
-
-.size post_mortem_stub, .-post_mortem_stub
+.section .text.post_mortem_stub, "ax", %progbits
+.align 4
+.global post_mortem_stub
+.type post_mortem_stub, %function
+post_mortem_stub:
+MSR CPSR_c, #0xD3 @ Supervisor mode, no IRQs, no FIQs
+MRC p15, 0, R0,c1,c0
+BIC R0, R0, #5
+MCR p15, 0, R0,c1,c0 @ Disable the Protection Unit and DCache
+MOV R13, #0
+pms_flushcache_loop:
+ MCR p15, 0, R13,c7,c14,2
+ ADD R0, R13, #0x10
+ MCR p15, 0, R0,c7,c14,2
+ ADD R0, R0, #0x10
+ MCR p15, 0, R0,c7,c14,2
+ ADD R0, R0, #0x10
+ MCR p15, 0, R0,c7,c14,2
+ ADDS R13, R13, #0x04000000
+BNE pms_flushcache_loop
+MCR p15, 0, R13,c7,c10,4
+
+LDR R7, pms_00080200
+ORR R8, R7, #0x8000
+ADR R9, pms_recvbuf
+LDR R10, pms_20080040
+MOV R11, #0x38800000
+MOV R12, #1
+
+MOV R2, #0x3C400000
+ADD R1, R2, #0x00100000 @ Enable USB clocks
+LDR R0, [R1,#0x28]
+BIC R0, R0, #0x4000
+STR R0, [R1,#0x28]
+LDR R0, [R1,#0x40]
+BIC R0, R0, #0x800
+STR R0, [R1,#0x40]
+LDR R0, pms_20803180 @ Clocking config
+STR R0, [R1]
+MOV R0, #0x280
+STR R0, [R1,#0x3C]
+MRC p15, 0, R0,c1,c0
+ORR R0, R0, #0xc0000000
+MCR p15, 0, R0,c1,c0 @ Asynchronous mode
+
+STR R13, [R11,#0xE00] @ PHY clock enable
+
+MOV R1, #0x800
+ORR R0, R2, #2
+STR R0, [R11,#0x804] @ USB2 Gadget: Soft disconnect
+
+STR R13, [R2] @ USB2 PHY: Power on
+STR R12, [R2,#0x08] @ USB2 PHY: Assert Software Reset
+MOV R0, #0x10000
+pms_wait:
+SUBS R0, R0, #1
+BNE pms_wait
+STR R13, [R2,#0x08] @ USB2 PHY: Deassert Software Reset
+STR R13, [R2,#0x04] @ USB2 PHY: Clock is 48MHz
+
+STR R12, [R11,#0x10] @ USB2 Gadget: Assert Core Software Reset
+pms_waitcorereset:
+LDR R0, [R11,#0x10] @ USB2 Gadget: Wait for Core to reset
+TST R0, #1
+BNE pms_waitcorereset
+TST R0, #0x80000000 @ USB2 Gadget: Wait for AHB IDLE
+BEQ pms_waitcorereset
+
+MOV R0, #0x200
+STR R0, [R11,#0x24] @ USB2 Gadget: RX FIFO size: 512 bytes
+ORR R0, R0, #0x2000000
+STR R0, [R11,#0x28] @ USB2 Gadget: Non-periodic TX FIFO size: 512 bytes
+MOV R0, #0x26
+STR R0, [R11,#0x08] @ USB2 Gadget: DMA Enable, Burst Length: 4, Mask Interrupts
+MOV R0, #0x1400
+ADD R0, R0, #8
+STR R0, [R11,#0x0C] @ USB2 Gadget: PHY IF is 16bit, Turnaround 5
+STR R1, [R11,#0x804] @ USB2 Gadget: Soft reconnect
+
+ADR R14, pms_ctrlbuf
+ORR R5, R8, #0x84000000
+@ fallthrough
+
+pms_mainloop:
+ LDR R3, [R11,#0x14] @ Global USB interrupts
+ TST R3, #0x00001000 @ BUS reset
+ BEQ pms_noreset
+ MOV R0, #0x500
+ STR R0, [R11,#0x804]
+ MOV R0, #4
+ STR R0, [R11,#0x800] @ USB2 Gadget: Device Address 0, STALL on non-zero length status stage
+ MOV R0, #0x8000
+ STR R0, [R11,#0x900] @ USB2 Gadget: Endpoint 0 IN Control: ACTIVE
+ STR R10, [R11,#0xB10] @ USB2 Gadget: Endpoint 0 OUT Transfer Size: 64 Bytes, 1 Packet, 1 Setup Packet
+ STR R14, [R11,#0xB14] @ USB2 Gadget: Endpoint 0 OUT DMA Address: pms_ctrlbuf
+ ORR R6, R0, #0x84000000
+ STR R6, [R11,#0xB00] @ USB2 Gadget: Endpoint 0 OUT Control: ENABLE CLEARNAK
+ STR R8, [R11,#0x960] @ USB2 Gadget: Endpoint 3 IN Control: ACTIVE BULK, 512 byte packets
+ STR R8, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ACTIVE BULK, 512 byte packets
+ STR R7, [R11,#0xB90] @ USB2 Gadget: Endpoint 4 OUT Transfer Size: 512 Bytes, 1 Packet
+ STR R9, [R11,#0xB94] @ USB2 Gadget: Endpoint 4 OUT DMA Address: pms_recvbuf
+ ORR R4, R5, #0x10000000
+ STR R4, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ENABLE CLEARNAK DATA0
+ pms_noreset:
+ LDR R0, [R11,#0x908] @ Just ACK all IN events...
+ STR R0, [R11,#0x908]
+ LDR R0, [R11,#0x968]
+ STR R0, [R11,#0x968]
+ LDR R2, [R11,#0xB08]
+ MOVS R2, R2 @ Event on OUT EP0
+ BEQ pms_noep0out
+ TST R2, #8 @ SETUP phase done
+ BEQ pms_controldone
+ LDRB R0, [R14,#1] @ Get request type
+ CMP R0, #0
+ BEQ pms_GET_STATUS
+ CMP R0, #1
+ BEQ pms_CLEAR_FEATURE
+ CMP R0, #3
+ BEQ pms_SET_FEATURE
+ CMP R0, #5
+ BEQ pms_SET_ADDRESS
+ CMP R0, #6
+ BEQ pms_GET_DESCRIPTOR
+ CMP R0, #8
+ BEQ pms_GET_CONFIGURATION
+ CMP R0, #9
+ BEQ pms_SET_CONFIGURATION
+ pms_ctrlstall:
+ LDR R0, [R11,#0x900]
+ ORR R0, R0, #0x00200000
+ STR R0, [R11,#0x900] @ Stall IN EP0
+ LDR R0, [R11,#0xB00]
+ ORR R0, R0, #0x00200000
+ STR R0, [R11,#0xB00] @ Stall OUT EP0
+ pms_controldone:
+ STR R10, [R11,#0xB10] @ OUT EP0: 64 Bytes, 1 Packet, 1 Setup Packet
+ STR R14, [R11,#0xB14] @ OUT EP0: DMA address
+ STR R6, [R11,#0xB00] @ OUT EP0: Enable ClearNAK
+ pms_noep0out:
+ STR R2, [R11,#0xB08] @ ACK it, whatever it was...
+ LDR R2, [R11,#0xB88]
+ MOVS R2, R2 @ Event on OUT EP4
+ BEQ pms_noep1out
+ TST R2, #1 @ XFER complete
+ BEQ pms_datadone
+ LDR R0, pms_000001FF
+ LDR R1, pms_recvbuf+4
+ ADD R0, R0, R1
+ MOV R0, R0,LSR#9
+ ORR R1, R1, R0,LSL#19 @ Number of packets
+ LDR R0, pms_recvbuf
+ STR R1, [R11,#0x970] @ EP3 IN: Number of packets, size
+ STR R0, [R11,#0x974] @ EP3 IN: DMA address
+ STR R5, [R11,#0x960] @ EP3 IN: Enable ClearNAK
+ pms_datadone:
+ STR R7, [R11,#0xB90] @ OUT EP4: 512 Bytes, 1 Packet
+ STR R9, [R11,#0xB94] @ Out EP4: DMA address
+ STR R5, [R11,#0xB80] @ Out EP4: Enable ClearNAK
+ pms_noep1out:
+ STR R2, [R11,#0xB88] @ ACK it, whatever it was...
+ STR R3, [R11,#0x14] @ ACK global ints
+B pms_mainloop
+
+pms_CLEAR_FEATURE:
+ LDRB R0, [R14]
+ CMP R0, #2
+ LDREQ R0, [R14,#2]
+ BICEQ R0, R0, #0x00800000
+ CMPEQ R0, #0x00010000
+@ fallthrough
+
+pms_SET_CONFIGURATION:
+ ORREQ R0, R8, #0x10000000
+ STREQ R0, [R11,#0x960] @ EP3 IN: Set DATA0 PID
+ STREQ R4, [R11,#0xB80] @ EP4 OUT: Set DATA0 PID
+B pms_SET_FEATURE @ zero-length ACK
+
+pms_GET_CONFIGURATION:
+ MOV R1, #1
+ STR R1, [R14]
+@ fallthrough
+
+pms_ctrlsend:
+ ORR R0, R1, #0x00080000 @ 1 Packet
+ STR R0, [R11,#0x910] @ EP0 IN: 1 Packet, Size as in R1
+ STR R14, [R11,#0x914] @ EP0 IN: DMA address
+ ORR R0, R6, #0x1800
+ STR R0, [R11,#0x900] @ EP0 IN: Enable ClearNAK
+ ADR R14, pms_ctrlbuf
+B pms_controldone
+
+pms_GET_DESCRIPTOR:
+ LDRB R0, [R14,#3] @ Descriptor type
+ CMP R0, #1
+ ADREQ R14, pms_devicedescriptor
+ BEQ pms_senddescriptor
+ CMP R0, #2
+ ADREQ R14, pms_configurationdescriptor
+ MOVEQ R1, #0x20
+ BEQ pms_senddescriptorcustomsize
+ CMP R0, #3
+ BNE pms_ctrlstall
+ LDRB R0, [R14,#2] @ String descriptor index
+ CMP R0, #0
+ LDREQ R0, pms_langstringdescriptor
+ STREQ R0, [R14]
+ BEQ pms_senddescriptor
+ CMP R0, #1
+ CMPNE R0, #2
+ ADREQ R14, pms_devnamestringdescriptor
+ BNE pms_ctrlstall
+@ fallthrough
+
+pms_senddescriptor:
+ LDRB R1, [R14] @ Descriptor length
+@ fallthrough
+
+pms_senddescriptorcustomsize:
+ LDRH R0, pms_ctrlbuf+6 @ Requested length
+ CMP R0, R1
+ MOVLO R1, R0
+B pms_ctrlsend
+
+pms_SET_ADDRESS:
+ LDRH R1, [R14,#2] @ new address
+ LDR R0, [R11,#0x800]
+ BIC R0, R0, #0x000007F0
+ ORR R0, R0, R1,LSL#4
+ STR R0, [R11,#0x800] @ set new address
+@ fallthrough
+
+pms_SET_FEATURE:
+ MOV R1, #0 @ zero-length ACK
+B pms_ctrlsend
+
+pms_20803180:
+.word 0x20803180
+
+.ltorg
+
+.align 4
+
+pms_configurationdescriptor:
+.word 0x00200209
+.word 0xC0000101
+.word 0x00040932
+.word 0xFFFF0200
+.word 0x050700FF
+.word 0x02000204
+.word 0x83050701
+.word 0x01020002
+
+pms_devicedescriptor:
+.word 0x02000112
+.word 0x40FFFFFF
+.word 0xA112FFFF
+.word 0x02010001
+.word 0x00010100
+
+pms_00080200:
+.word 0x00080200
+
+pms_20080040:
+.word 0x20080040
+
+pms_000001FF:
+.word 0x000001FF
+
+pms_devnamestringdescriptor:
+.word 0x0052030C
+.word 0x00500042
+.word 0x0053004D
+
+pms_langstringdescriptor:
+.word 0x04090304
+
+pms_ctrlbuf:
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+
+pms_recvbuf:
+.word 0
+.word 0
+
+pms_GET_STATUS:
+ LDRB R0, [R14]
+ CMP R0, #0x80
+ STREQ R12, [R14]
+ STRNE R13, [R14]
+ MOV R1, #2
+B pms_ctrlsend
+
+.size post_mortem_stub, .-post_mortem_stub
diff --git a/firmware/target/arm/s5l8702/debug-s5l8702.c b/firmware/target/arm/s5l8702/debug-s5l8702.c
index 5001d61f70..f49595aa00 100644
--- a/firmware/target/arm/s5l8702/debug-s5l8702.c
+++ b/firmware/target/arm/s5l8702/debug-s5l8702.c
@@ -1,166 +1,166 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: debug-s5l8700.c 28719 2010-12-01 18:35:01Z Buschel $
- *
- * Copyright © 2008 Rafaël Carré
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-
-#include <stdbool.h>
-#include "config.h"
-#include "kernel.h"
-#include "debug-target.h"
-#include "button.h"
-#include "lcd.h"
-#include "font.h"
-#include "storage.h"
-#include "power.h"
-#include "pmu-target.h"
-#include "pcm-target.h"
-
-/* Skeleton for adding target specific debug info to the debug menu
- */
-
-#define _DEBUG_PRINTF(a, varargs...) lcd_putsf(0, line++, (a), ##varargs);
-
-extern int lcd_type;
-bool dbg_hw_info(void)
-{
- int line;
- int i;
- unsigned int state = 0;
- const unsigned int max_states=3;
-
- lcd_clear_display();
- lcd_setfont(FONT_SYSFIXED);
-
- state=0;
- while(1)
- {
- lcd_clear_display();
- line = 0;
-
- if(state == 0)
- {
- _DEBUG_PRINTF("CPU:");
- _DEBUG_PRINTF("current_tick: %d", (unsigned int)current_tick);
- line++;
-
- _DEBUG_PRINTF("LCD type: %d", lcd_type);
- line++;
- }
- else if(state==1)
- {
- _DEBUG_PRINTF("PMU:");
- for(i=0;i<7;i++)
- {
- char *device[] = {"(unknown)",
- "(unknown)",
- "(unknown)",
- "(unknown)",
- "(unknown)",
- "(unknown)",
- "(unknown)"};
- _DEBUG_PRINTF("ldo%d %s: %dmV %s",i,
- pmu_read(0x2e + (i << 1))?" on":"off",
- 900 + pmu_read(0x2d + (i << 1))*100,
- device[i]);
- }
- _DEBUG_PRINTF("cpu voltage: %dmV",625 + pmu_read(0x1e)*25);
- _DEBUG_PRINTF("memory voltage: %dmV",625 + pmu_read(0x22)*25);
- line++;
- _DEBUG_PRINTF("charging: %s", charging_state() ? "true" : "false");
- _DEBUG_PRINTF("backlight: %s", pmu_read(0x29) ? "on" : "off");
- _DEBUG_PRINTF("brightness value: %d", pmu_read(0x28));
- }
- else if(state==2)
- {
- _DEBUG_PRINTF("Audio DMA:");
- _DEBUG_PRINTF(">%08X %08X %08X %08X %08X", DMAC0C0CONFIG, DMAC0C0SRCADDR,
- DMAC0C0DESTADDR, DMAC0C0NEXTLLI, DMAC0C0CONTROL);
- for(i = 0; i < PCM_LLICOUNT; i++)
- _DEBUG_PRINTF("%08X: %08X %08X %08X %08X", &pcm_lli[i], pcm_lli[i].srcaddr,
- pcm_lli[i].dstaddr, pcm_lli[i].nextlli, pcm_lli[i].control);
- _DEBUG_PRINTF("chunk: %08X %08X", pcm_chunksize, pcm_remaining);
- }
- else
- {
- state=0;
- }
-
-
- lcd_update();
- switch(button_get_w_tmo(HZ/20))
- {
- case BUTTON_SCROLL_BACK:
- if(state!=0) state--;
- break;
-
- case BUTTON_SCROLL_FWD:
- if(state!=max_states-1)
- {
- state++;
- }
- break;
-
- case DEBUG_CANCEL:
- case BUTTON_REL:
- lcd_setfont(FONT_UI);
- return false;
- }
- }
-
- lcd_setfont(FONT_UI);
- return false;
-}
-
-bool dbg_ports(void)
-{
- int line;
-
- lcd_setfont(FONT_SYSFIXED);
-
- while(1)
- {
- lcd_clear_display();
- line = 0;
-
- _DEBUG_PRINTF("GPIO 0: %08x",(unsigned int)PDAT(0));
- _DEBUG_PRINTF("GPIO 1: %08x",(unsigned int)PDAT(1));
- _DEBUG_PRINTF("GPIO 2: %08x",(unsigned int)PDAT(2));
- _DEBUG_PRINTF("GPIO 3: %08x",(unsigned int)PDAT(3));
- _DEBUG_PRINTF("GPIO 4: %08x",(unsigned int)PDAT(4));
- _DEBUG_PRINTF("GPIO 5: %08x",(unsigned int)PDAT(5));
- _DEBUG_PRINTF("GPIO 6: %08x",(unsigned int)PDAT(6));
- _DEBUG_PRINTF("GPIO 7: %08x",(unsigned int)PDAT(7));
- _DEBUG_PRINTF("GPIO 8: %08x",(unsigned int)PDAT(8));
- _DEBUG_PRINTF("GPIO 9: %08x",(unsigned int)PDAT(9));
- _DEBUG_PRINTF("GPIO 10: %08x",(unsigned int)PDAT(10));
- _DEBUG_PRINTF("GPIO 11: %08x",(unsigned int)PDAT(11));
- _DEBUG_PRINTF("GPIO 12: %08x",(unsigned int)PDAT(12));
- _DEBUG_PRINTF("GPIO 13: %08x",(unsigned int)PDAT(13));
- _DEBUG_PRINTF("GPIO 14: %08x",(unsigned int)PDAT(14));
- _DEBUG_PRINTF("GPIO 15: %08x",(unsigned int)PDAT(15));
- _DEBUG_PRINTF("USEC : %08x",(unsigned int)USEC_TIMER);
-
- lcd_update();
- if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
- break;
- }
- lcd_setfont(FONT_UI);
- return false;
-}
-
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: debug-s5l8700.c 28719 2010-12-01 18:35:01Z Buschel $
+ *
+ * Copyright © 2008 Rafaël Carré
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include <stdbool.h>
+#include "config.h"
+#include "kernel.h"
+#include "debug-target.h"
+#include "button.h"
+#include "lcd.h"
+#include "font.h"
+#include "storage.h"
+#include "power.h"
+#include "pmu-target.h"
+#include "pcm-target.h"
+
+/* Skeleton for adding target specific debug info to the debug menu
+ */
+
+#define _DEBUG_PRINTF(a, varargs...) lcd_putsf(0, line++, (a), ##varargs);
+
+extern int lcd_type;
+bool dbg_hw_info(void)
+{
+ int line;
+ int i;
+ unsigned int state = 0;
+ const unsigned int max_states=3;
+
+ lcd_clear_display();
+ lcd_setfont(FONT_SYSFIXED);
+
+ state=0;
+ while(1)
+ {
+ lcd_clear_display();
+ line = 0;
+
+ if(state == 0)
+ {
+ _DEBUG_PRINTF("CPU:");
+ _DEBUG_PRINTF("current_tick: %d", (unsigned int)current_tick);
+ line++;
+
+ _DEBUG_PRINTF("LCD type: %d", lcd_type);
+ line++;
+ }
+ else if(state==1)
+ {
+ _DEBUG_PRINTF("PMU:");
+ for(i=0;i<7;i++)
+ {
+ char *device[] = {"(unknown)",
+ "(unknown)",
+ "(unknown)",
+ "(unknown)",
+ "(unknown)",
+ "(unknown)",
+ "(unknown)"};
+ _DEBUG_PRINTF("ldo%d %s: %dmV %s",i,
+ pmu_read(0x2e + (i << 1))?" on":"off",
+ 900 + pmu_read(0x2d + (i << 1))*100,
+ device[i]);
+ }
+ _DEBUG_PRINTF("cpu voltage: %dmV",625 + pmu_read(0x1e)*25);
+ _DEBUG_PRINTF("memory voltage: %dmV",625 + pmu_read(0x22)*25);
+ line++;
+ _DEBUG_PRINTF("charging: %s", charging_state() ? "true" : "false");
+ _DEBUG_PRINTF("backlight: %s", pmu_read(0x29) ? "on" : "off");
+ _DEBUG_PRINTF("brightness value: %d", pmu_read(0x28));
+ }
+ else if(state==2)
+ {
+ _DEBUG_PRINTF("Audio DMA:");
+ _DEBUG_PRINTF(">%08X %08X %08X %08X %08X", DMAC0C0CONFIG, DMAC0C0SRCADDR,
+ DMAC0C0DESTADDR, DMAC0C0NEXTLLI, DMAC0C0CONTROL);
+ for(i = 0; i < PCM_LLICOUNT; i++)
+ _DEBUG_PRINTF("%08X: %08X %08X %08X %08X", &pcm_lli[i], pcm_lli[i].srcaddr,
+ pcm_lli[i].dstaddr, pcm_lli[i].nextlli, pcm_lli[i].control);
+ _DEBUG_PRINTF("chunk: %08X %08X", pcm_chunksize, pcm_remaining);
+ }
+ else
+ {
+ state=0;
+ }
+
+
+ lcd_update();
+ switch(button_get_w_tmo(HZ/20))
+ {
+ case BUTTON_SCROLL_BACK:
+ if(state!=0) state--;
+ break;
+
+ case BUTTON_SCROLL_FWD:
+ if(state!=max_states-1)
+ {
+ state++;
+ }
+ break;
+
+ case DEBUG_CANCEL:
+ case BUTTON_REL:
+ lcd_setfont(FONT_UI);
+ return false;
+ }
+ }
+
+ lcd_setfont(FONT_UI);
+ return false;
+}
+
+bool dbg_ports(void)
+{
+ int line;
+
+ lcd_setfont(FONT_SYSFIXED);
+
+ while(1)
+ {
+ lcd_clear_display();
+ line = 0;
+
+ _DEBUG_PRINTF("GPIO 0: %08x",(unsigned int)PDAT(0));
+ _DEBUG_PRINTF("GPIO 1: %08x",(unsigned int)PDAT(1));
+ _DEBUG_PRINTF("GPIO 2: %08x",(unsigned int)PDAT(2));
+ _DEBUG_PRINTF("GPIO 3: %08x",(unsigned int)PDAT(3));
+ _DEBUG_PRINTF("GPIO 4: %08x",(unsigned int)PDAT(4));
+ _DEBUG_PRINTF("GPIO 5: %08x",(unsigned int)PDAT(5));
+ _DEBUG_PRINTF("GPIO 6: %08x",(unsigned int)PDAT(6));
+ _DEBUG_PRINTF("GPIO 7: %08x",(unsigned int)PDAT(7));
+ _DEBUG_PRINTF("GPIO 8: %08x",(unsigned int)PDAT(8));
+ _DEBUG_PRINTF("GPIO 9: %08x",(unsigned int)PDAT(9));
+ _DEBUG_PRINTF("GPIO 10: %08x",(unsigned int)PDAT(10));
+ _DEBUG_PRINTF("GPIO 11: %08x",(unsigned int)PDAT(11));
+ _DEBUG_PRINTF("GPIO 12: %08x",(unsigned int)PDAT(12));
+ _DEBUG_PRINTF("GPIO 13: %08x",(unsigned int)PDAT(13));
+ _DEBUG_PRINTF("GPIO 14: %08x",(unsigned int)PDAT(14));
+ _DEBUG_PRINTF("GPIO 15: %08x",(unsigned int)PDAT(15));
+ _DEBUG_PRINTF("USEC : %08x",(unsigned int)USEC_TIMER);
+
+ lcd_update();
+ if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
+ break;
+ }
+ lcd_setfont(FONT_UI);
+ return false;
+}
+
diff --git a/firmware/target/arm/s5l8702/debug-target.h b/firmware/target/arm/s5l8702/debug-target.h
index 55ea497f00..a493c0e3dd 100644
--- a/firmware/target/arm/s5l8702/debug-target.h
+++ b/firmware/target/arm/s5l8702/debug-target.h
@@ -1,33 +1,33 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: debug-target.h 28522 2010-11-06 14:24:25Z wodz $
- *
- * Copyright (C) 2007 by Karl Kurbjun
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-
-#ifndef _DEBUG_TARGET_H_
-#define _DEBUG_TARGET_H_
-
-#include <stdbool.h>
-
-#define DEBUG_CANCEL BUTTON_MENU
-
-bool dbg_hw_info(void);
-bool dbg_ports(void);
-
-#endif /* _DEBUG_TARGET_H_ */
-
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: debug-target.h 28522 2010-11-06 14:24:25Z wodz $
+ *
+ * Copyright (C) 2007 by Karl Kurbjun
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef _DEBUG_TARGET_H_
+#define _DEBUG_TARGET_H_
+
+#include <stdbool.h>
+
+#define DEBUG_CANCEL BUTTON_MENU
+
+bool dbg_hw_info(void);
+bool dbg_ports(void);
+
+#endif /* _DEBUG_TARGET_H_ */
+
diff --git a/firmware/target/arm/s5l8702/i2c-s5l8702.c b/firmware/target/arm/s5l8702/i2c-s5l8702.c
index 294e5b58ce..4d0e4188ab 100644
--- a/firmware/target/arm/s5l8702/i2c-s5l8702.c
+++ b/firmware/target/arm/s5l8702/i2c-s5l8702.c
@@ -1,196 +1,196 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $
- *
- * Copyright (C) 2009 by Bertrik Sikken
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-
-#include "config.h"
-#include "system.h"
-#include "kernel.h"
-#include "i2c-s5l8702.h"
-
-/* Driver for the s5l8700 built-in I2C controller in master mode
-
- Both the i2c_read and i2c_write function take the following arguments:
- * slave, the address of the i2c slave device to read from / write to
- * address, optional sub-address in the i2c slave (unused if -1)
- * len, number of bytes to be transfered
- * data, pointer to data to be transfered
- A return value < 0 indicates an error.
-
- Note:
- * blocks the calling thread for the entire duraton of the i2c transfer but
- uses wakeup_wait/wakeup_signal to allow other threads to run.
- * ACK from slave is not checked, so functions never return an error
-*/
-
-static struct mutex i2c_mtx[2];
-
-static void i2c_on(int bus)
-{
- /* enable I2C clock */
- PWRCON(1) &= ~(1 << 4);
-
- IICCON(bus) = (1 << 7) | /* ACK_GEN */
- (0 << 6) | /* CLKSEL = PCLK/16 */
- (1 << 5) | /* INT_EN */
- (1 << 4) | /* IRQ clear */
- (7 << 0); /* CK_REG */
-
- /* serial output on */
- IICSTAT(bus) = (1 << 4);
-}
-
-static void i2c_off(int bus)
-{
- /* serial output off */
- IICSTAT(bus) = 0;
-
- /* disable I2C clock */
- PWRCON(1) |= (1 << 4);
-}
-
-void i2c_init()
-{
- mutex_init(&i2c_mtx[0]);
- mutex_init(&i2c_mtx[1]);
-}
-
-int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data)
-{
- mutex_lock(&i2c_mtx[bus]);
- i2c_on(bus);
- long timeout = current_tick + HZ / 50;
-
- /* START */
- IICDS(bus) = slave & ~1;
- IICSTAT(bus) = 0xF0;
- IICCON(bus) = 0xB3;
- while ((IICCON(bus) & 0x10) == 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 1;
- }
-
-
- if (address >= 0) {
- /* write address */
- IICDS(bus) = address;
- IICCON(bus) = 0xB3;
- while ((IICCON(bus) & 0x10) == 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 2;
- }
- }
-
- /* write data */
- while (len--) {
- IICDS(bus) = *data++;
- IICCON(bus) = 0xB3;
- while ((IICCON(bus) & 0x10) == 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 4;
- }
- }
-
- /* STOP */
- IICSTAT(bus) = 0xD0;
- IICCON(bus) = 0xB3;
- while ((IICSTAT(bus) & (1 << 5)) != 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 5;
- }
-
- i2c_off(bus);
- mutex_unlock(&i2c_mtx[bus]);
- return 0;
-}
-
-int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data)
-{
- mutex_lock(&i2c_mtx[bus]);
- i2c_on(bus);
- long timeout = current_tick + HZ / 50;
-
- if (address >= 0) {
- /* START */
- IICDS(bus) = slave & ~1;
- IICSTAT(bus) = 0xF0;
- IICCON(bus) = 0xB3;
- while ((IICCON(bus) & 0x10) == 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 1;
- }
-
- /* write address */
- IICDS(bus) = address;
- IICCON(bus) = 0xB3;
- while ((IICCON(bus) & 0x10) == 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 2;
- }
- }
-
- /* (repeated) START */
- IICDS(bus) = slave | 1;
- IICSTAT(bus) = 0xB0;
- IICCON(bus) = 0xB3;
- while ((IICCON(bus) & 0x10) == 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 3;
- }
-
- while (len--) {
- IICCON(bus) = (len == 0) ? 0x33 : 0xB3; /* NAK or ACK */
- while ((IICCON(bus) & 0x10) == 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 4;
- }
- *data++ = IICDS(bus);
- }
-
- /* STOP */
- IICSTAT(bus) = 0x90;
- IICCON(bus) = 0xB3;
- while ((IICSTAT(bus) & (1 << 5)) != 0)
- if (TIME_AFTER(current_tick, timeout))
- {
- mutex_unlock(&i2c_mtx[bus]);
- return 5;
- }
-
- i2c_off(bus);
- mutex_unlock(&i2c_mtx[bus]);
- return 0;
-}
-
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $
+ *
+ * Copyright (C) 2009 by Bertrik Sikken
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "system.h"
+#include "kernel.h"
+#include "i2c-s5l8702.h"
+
+/* Driver for the s5l8700 built-in I2C controller in master mode
+
+ Both the i2c_read and i2c_write function take the following arguments:
+ * slave, the address of the i2c slave device to read from / write to
+ * address, optional sub-address in the i2c slave (unused if -1)
+ * len, number of bytes to be transfered
+ * data, pointer to data to be transfered
+ A return value < 0 indicates an error.
+
+ Note:
+ * blocks the calling thread for the entire duraton of the i2c transfer but
+ uses wakeup_wait/wakeup_signal to allow other threads to run.
+ * ACK from slave is not checked, so functions never return an error
+*/
+
+static struct mutex i2c_mtx[2];
+
+static void i2c_on(int bus)
+{
+ /* enable I2C clock */
+ PWRCON(1) &= ~(1 << 4);
+
+ IICCON(bus) = (1 << 7) | /* ACK_GEN */
+ (0 << 6) | /* CLKSEL = PCLK/16 */
+ (1 << 5) | /* INT_EN */
+ (1 << 4) | /* IRQ clear */
+ (7 << 0); /* CK_REG */
+
+ /* serial output on */
+ IICSTAT(bus) = (1 << 4);
+}
+
+static void i2c_off(int bus)
+{
+ /* serial output off */
+ IICSTAT(bus) = 0;
+
+ /* disable I2C clock */
+ PWRCON(1) |= (1 << 4);
+}
+
+void i2c_init()
+{
+ mutex_init(&i2c_mtx[0]);
+ mutex_init(&i2c_mtx[1]);
+}
+
+int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data)
+{
+ mutex_lock(&i2c_mtx[bus]);
+ i2c_on(bus);
+ long timeout = current_tick + HZ / 50;
+
+ /* START */
+ IICDS(bus) = slave & ~1;
+ IICSTAT(bus) = 0xF0;
+ IICCON(bus) = 0xB3;
+ while ((IICCON(bus) & 0x10) == 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 1;
+ }
+
+
+ if (address >= 0) {
+ /* write address */
+ IICDS(bus) = address;
+ IICCON(bus) = 0xB3;
+ while ((IICCON(bus) & 0x10) == 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 2;
+ }
+ }
+
+ /* write data */
+ while (len--) {
+ IICDS(bus) = *data++;
+ IICCON(bus) = 0xB3;
+ while ((IICCON(bus) & 0x10) == 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 4;
+ }
+ }
+
+ /* STOP */
+ IICSTAT(bus) = 0xD0;
+ IICCON(bus) = 0xB3;
+ while ((IICSTAT(bus) & (1 << 5)) != 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 5;
+ }
+
+ i2c_off(bus);
+ mutex_unlock(&i2c_mtx[bus]);
+ return 0;
+}
+
+int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data)
+{
+ mutex_lock(&i2c_mtx[bus]);
+ i2c_on(bus);
+ long timeout = current_tick + HZ / 50;
+
+ if (address >= 0) {
+ /* START */
+ IICDS(bus) = slave & ~1;
+ IICSTAT(bus) = 0xF0;
+ IICCON(bus) = 0xB3;
+ while ((IICCON(bus) & 0x10) == 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 1;
+ }
+
+ /* write address */
+ IICDS(bus) = address;
+ IICCON(bus) = 0xB3;
+ while ((IICCON(bus) & 0x10) == 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 2;
+ }
+ }
+
+ /* (repeated) START */
+ IICDS(bus) = slave | 1;
+ IICSTAT(bus) = 0xB0;
+ IICCON(bus) = 0xB3;
+ while ((IICCON(bus) & 0x10) == 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 3;
+ }
+
+ while (len--) {
+ IICCON(bus) = (len == 0) ? 0x33 : 0xB3; /* NAK or ACK */
+ while ((IICCON(bus) & 0x10) == 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 4;
+ }
+ *data++ = IICDS(bus);
+ }
+
+ /* STOP */
+ IICSTAT(bus) = 0x90;
+ IICCON(bus) = 0xB3;
+ while ((IICSTAT(bus) & (1 << 5)) != 0)
+ if (TIME_AFTER(current_tick, timeout))
+ {
+ mutex_unlock(&i2c_mtx[bus]);
+ return 5;
+ }
+
+ i2c_off(bus);
+ mutex_unlock(&i2c_mtx[bus]);
+ return 0;
+}
+
diff --git a/firmware/target/arm/s5l8702/kernel-s5l8702.c b/firmware/target/arm/s5l8702/kernel-s5l8702.c
index 7c5a697043..af54e4dca4 100644
--- a/firmware/target/arm/s5l8702/kernel-s5l8702.c
+++ b/firmware/target/arm/s5l8702/kernel-s5l8702.c
@@ -1,56 +1,56 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: kernel-s5l8700.c 28795 2010-12-11 17:52:52Z Buschel $
- *
- * Copyright 2009 Bertrik Sikken
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#include "config.h"
-#include "system.h"
-#include "kernel.h"
-
-/* S5L8702 driver for the kernel timer
-
- Timer B is configured as a 10 kHz timer
- */
-
-void INT_TIMERB(void)
-{
- /* clear interrupt */
- TBCON = TBCON;
-
- call_tick_tasks(); /* Run through the list of tick tasks */
-}
-
-void tick_start(unsigned int interval_in_ms)
-{
- int cycles = 10 * interval_in_ms;
-
- /* configure timer for 10 kHz */
- TBCMD = (1 << 1); /* TB_CLR */
- TBPRE = 337 - 1; /* prescaler */
- TBCON = (0 << 13) | /* TB_INT1_EN */
- (1 << 12) | /* TB_INT0_EN */
- (0 << 11) | /* TB_START */
- (2 << 8) | /* TB_CS = PCLK / 16 */
- (0 << 4); /* TB_MODE_SEL = interval mode */
- TBDATA0 = cycles; /* set interval period */
- TBCMD = (1 << 0); /* TB_EN */
-
- /* enable timer interrupt */
- VIC0INTENABLE = 1 << IRQ_TIMER;
-}
-
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: kernel-s5l8700.c 28795 2010-12-11 17:52:52Z Buschel $
+ *
+ * Copyright 2009 Bertrik Sikken
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "system.h"
+#include "kernel.h"
+
+/* S5L8702 driver for the kernel timer
+
+ Timer B is configured as a 10 kHz timer
+ */
+
+void INT_TIMERB(void)
+{
+ /* clear interrupt */
+ TBCON = TBCON;
+
+ call_tick_tasks(); /* Run through the list of tick tasks */
+}
+
+void tick_start(unsigned int interval_in_ms)
+{
+ int cycles = 10 * interval_in_ms;
+
+ /* configure timer for 10 kHz */
+ TBCMD = (1 << 1); /* TB_CLR */
+ TBPRE = 337 - 1; /* prescaler */
+ TBCON = (0 << 13) | /* TB_INT1_EN */
+ (1 << 12) | /* TB_INT0_EN */
+ (0 << 11) | /* TB_START */
+ (2 << 8) | /* TB_CS = PCLK / 16 */
+ (0 << 4); /* TB_MODE_SEL = interval mode */
+ TBDATA0 = cycles; /* set interval period */
+ TBCMD = (1 << 0); /* TB_EN */
+
+ /* enable timer interrupt */
+ VIC0INTENABLE = 1 << IRQ_TIMER;
+}
+
diff --git a/firmware/target/arm/s5l8702/pcm-s5l8702.c b/firmware/target/arm/s5l8702/pcm-s5l8702.c
index c3df77f14f..6461418744 100644
--- a/firmware/target/arm/s5l8702/pcm-s5l8702.c
+++ b/firmware/target/arm/s5l8702/pcm-s5l8702.c
@@ -1,228 +1,228 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: pcm-s5l8700.c 28600 2010-11-14 19:49:20Z Buschel $
- *
- * Copyright © 2011 Michael Sparmann
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#include <string.h>
-
-#include "config.h"
-#include "system.h"
-#include "audio.h"
-#include "s5l8702.h"
-#include "panic.h"
-#include "audiohw.h"
-#include "pcm.h"
-#include "pcm-internal.h"
-#include "pcm_sampr.h"
-#include "mmu-arm.h"
-#include "pcm-target.h"
-
-static volatile int locked = 0;
-static const int zerosample = 0;
-static unsigned char dblbuf[2][PCM_WATERMARK * 4];
-static int active_dblbuf;
-struct dma_lli pcm_lli[PCM_LLICOUNT] __attribute__((aligned(16)));
-static struct dma_lli* lastlli;
-static const unsigned char* dataptr;
-size_t pcm_remaining;
-size_t pcm_chunksize;
-
-/* Mask the DMA interrupt */
-void pcm_play_lock(void)
-{
- if (locked++ == 0) {
- //TODO: Urgh, I don't like that at all...
- VIC0INTENCLEAR = 1 << IRQ_DMAC0;
- }
-}
-
-/* Unmask the DMA interrupt if enabled */
-void pcm_play_unlock(void)
-{
- if (--locked == 0) {
- VIC0INTENABLE = 1 << IRQ_DMAC0;
- }
-}
-
-void INT_DMAC0C0(void) ICODE_ATTR;
-void INT_DMAC0C0(void)
-{
- DMAC0INTTCCLR = 1;
- if (!pcm_remaining)
- {
- pcm_play_get_more_callback((void**)&dataptr, &pcm_remaining);
- pcm_chunksize = pcm_remaining;
- }
- if (!pcm_remaining)
- {
- pcm_lli->nextlli = NULL;
- pcm_lli->control = 0x75249000;
- clean_dcache();
- return;
- }
- uint32_t lastsize = MIN(PCM_WATERMARK * 4, pcm_remaining / 2 + 1) & ~1;
- pcm_remaining -= lastsize;
- if (pcm_remaining) lastlli = &pcm_lli[ARRAYLEN(pcm_lli) - 1];
- else lastlli = pcm_lli;
- uint32_t chunksize = MIN(PCM_CHUNKSIZE * 4 - lastsize, pcm_remaining);
- if (pcm_remaining > chunksize && chunksize > pcm_remaining - PCM_WATERMARK * 8)
- chunksize = pcm_remaining - PCM_WATERMARK * 8;
- pcm_remaining -= chunksize;
- bool last = !chunksize;
- int i = 0;
- while (chunksize)
- {
- uint32_t thislli = MIN(PCM_LLIMAX * 4, chunksize);
- chunksize -= thislli;
- pcm_lli[i].srcaddr = (void*)dataptr;
- pcm_lli[i].dstaddr = (void*)((int)&I2STXDB0);
- pcm_lli[i].nextlli = chunksize ? &pcm_lli[i + 1] : lastlli;
- pcm_lli[i].control = (chunksize ? 0x75249000 : 0xf5249000) | (thislli / 2);
- dataptr += thislli;
- i++;
- }
- if (!pcm_remaining)
- {
- memcpy(dblbuf[active_dblbuf], dataptr, lastsize);
- lastlli->srcaddr = dblbuf[active_dblbuf];
- active_dblbuf ^= 1;
- }
- else lastlli->srcaddr = dataptr;
- lastlli->dstaddr = (void*)((int)&I2STXDB0);
- lastlli->nextlli = last ? NULL : pcm_lli;
- lastlli->control = (last ? 0xf5249000 : 0x75249000) | (lastsize / 2);
- dataptr += lastsize;
- clean_dcache();
- if (!(DMAC0C0CONFIG & 1) && (pcm_lli[0].control & 0xfff))
- {
- DMAC0C0LLI = pcm_lli[0];
- DMAC0C0CONFIG = 0x8a81;
- }
- else DMAC0C0NEXTLLI = pcm_lli;
-
- pcm_play_dma_started_callback();
-}
-
-void pcm_play_dma_start(const void* addr, size_t size)
-{
- dataptr = (const unsigned char*)addr;
- pcm_remaining = size;
- I2STXCOM = 0xe;
- DMAC0CONFIG |= 4;
- INT_DMAC0C0();
-}
-
-void pcm_play_dma_stop(void)
-{
- DMAC0C0CONFIG = 0x8a80;
- I2STXCOM = 0xa;
-}
-
-/* pause playback by disabling LRCK */
-void pcm_play_dma_pause(bool pause)
-{
- if (pause) I2STXCOM |= 1;
- else I2STXCOM &= ~1;
-}
-
-void pcm_play_dma_init(void)
-{
- PWRCON(0) &= ~(1 << 4);
- PWRCON(1) &= ~(1 << 7);
- I2S40 = 0x110;
- I2STXCON = 0xb100059;
- I2SCLKCON = 1;
- VIC0INTENABLE = 1 << IRQ_DMAC0;
-
- audiohw_preinit();
-}
-
-void pcm_play_dma_postinit(void)
-{
- audiohw_postinit();
-}
-
-void pcm_dma_apply_settings(void)
-{
-}
-
-size_t pcm_get_bytes_waiting(void)
-{
- int bytes = pcm_remaining;
- const struct dma_lli* lli = (const struct dma_lli*)((int)&DMAC0C0LLI);
- while (lli)
- {
- bytes += (lli->control & 0xfff) * 2;
- if (lli == lastlli) break;
- lli = lli->nextlli;
- }
- return bytes;
-}
-
-const void* pcm_play_dma_get_peak_buffer(int *count)
-{
- *count = (DMAC0C0LLI.control & 0xfff) * 2;
- return (void*)(((uint32_t)DMAC0C0LLI.srcaddr) & ~3);
-}
-
-#ifdef HAVE_PCM_DMA_ADDRESS
-void * pcm_dma_addr(void *addr)
-{
- return addr;
-}
-#endif
-
-
-/****************************************************************************
- ** Recording DMA transfer
- **/
-#ifdef HAVE_RECORDING
-void pcm_rec_lock(void)
-{
-}
-
-void pcm_rec_unlock(void)
-{
-}
-
-void pcm_rec_dma_stop(void)
-{
-}
-
-void pcm_rec_dma_start(void *addr, size_t size)
-{
- (void)addr;
- (void)size;
-}
-
-void pcm_rec_dma_close(void)
-{
-}
-
-
-void pcm_rec_dma_init(void)
-{
-}
-
-
-const void * pcm_rec_dma_get_peak_buffer(void)
-{
- return NULL;
-}
-
-#endif /* HAVE_RECORDING */
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: pcm-s5l8700.c 28600 2010-11-14 19:49:20Z Buschel $
+ *
+ * Copyright © 2011 Michael Sparmann
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <string.h>
+
+#include "config.h"
+#include "system.h"
+#include "audio.h"
+#include "s5l8702.h"
+#include "panic.h"
+#include "audiohw.h"
+#include "pcm.h"
+#include "pcm-internal.h"
+#include "pcm_sampr.h"
+#include "mmu-arm.h"
+#include "pcm-target.h"
+
+static volatile int locked = 0;
+static const int zerosample = 0;
+static unsigned char dblbuf[2][PCM_WATERMARK * 4];
+static int active_dblbuf;
+struct dma_lli pcm_lli[PCM_LLICOUNT] __attribute__((aligned(16)));
+static struct dma_lli* lastlli;
+static const unsigned char* dataptr;
+size_t pcm_remaining;
+size_t pcm_chunksize;
+
+/* Mask the DMA interrupt */
+void pcm_play_lock(void)
+{
+ if (locked++ == 0) {
+ //TODO: Urgh, I don't like that at all...
+ VIC0INTENCLEAR = 1 << IRQ_DMAC0;
+ }
+}
+
+/* Unmask the DMA interrupt if enabled */
+void pcm_play_unlock(void)
+{
+ if (--locked == 0) {
+ VIC0INTENABLE = 1 << IRQ_DMAC0;
+ }
+}
+
+void INT_DMAC0C0(void) ICODE_ATTR;
+void INT_DMAC0C0(void)
+{
+ DMAC0INTTCCLR = 1;
+ if (!pcm_remaining)
+ {
+ pcm_play_get_more_callback((void**)&dataptr, &pcm_remaining);
+ pcm_chunksize = pcm_remaining;
+ }
+ if (!pcm_remaining)
+ {
+ pcm_lli->nextlli = NULL;
+ pcm_lli->control = 0x75249000;
+ clean_dcache();
+ return;
+ }
+ uint32_t lastsize = MIN(PCM_WATERMARK * 4, pcm_remaining / 2 + 1) & ~1;
+ pcm_remaining -= lastsize;
+ if (pcm_remaining) lastlli = &pcm_lli[ARRAYLEN(pcm_lli) - 1];
+ else lastlli = pcm_lli;
+ uint32_t chunksize = MIN(PCM_CHUNKSIZE * 4 - lastsize, pcm_remaining);
+ if (pcm_remaining > chunksize && chunksize > pcm_remaining - PCM_WATERMARK * 8)
+ chunksize = pcm_remaining - PCM_WATERMARK * 8;
+ pcm_remaining -= chunksize;
+ bool last = !chunksize;
+ int i = 0;
+ while (chunksize)
+ {
+ uint32_t thislli = MIN(PCM_LLIMAX * 4, chunksize);
+ chunksize -= thislli;
+ pcm_lli[i].srcaddr = (void*)dataptr;
+ pcm_lli[i].dstaddr = (void*)((int)&I2STXDB0);
+ pcm_lli[i].nextlli = chunksize ? &pcm_lli[i + 1] : lastlli;
+ pcm_lli[i].control = (chunksize ? 0x75249000 : 0xf5249000) | (thislli / 2);
+ dataptr += thislli;
+ i++;
+ }
+ if (!pcm_remaining)
+ {
+ memcpy(dblbuf[active_dblbuf], dataptr, lastsize);
+ lastlli->srcaddr = dblbuf[active_dblbuf];
+ active_dblbuf ^= 1;
+ }
+ else lastlli->srcaddr = dataptr;
+ lastlli->dstaddr = (void*)((int)&I2STXDB0);
+ lastlli->nextlli = last ? NULL : pcm_lli;
+ lastlli->control = (last ? 0xf5249000 : 0x75249000) | (lastsize / 2);
+ dataptr += lastsize;
+ clean_dcache();
+ if (!(DMAC0C0CONFIG & 1) && (pcm_lli[0].control & 0xfff))
+ {
+ DMAC0C0LLI = pcm_lli[0];
+ DMAC0C0CONFIG = 0x8a81;
+ }
+ else DMAC0C0NEXTLLI = pcm_lli;
+
+ pcm_play_dma_started_callback();
+}
+
+void pcm_play_dma_start(const void* addr, size_t size)
+{
+ dataptr = (const unsigned char*)addr;
+ pcm_remaining = size;
+ I2STXCOM = 0xe;
+ DMAC0CONFIG |= 4;
+ INT_DMAC0C0();
+}
+
+void pcm_play_dma_stop(void)
+{
+ DMAC0C0CONFIG = 0x8a80;
+ I2STXCOM = 0xa;
+}
+
+/* pause playback by disabling LRCK */
+void pcm_play_dma_pause(bool pause)
+{
+ if (pause) I2STXCOM |= 1;
+ else I2STXCOM &= ~1;
+}
+
+void pcm_play_dma_init(void)
+{
+ PWRCON(0) &= ~(1 << 4);
+ PWRCON(1) &= ~(1 << 7);
+ I2S40 = 0x110;
+ I2STXCON = 0xb100059;
+ I2SCLKCON = 1;
+ VIC0INTENABLE = 1 << IRQ_DMAC0;
+
+ audiohw_preinit();
+}
+
+void pcm_play_dma_postinit(void)
+{
+ audiohw_postinit();
+}
+
+void pcm_dma_apply_settings(void)
+{
+}
+
+size_t pcm_get_bytes_waiting(void)
+{
+ int bytes = pcm_remaining;
+ const struct dma_lli* lli = (const struct dma_lli*)((int)&DMAC0C0LLI);
+ while (lli)
+ {
+ bytes += (lli->control & 0xfff) * 2;
+ if (lli == lastlli) break;
+ lli = lli->nextlli;
+ }
+ return bytes;
+}
+
+const void* pcm_play_dma_get_peak_buffer(int *count)
+{
+ *count = (DMAC0C0LLI.control & 0xfff) * 2;
+ return (void*)(((uint32_t)DMAC0C0LLI.srcaddr) & ~3);
+}
+
+#ifdef HAVE_PCM_DMA_ADDRESS
+void * pcm_dma_addr(void *addr)
+{
+ return addr;
+}
+#endif
+
+
+/****************************************************************************
+ ** Recording DMA transfer
+ **/
+#ifdef HAVE_RECORDING
+void pcm_rec_lock(void)
+{
+}
+
+void pcm_rec_unlock(void)
+{
+}
+
+void pcm_rec_dma_stop(void)
+{
+}
+
+void pcm_rec_dma_start(void *addr, size_t size)
+{
+ (void)addr;
+ (void)size;
+}
+
+void pcm_rec_dma_close(void)
+{
+}
+
+
+void pcm_rec_dma_init(void)
+{
+}
+
+
+const void * pcm_rec_dma_get_peak_buffer(void)
+{
+ return NULL;
+}
+
+#endif /* HAVE_RECORDING */
diff --git a/firmware/target/arm/s5l8702/pcm-target.h b/firmware/target/arm/s5l8702/pcm-target.h
index 1b149a6e0b..aefb64e328 100644
--- a/firmware/target/arm/s5l8702/pcm-target.h
+++ b/firmware/target/arm/s5l8702/pcm-target.h
@@ -1,40 +1,40 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $
- *
- * Copyright (C) 2010 by Michael Sparmann
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __PCM_TARGET_H__
-#define __PCM_TARGET_H__
-
-
-/* S5L8702 PCM driver tunables: */
-#define PCM_LLIMAX (2047) /* Maximum number of samples per LLI */
-#define PCM_CHUNKSIZE (10747) /* Maximum number of samples to handle with one IRQ */
- /* (bigger chunks will be segmented internally) */
-#define PCM_WATERMARK (512) /* Number of remaining samples to schedule IRQ at */
-
-
-#define PCM_LLICOUNT ((PCM_CHUNKSIZE - PCM_WATERMARK + PCM_LLIMAX - 1) / PCM_LLIMAX + 1)
-
-
-extern struct dma_lli pcm_lli[PCM_LLICOUNT];
-extern size_t pcm_remaining;
-extern size_t pcm_chunksize;
-
-
-#endif /* __PCM_TARGET_H__ */
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $
+ *
+ * Copyright (C) 2010 by Michael Sparmann
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __PCM_TARGET_H__
+#define __PCM_TARGET_H__
+
+
+/* S5L8702 PCM driver tunables: */
+#define PCM_LLIMAX (2047) /* Maximum number of samples per LLI */
+#define PCM_CHUNKSIZE (10747) /* Maximum number of samples to handle with one IRQ */
+ /* (bigger chunks will be segmented internally) */
+#define PCM_WATERMARK (512) /* Number of remaining samples to schedule IRQ at */
+
+
+#define PCM_LLICOUNT ((PCM_CHUNKSIZE - PCM_WATERMARK + PCM_LLIMAX - 1) / PCM_LLIMAX + 1)
+
+
+extern struct dma_lli pcm_lli[PCM_LLICOUNT];
+extern size_t pcm_remaining;
+extern size_t pcm_chunksize;
+
+
+#endif /* __PCM_TARGET_H__ */
diff --git a/firmware/target/arm/s5l8702/system-target.h b/firmware/target/arm/s5l8702/system-target.h
index 30e53ad6ea..799efb7006 100644
--- a/firmware/target/arm/s5l8702/system-target.h
+++ b/firmware/target/arm/s5l8702/system-target.h
@@ -1,47 +1,47 @@
-/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $
- *
- * Copyright (C) 2007 by Dave Chapman
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef SYSTEM_TARGET_H
-#define SYSTEM_TARGET_H
-
-#include "system-arm.h"
-#include "mmu-arm.h"
-
-#define CPUFREQ_SLEEP 32768
-#define CPUFREQ_MAX 216000000
-#define CPUFREQ_DEFAULT 108000000
-#define CPUFREQ_NORMAL 108000000
-
-#define STORAGE_WANTS_ALIGN
-
-#define inl(a) (*(volatile unsigned long *) (a))
-#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
-#define inb(a) (*(volatile unsigned char *) (a))
-#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
-#define inw(a) (*(volatile unsigned short*) (a))
-#define outw(a,b) (*(volatile unsigned short*) (b) = (a))
-
-static inline void udelay(unsigned usecs)
-{
- unsigned stop = USEC_TIMER + usecs;
- while (TIME_BEFORE(USEC_TIMER, stop));
-}
-
-#endif /* SYSTEM_TARGET_H */
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $
+ *
+ * Copyright (C) 2007 by Dave Chapman
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef SYSTEM_TARGET_H
+#define SYSTEM_TARGET_H
+
+#include "system-arm.h"
+#include "mmu-arm.h"
+
+#define CPUFREQ_SLEEP 32768
+#define CPUFREQ_MAX 216000000
+#define CPUFREQ_DEFAULT 108000000
+#define CPUFREQ_NORMAL 108000000
+
+#define STORAGE_WANTS_ALIGN
+
+#define inl(a) (*(volatile unsigned long *) (a))
+#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
+#define inb(a) (*(volatile unsigned char *) (a))
+#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
+#define inw(a) (*(volatile unsigned short*) (a))
+#define outw(a,b) (*(volatile unsigned short*) (b) = (a))
+
+static inline void udelay(unsigned usecs)
+{
+ unsigned stop = USEC_TIMER + usecs;
+ while (TIME_BEFORE(USEC_TIMER, stop));
+}
+
+#endif /* SYSTEM_TARGET_H */
diff --git a/firmware/target/arm/s5l8702/timer-s5l8702.c b/firmware/target/arm/s5l8702/timer-s5l8702.c
index fb56a9ffcf..61d4d590e4 100644
--- a/firmware/target/arm/s5l8702/timer-s5l8702.c
+++ b/firmware/target/arm/s5l8702/timer-s5l8702.c
@@ -1,94 +1,94 @@
-/***************************************************************************
-* __________ __ ___.
-* Open \______ \ ____ ____ | | _\_ |__ _______ ___
-* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
-* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
-* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
-* \/ \/ \/ \/ \/
-* $Id: timer-s5l8700.c 23103 2009-10-11 11:35:14Z theseven $
-*
-* Copyright (C) 2009 Bertrik Sikken
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License
-* as published by the Free Software Foundation; either version 2
-* of the License, or (at your option) any later version.
-*
-* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
-* KIND, either express or implied.
-*
-****************************************************************************/
-
-#include "config.h"
-
-#include "inttypes.h"
-#include "s5l8702.h"
-#include "system.h"
-#include "timer.h"
-
-//TODO: This needs calibration once we figure out the clocking
-
-void INT_TIMERC(void)
-{
- /* clear interrupt */
- TCCON = TCCON;
-
- if (pfn_timer != NULL) {
- pfn_timer();
- }
-}
-
-bool timer_set(long cycles, bool start)
-{
- static const int cs_table[] = {1, 2, 4, 6};
- int prescale, cs;
- long count;
-
- /* stop and clear timer */
- TCCMD = (1 << 1); /* TD_CLR */
-
- /* optionally unregister any previously registered timer user */
- if (start) {
- if (pfn_unregister != NULL) {
- pfn_unregister();
- pfn_unregister = NULL;
- }
- }
-
- /* scale the count down with the clock select */
- for (cs = 0; cs < 4; cs++) {
- count = cycles >> cs_table[cs];
- if ((count < 65536) || (cs == 3)) {
- break;
- }
- }
-
- /* scale the count down with the prescaler */
- prescale = 1;
- while (count >= 65536) {
- count >>= 1;
- prescale <<= 1;
- }
-
- /* configure timer */
- TCCON = (1 << 12) | /* TD_INT0_EN */
- (cs << 8) | /* TS_CS */
- (0 << 4); /* TD_MODE_SEL, 0 = interval mode */
- TCPRE = prescale - 1;
- TCDATA0 = count;
- TCCMD = (1 << 0); /* TD_ENABLE */
-
- return true;
-}
-
-bool timer_start(void)
-{
- TCCMD = (1 << 0); /* TD_ENABLE */
- return true;
-}
-
-void timer_stop(void)
-{
- TCCMD = (0 << 0); /* TD_ENABLE */
-}
-
+/***************************************************************************
+* __________ __ ___.
+* Open \______ \ ____ ____ | | _\_ |__ _______ ___
+* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+* \/ \/ \/ \/ \/
+* $Id: timer-s5l8700.c 23103 2009-10-11 11:35:14Z theseven $
+*
+* Copyright (C) 2009 Bertrik Sikken
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+* KIND, either express or implied.
+*
+****************************************************************************/
+
+#include "config.h"
+
+#include "inttypes.h"
+#include "s5l8702.h"
+#include "system.h"
+#include "timer.h"
+
+//TODO: This needs calibration once we figure out the clocking
+
+void INT_TIMERC(void)
+{
+ /* clear interrupt */
+ TCCON = TCCON;
+
+ if (pfn_timer != NULL) {
+ pfn_timer();
+ }
+}
+
+bool timer_set(long cycles, bool start)
+{
+ static const int cs_table[] = {1, 2, 4, 6};
+ int prescale, cs;
+ long count;
+
+ /* stop and clear timer */
+ TCCMD = (1 << 1); /* TD_CLR */
+
+ /* optionally unregister any previously registered timer user */
+ if (start) {
+ if (pfn_unregister != NULL) {
+ pfn_unregister();
+ pfn_unregister = NULL;
+ }
+ }
+
+ /* scale the count down with the clock select */
+ for (cs = 0; cs < 4; cs++) {
+ count = cycles >> cs_table[cs];
+ if ((count < 65536) || (cs == 3)) {
+ break;
+ }
+ }
+
+ /* scale the count down with the prescaler */
+ prescale = 1;
+ while (count >= 65536) {
+ count >>= 1;
+ prescale <<= 1;
+ }
+
+ /* configure timer */
+ TCCON = (1 << 12) | /* TD_INT0_EN */
+ (cs << 8) | /* TS_CS */
+ (0 << 4); /* TD_MODE_SEL, 0 = interval mode */
+ TCPRE = prescale - 1;
+ TCDATA0 = count;
+ TCCMD = (1 << 0); /* TD_ENABLE */
+
+ return true;
+}
+
+bool timer_start(void)
+{
+ TCCMD = (1 << 0); /* TD_ENABLE */
+ return true;
+}
+
+void timer_stop(void)
+{
+ TCCMD = (0 << 0); /* TD_ENABLE */
+}
+
diff --git a/firmware/target/sh/archos/mascodec-archos.c b/firmware/target/sh/archos/mascodec-archos.c
index 3f932166eb..1eb6e1044d 100644
--- a/firmware/target/sh/archos/mascodec-archos.c
+++ b/firmware/target/sh/archos/mascodec-archos.c
@@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
- * $Id: mas.c 18807 2008-10-14 11:12:20Z zagor $
+ * $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*