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authorJack Halpin <jack.halpin@gmail.com>2010-03-24 02:48:38 +0000
committerJack Halpin <jack.halpin@gmail.com>2010-03-24 02:48:38 +0000
commit66f011e8c14a416a167e293dc91767ae6eda818c (patch)
treefbe02a294097595c20c1a09a48d45efd326aa4af /firmware
parent56199d3dfba2c2454c1226fac5d98e84ecf11cd1 (diff)
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sd-as3525v2.c Adjust comments for MCI_INT bits to show if they are related to CMD, DATA, or a termination signal.
Adjust the initial MCI_MASK value to also mask the MCI_INT_RXDR and MCI_INT_TXDR bits as it seems we don't use them for dma transfers. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25314 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/target/arm/as3525/sd-as3525v2.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/firmware/target/arm/as3525/sd-as3525v2.c b/firmware/target/arm/as3525/sd-as3525v2.c
index 250dfca784..1546bcbd30 100644
--- a/firmware/target/arm/as3525/sd-as3525v2.c
+++ b/firmware/target/arm/as3525/sd-as3525v2.c
@@ -157,23 +157,23 @@
#define MCI_RAW_STATUS SD_REG(0x44) /* raw interrupt status, also used as
* status clear */
-/* interrupt bits */
-#define MCI_INT_CRDDET (1<<0) /* card detect */
-#define MCI_INT_RE (1<<1) /* response error */
-#define MCI_INT_CD (1<<2) /* command done */
-#define MCI_INT_DTO (1<<3) /* data transfer over */
-#define MCI_INT_TXDR (1<<4) /* tx fifo data request */
-#define MCI_INT_RXDR (1<<5) /* rx fifo data request */
-#define MCI_INT_RCRC (1<<6) /* response crc error */
-#define MCI_INT_DCRC (1<<7) /* data crc error */
-#define MCI_INT_RTO (1<<8) /* response timeout */
-#define MCI_INT_DRTO (1<<9) /* data read timeout */
-#define MCI_INT_HTO (1<<10) /* data starv timeout */
-#define MCI_INT_FRUN (1<<11) /* fifo over/underrun */
-#define MCI_INT_HLE (1<<12) /* hw locked while error */
-#define MCI_INT_SBE (1<<13) /* start bit error */
-#define MCI_INT_ACD (1<<14) /* auto command done */
-#define MCI_INT_EBE (1<<15) /* end bit error */
+/* interrupt bits */ /* C D E (Cmd) (Data) (End) */
+#define MCI_INT_CRDDET (1<<0) /* card detect */
+#define MCI_INT_RE (1<<1) /* x response error */
+#define MCI_INT_CD (1<<2) /* x command done */
+#define MCI_INT_DTO (1<<3) /* x data transfer over */
+#define MCI_INT_TXDR (1<<4) /* tx fifo data request */
+#define MCI_INT_RXDR (1<<5) /* rx fifo data request */
+#define MCI_INT_RCRC (1<<6) /* x response crc error */
+#define MCI_INT_DCRC (1<<7) /* x data crc error */
+#define MCI_INT_RTO (1<<8) /* x response timeout */
+#define MCI_INT_DRTO (1<<9) /* x data read timeout */
+#define MCI_INT_HTO (1<<10) /* x data starv timeout */
+#define MCI_INT_FRUN (1<<11) /* x fifo over/underrun */
+#define MCI_INT_HLE (1<<12) /* x x hw locked while error */
+#define MCI_INT_SBE (1<<13) /* x start bit error */
+#define MCI_INT_ACD (1<<14) /* auto command done */
+#define MCI_INT_EBE (1<<15) /* x end bit error */
#define MCI_INT_SDIO (0xf<<16)
/*
@@ -631,7 +631,7 @@ static void init_controller(void)
MCI_FIFOTH &= MCI_FIFOTH_MASK;
MCI_FIFOTH |= 0x503f0080;
- MCI_MASK = 0xffffffff & ~(MCI_INT_ACD|MCI_INT_CRDDET);
+ MCI_MASK = 0xffff & ~(MCI_INT_ACD|MCI_INT_CRDDET|MCI_INT_RXDR|MCI_INT_TXDR);
GPIOB_DIR |= (1<<5); /* Pin B5 output */