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authorMichael Sevakis <jethead71@rockbox.org>2008-04-17 00:07:06 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-04-17 00:07:06 +0000
commit99a65dfc1ef034da43de56ae7a4964946d5d67f3 (patch)
treedcd1e749f408501fcd0c21e9d76f281a464c3bc3 /firmware
parent7fee4868f975c6de13fe4f5fe1f82546d0e0eadd (diff)
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Cache functions should include data and instruction barriers.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17150 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/system-target.h9
-rw-r--r--firmware/target/arm/mmu-arm.c16
2 files changed, 18 insertions, 7 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
index 17f1593f62..e48b5d1ed1 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -42,8 +42,13 @@ static inline void invalidate_icache(void)
asm volatile(
/* Clean and invalidate entire data cache */
"mcr p15, 0, %0, c7, c14, 0 \n"
- /* Invalidate entire instruction cache */
+ /* Invalidate entire intruction cache
+ * Also flushes the branch target cache */
"mcr p15, 0, %0, c7, c5, 0 \n"
+ /* Data synchronization barrier */
+ "mcr p15, 0, %0, c7, c10, 4 \n"
+ /* Flush prefetch buffer */
+ "mcr p15, 0, %0, c7, c5, 4 \n"
: : "r"(0)
);
}
@@ -54,6 +59,8 @@ static inline void flush_icache(void)
asm volatile (
/* Clean entire data cache */
"mcr p15, 0, %0, c7, c10, 0 \n"
+ /* Data synchronization barrier */
+ "mcr p15, 0, r2, c7, c10, 4 \n"
: : "r"(0)
);
}
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c
index 5fa05d1dc6..ffca7a43ee 100644
--- a/firmware/target/arm/mmu-arm.c
+++ b/firmware/target/arm/mmu-arm.c
@@ -90,9 +90,11 @@ void enable_mmu(void) {
void __attribute__((naked)) invalidate_dcache_range(const void *base, unsigned int size)
{
asm volatile(
- "add r1, r1, r0 \n"
- "mcrr p15, 0, r1, r0, c14 \n"
- "bx lr \n"
+ "add r1, r1, r0 \n"
+ "mov r2, #0 \n"
+ "mcrr p15, 0, r1, r0, c14 \n" /* Clean and invalidate dcache range */
+ "mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
+ "bx lr \n"
);
(void)base; (void)size;
}
@@ -140,9 +142,11 @@ void invalidate_dcache_range(const void *base, unsigned int size) {
void __attribute__((naked)) clean_dcache_range(const void *base, unsigned int size)
{
asm volatile(
- "add r1, r1, r0 \n"
- "mcrr p15, 0, r1, r0, c12 \n"
- "bx lr \n"
+ "add r1, r1, r0 \n"
+ "mov r2, #0 \n"
+ "mcrr p15, 0, r1, r0, c12 \n" /* Clean dcache range */
+ "mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
+ "bx lr \n"
);
(void)base; (void)size;
}