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authorRafaël Carré <rafael.carre@gmail.com>2010-03-26 00:11:50 +0000
committerRafaël Carré <rafael.carre@gmail.com>2010-03-26 00:11:50 +0000
commitb6065a8ceb83655d265c6c4adc4f30f7436e7bd7 (patch)
tree1833e26e122f680aa235a0c210c3754d13c0f8ac /firmware
parente108d571ba6d74552f679c7251df4d0e85c5fd00 (diff)
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Use STORAGE_WANTS_ALIGN to make clear it's not a strict necessity
Define PROC_NEEDS_CACHEALIGN only for PP git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25339 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/export/system.h29
-rw-r--r--firmware/target/arm/s5l8700/system-target.h4
-rw-r--r--firmware/target/arm/system-target.h2
3 files changed, 15 insertions, 20 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h
index 7dd01b5c93..9df382bc24 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -293,11 +293,13 @@ static inline void cpucache_flush(void)
}
#endif
-#ifdef PROC_NEEDS_CACHEALIGN
-/* Cache alignment attributes and sizes are enabled */
-
+#ifdef CACHEALIGN_BITS
/* 2^CACHEALIGN_BITS = the byte size */
#define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS)
+#endif
+
+#ifdef PROC_NEEDS_CACHEALIGN
+/* Cache alignment attributes and sizes are enabled */
#define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE)))
/* Aligns x up to a CACHEALIGN_SIZE boundary */
@@ -312,16 +314,6 @@ static inline void cpucache_flush(void)
/* Aligns a buffer pointer and size to proper boundaries */
#define CACHEALIGN_BUFFER(start, size) \
ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE)
-/* Pad a size so the buffer can be aligned later */
-#define CACHE_PAD(x) ((x) + CACHEALIGN_SIZE - 1)
-/* Number of bytes in the last cacheline assuming buffer of size x is aligned */
-#define CACHE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1))
-
-#ifdef NEEDS_STORAGE_ALIGN
-#define STORAGE_ALIGN_DOWN(x) CACHEALIGN_DOWN(x)
-#define STORAGE_PAD(x) CACHE_PAD(x)
-#define STORAGE_OVERLAP(x) CACHE_OVERLAP(x)
-#endif
#else /* ndef PROC_NEEDS_CACHEALIGN */
@@ -333,12 +325,17 @@ static inline void cpucache_flush(void)
#define CACHEALIGN_DOWN(x) (x)
/* Make no adjustments */
#define CACHEALIGN_BUFFER(start, size)
-#define CACHE_PAD(x) (x)
-#define CACHE_OVERLAP(x) 0
#endif /* PROC_NEEDS_CACHEALIGN */
-#if !defined(PROC_NEEDS_CACHEALIGN) || !defined(NEEDS_STORAGE_ALIGN)
+#ifdef STORAGE_WANTS_ALIGN
+#define STORAGE_ALIGN_DOWN(x) \
+ ((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS))
+/* Pad a size so the buffer can be aligned later */
+#define STORAGE_PAD(x) ((x) + CACHEALIGN_SIZE - 1)
+/* Number of bytes in the last cacheline assuming buffer of size x is aligned */
+#define STORAGE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1))
+#else
#define STORAGE_ALIGN_DOWN(x) (x)
#define STORAGE_PAD(x) (x)
#define STORAGE_OVERLAP(x) 0
diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h
index c531344b64..5f91032d9e 100644
--- a/firmware/target/arm/s5l8700/system-target.h
+++ b/firmware/target/arm/s5l8700/system-target.h
@@ -29,10 +29,8 @@
#define CPUFREQ_NORMAL 47923200
#define CPUFREQ_MAX 191692800
-/* DMA engine needs aligned addresses */
-#define PROC_NEEDS_CACHEALIGN
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
-#define NEEDS_STORAGE_ALIGN
+#define WANTS_STORAGE_ALIGN
#define inl(a) (*(volatile unsigned long *) (a))
#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 1422e6467a..157a450743 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -164,7 +164,7 @@ static inline void wake_core(int core)
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
-#define NEEDS_STORAGE_ALIGN
+#define STORAGE_WANTS_ALIGN
#endif
/** cache functions **/