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authorSolomon Peachy <pizza@shaftnet.org>2018-08-20 11:12:58 -0400
committerMarcin Bukat <marcin.bukat@gmail.com>2018-09-07 09:55:12 +0200
commitbe801c61bbe95d75e4285da1982017da7fa1736b (patch)
treea56c4629b961e5c8e29eaf2b059b9ff54577baa5 /firmware
parent734be0d6aa79e47871bd9746394b2f5c98df5fcf (diff)
downloadrockbox-be801c61bbe95d75e4285da1982017da7fa1736b.tar.gz
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mips: Update the MIPS threading code
Taken from Amaury Pouly's Fiio X1 patches in gerrit. Xduoo X3 no longer panics on startup Change-Id: I4c2dee832306755b9e496084cb47fb61f804af20
Diffstat (limited to 'firmware')
-rw-r--r--firmware/asm/mips/thread-mips32.c83
-rw-r--r--firmware/asm/mips/thread.h17
2 files changed, 47 insertions, 53 deletions
diff --git a/firmware/asm/mips/thread-mips32.c b/firmware/asm/mips/thread-mips32.c
index 3e38685f1b..b8e684bb80 100644
--- a/firmware/asm/mips/thread-mips32.c
+++ b/firmware/asm/mips/thread-mips32.c
@@ -26,23 +26,24 @@
*---------------------------------------------------------------------------
*/
-static void USED_ATTR start_thread(void *addr)
+void start_thread(void); /* Provide C access to ASM label */
+static void USED_ATTR _start_thread(void)
{
+ /* t1 = context */
asm volatile (
+ "start_thread: \n"
".set noreorder \n"
".set noat \n"
- "lw $25, 4(%0) \n" /* Fetch thread function pointer ($25 = t9) */
- "lw $25, 40(%0) \n" /* Set initial sp(=$29) */
- "jalr $25 \n" /* Start the thread */
- "sw $0, 48(%0) \n" /* Clear start address */
+ "lw $8, 4($9) \n" /* Fetch thread function pointer ($8 = t0, $9 = t1) */
+ "lw $29, 36($9) \n" /* Set initial sp(=$29) */
+ "jalr $8 \n" /* Start the thread */
+ "sw $0, 44($9) \n" /* Clear start address */
".set at \n"
".set reorder \n"
- : : "r" (addr) : "$25"
);
thread_exit();
}
-
/* Place context pointer in s0 slot, function pointer in s1 slot, and
* start_thread pointer in context_start */
#define THREAD_STARTUP_INIT(core, thread, function) \
@@ -59,21 +60,25 @@ static inline void store_context(void* addr)
asm volatile (
".set noreorder \n"
".set noat \n"
- "sw $16, 0(%0) \n" /* s0 */
- "sw $17, 4(%0) \n" /* s1 */
- "sw $18, 8(%0) \n" /* s2 */
- "sw $19, 12(%0) \n" /* s3 */
- "sw $20, 16(%0) \n" /* s4 */
- "sw $21, 20(%0) \n" /* s5 */
- "sw $22, 24(%0) \n" /* s6 */
- "sw $23, 28(%0) \n" /* s7 */
- "sw $28, 32(%0) \n" /* gp */
- "sw $30, 36(%0) \n" /* fp */
- "sw $29, 40(%0) \n" /* sp */
- "sw $31, 44(%0) \n" /* ra */
+ "move $8, %0 \n" /* Store addr in clobbered t0 othrewise
+ * compiler could select %0 to be s0-s7
+ * during inlining which would break
+ * things horribly.
+ */
+ "sw $16, 0($8) \n" /* s0 */
+ "sw $17, 4($8) \n" /* s1 */
+ "sw $18, 8($8) \n" /* s2 */
+ "sw $19, 12($8) \n" /* s3 */
+ "sw $20, 16($8) \n" /* s4 */
+ "sw $21, 20($8) \n" /* s5 */
+ "sw $22, 24($8) \n" /* s6 */
+ "sw $23, 28($8) \n" /* s7 */
+ "sw $30, 32($8) \n" /* fp */
+ "sw $29, 36($8) \n" /* sp */
+ "sw $31, 40($8) \n" /* ra */
".set at \n"
".set reorder \n"
- : : "r" (addr)
+ : : "r" (addr) : "t0"
);
}
@@ -86,27 +91,31 @@ static inline void load_context(const void* addr)
asm volatile (
".set noat \n"
".set noreorder \n"
- "lw $25, 48(%0) \n" /* Get start address (t9 = $25) */
- "beqz $25, running \n" /* NULL -> already running */
+ "lw $8, 44(%0) \n" /* Get start address ($8 = t0) */
+ "beqz $8, running \n" /* NULL -> already running */
"nop \n"
- "jr $25 \n"
- "move $4, %0 \n" /* a0 = context branch delay slot anyway */
+ "jr $8 \n"
+ "move $9, %0 \n" /* t1 = context */
"running: \n"
- "lw $16, 0(%0) \n" /* s0 */
- "lw $17, 4(%0) \n" /* s1 */
- "lw $18, 8(%0) \n" /* s2 */
- "lw $19, 12(%0) \n" /* s3 */
- "lw $20, 16(%0) \n" /* s4 */
- "lw $21, 20(%0) \n" /* s5 */
- "lw $22, 24(%0) \n" /* s6 */
- "lw $23, 28(%0) \n" /* s7 */
- "lw $28, 32(%0) \n" /* gp */
- "lw $30, 36(%0) \n" /* fp */
- "lw $29, 40(%0) \n" /* sp */
- "lw $31, 44(%0) \n" /* ra */
+ "move $8, %0 \n" /* Store addr in clobbered t0 otherwise
+ * compiler could select %0 to be s0-s7
+ * during inlining which would break
+ * things horribly.
+ */
+ "lw $16, 0($8) \n" /* s0 */
+ "lw $17, 4($8) \n" /* s1 */
+ "lw $18, 8($8) \n" /* s2 */
+ "lw $19, 12($8) \n" /* s3 */
+ "lw $20, 16($8) \n" /* s4 */
+ "lw $21, 20($8) \n" /* s5 */
+ "lw $22, 24($8) \n" /* s6 */
+ "lw $23, 28($8) \n" /* s7 */
+ "lw $30, 32($8) \n" /* fp */
+ "lw $29, 36($8) \n" /* sp */
+ "lw $31, 40($8) \n" /* ra */
".set at \n"
".set reorder \n"
- : : "r" (addr) : "$25"
+ : : "r" (addr) : "t0", "t1"
);
}
diff --git a/firmware/asm/mips/thread.h b/firmware/asm/mips/thread.h
index 42b0f7049f..ac37560a68 100644
--- a/firmware/asm/mips/thread.h
+++ b/firmware/asm/mips/thread.h
@@ -19,24 +19,9 @@
*
****************************************************************************/
-/* index offset register
- * 0 0 $16 s0
- * 1 4 $17 s1
- * 2 8 $18 s2
- * 3 12 $19 s3
- * 4 16 $20 s4
- * 5 20 $21 s5
- * 6 24 $22 s6
- * 7 28 $23 s7
- * 8 32 $28 gp
- * 9 36 $30 s8 (s8)
- * 10 40 $29 sp
- * 11 44 $31 ra
- * 12 48 start
- */
struct regs
{
- uint32_t r[10]; /* 0-32 - Registers s0-s7, gp, fp */
+ uint32_t r[9]; /* 0-32 - Registers s0-s7, fp */
uint32_t sp; /* 36 - Stack pointer */
uint32_t ra; /* 40 - Return address */
uint32_t start; /* 44 - Thread start address, or NULL when started */