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authorAmaury Pouly <amaury.pouly@gmail.com>2014-04-12 00:08:11 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2014-04-12 00:11:13 +0200
commit238be18d0331a7a87e3ea8ea0d24b78e451357cb (patch)
tree31807bf3fd533d2d0d3d4eb0421b08100cc67c25 /utils/hwstub/stub/pp/crt0.S
parent910235b49a754fcd18157dbd22e125a32b482c9d (diff)
downloadrockbox-238be18d0331a7a87e3ea8ea0d24b78e451357cb.tar.gz
rockbox-238be18d0331a7a87e3ea8ea0d24b78e451357cb.zip
hwstub: add proper PP support
- drop support for PP500x: it's very different from other PP and although it would be possible to support them, I don't have one to test the code - make sure only the CPU is started - add PP descriptor to report chip ID and revision - add code in shell and lua to support pp (no register description yet) - compile for ARMv4 because PP502x is an ARM7TDMI Change-Id: I36c4e465dfc2cfdfe7433b2f65cc8f6f0720fe62
Diffstat (limited to 'utils/hwstub/stub/pp/crt0.S')
-rw-r--r--utils/hwstub/stub/pp/crt0.S31
1 files changed, 21 insertions, 10 deletions
diff --git a/utils/hwstub/stub/pp/crt0.S b/utils/hwstub/stub/pp/crt0.S
index 38b6f18ac5..a128391286 100644
--- a/utils/hwstub/stub/pp/crt0.S
+++ b/utils/hwstub/stub/pp/crt0.S
@@ -5,9 +5,25 @@
start:
sub r7, pc, #8 /* Copy running address */
msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
- /* The stub could be located at a virtual address so killing the MMU at
- * this point would be mere suicide. We assume that the remap location
- * is identically mapped and kill the MMU after the copy */
+
+ /* Get processor ID */
+ ldr r0, =0x60000000 /* PROC_ID */
+ ldrb r4, [r0]
+
+ /* Halt the COP */
+ ldr r6, =0x60007004 /* COP_CTL */
+ cmp r4, #0x55 /* CPU_ID */
+1:
+ ldrne r1, [r6]
+ orrne r1, #0x80000000 /* PROC_SLEEP */
+ strne r1, [r6]
+ bne 1b
+
+ /* Wait for the COP to be stopped */
+1:
+ ldr r0, [r6]
+ tst r0, #0x80000000 /* PROC_SLEEP */
+ beq 1b
/* Relocate to right address */
mov r2, r7
@@ -19,16 +35,11 @@ start:
strhi r5, [r3], #4
bhi 1b
mov r2, #0
- mcr p15, 0, r2, c7, c5, 0 @ Invalidate ICache
+ /* FIXME invalid Icache here ? */
/* Jump to real location */
ldr pc, =remap
remap:
- /* Disable MMU, disable caching and buffering;
- * use low exception range address */
- mrc p15, 0, r0, c1, c0, 0
- ldr r1, =0x3005
- bic r0, r1
- mcr p15, 0, r0, c1, c0, 0
+ /* NOTE on PP611x, we should make sure the MMU is disabled at this point */
/* clear bss */
ldr r2, =bss_start
ldr r3, =bss_end