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authorAmaury Pouly <amaury.pouly@gmail.com>2016-03-19 21:51:21 +0000
committerAmaury Pouly <amaury.pouly@gmail.com>2017-01-24 15:17:46 +0100
commit0b6cbd8e49eaf664cd005c6bb63a3111a4f4c308 (patch)
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regtools: add JZ4760B description
This is a register description file for the JZ4760B. There are several details worth noticing: - it was obtained by gathering information from several sources/headers, but since there are inconsistencies between them about the exact differences between JZ4760 and JZ4760B, this file probably contains some errors - the register names are not the same as the manual ones (which are not the same as the one in the headers anyway): I dropped the "R" suffix on most registers because it's redundant - Ingenic likes to have read-only registers and then set/clr registers, with very confusing names like DIR/DIRS/DIRC: in the file, the set/clr registers are described as set/clr variants of the original register - Parts of the description were obtained programmatically, which explains why there are empty nodes or partially undocumented registers Change-Id: I8da1d61e172e932e1a4a58ac0a5008f02b1751be
Diffstat (limited to 'utils/regtools')
-rw-r--r--utils/regtools/desc/regs-jz4760b.xml13645
1 files changed, 13645 insertions, 0 deletions
diff --git a/utils/regtools/desc/regs-jz4760b.xml b/utils/regtools/desc/regs-jz4760b.xml
new file mode 100644
index 0000000000..2ff16e7c2b
--- /dev/null
+++ b/utils/regtools/desc/regs-jz4760b.xml
@@ -0,0 +1,13645 @@
+<?xml version="1.0"?>
+<soc version="2">
+ <name>jz4760b</name>
+ <author>Amaury Pouly</author>
+ <isa>mips (xburst)</isa>
+ <version>1.0</version>
+ <node>
+ <name>IPU_P</name>
+ <instance>
+ <name>IPU_P</name>
+ <address>0x13080000</address>
+ </instance>
+ </node>
+ <node>
+ <name>CPM</name>
+ <instance>
+ <name>CPM</name>
+ <address>0xb0000000</address>
+ </instance>
+ <node>
+ <name>CTRL</name>
+ <title>Clock control register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>ECS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>MEM</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>SDIV</name>
+ <position>24</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>CE</name>
+ <position>22</position>
+ </field>
+ <field>
+ <name>PCS</name>
+ <position>21</position>
+ </field>
+ <field>
+ <name>H2DIV</name>
+ <position>16</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>MDIV</name>
+ <position>12</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>PDIV</name>
+ <position>8</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>HDIV</name>
+ <position>4</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>CDIV</name>
+ <position>0</position>
+ <width>4</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>LOW</name>
+ <title>Low power control register</title>
+ <instance>
+ <name>LOW</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>PDAHB1</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>VBATIR</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>PDGPS</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>PDAHB1S</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>PDGPSS</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>PST</name>
+ <position>8</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>DUTY</name>
+ <position>3</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>DOZE</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>LPM</name>
+ <position>0</position>
+ <width>2</width>
+ <enum>
+ <name>IDLE</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>SLEEP</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RESET</name>
+ <title>Reset status register</title>
+ <instance>
+ <name>RESET</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>P0R</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>WR</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>PR</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PLL0</name>
+ <title>PLL control register 0</title>
+ <instance>
+ <name>PL</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <field>
+ <name>PLLM</name>
+ <position>24</position>
+ <width>7</width>
+ </field>
+ <field>
+ <name>PLLN</name>
+ <position>18</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>PLLOD</name>
+ <position>16</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <desc>LOCK0 bit</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>ENLOCK</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>PLLS</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>PLLBP</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>PLLEN</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>PLLST</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PLLSWITCH</name>
+ <title>PLL switch and status register</title>
+ <instance>
+ <name>PLLSWITCH</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <field>
+ <name>PLLOFF</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>PLLBP</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>PLLON</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>PS</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>FS</name>
+ <position>27</position>
+ </field>
+ <field>
+ <name>CS</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>SM</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>PM</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>FM</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>GATE0</name>
+ <title>Clock gate register 0</title>
+ <instance>
+ <name>GATE0</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <field>
+ <name>EMC</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>DDR</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>IPU</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>LCD</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>TVE</name>
+ <position>27</position>
+ </field>
+ <field>
+ <name>CIM</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>MDMA</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>UHC</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>MAC</name>
+ <position>23</position>
+ </field>
+ <field>
+ <name>GPS</name>
+ <position>22</position>
+ </field>
+ <field>
+ <name>DMAC</name>
+ <position>21</position>
+ </field>
+ <field>
+ <name>SSI2</name>
+ <position>20</position>
+ </field>
+ <field>
+ <name>SSI1</name>
+ <position>19</position>
+ </field>
+ <field>
+ <name>UART3</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>UART2</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>UART1</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>UART0</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>SADC</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>KBC</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>MSC2</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>MSC1</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>OWI</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>TSSI</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>AIC</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>SCC</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>I2C1</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>I2C0</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>SSI0</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>MSC0</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>OTG</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>BCH</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>NEMC</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OSC</name>
+ <title>Oscillator and power control register</title>
+ <instance>
+ <name>OSC</name>
+ <address>0x24</address>
+ </instance>
+ <register>
+ <field>
+ <name>O1ST</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>OTGPHY_ENABLE</name>
+ <desc>SPENDN bit</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>GPSEN</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>UHCPHY_DISABLE</name>
+ <desc>SPENDH bit</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>O1SE</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>PD</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>ERCS</name>
+ <position>2</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>GATE1</name>
+ <title>Clock gate register 1</title>
+ <instance>
+ <name>GATE1</name>
+ <address>0x28</address>
+ </instance>
+ <register>
+ <field>
+ <name>AUX</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>OSD</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>GPU</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>PCM</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>AHB1</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>CABAC</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>SRAM</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>DCT</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>ME</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>DBLK</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>MC</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>BDMA</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PLL1</name>
+ <title>PLL control register 1</title>
+ <instance>
+ <name>PLL1</name>
+ <address>0x30</address>
+ </instance>
+ <register>
+ <field>
+ <name>PLL1M</name>
+ <position>24</position>
+ <width>7</width>
+ </field>
+ <field>
+ <name>PLL1N</name>
+ <position>18</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>PLL1OD</name>
+ <position>16</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>P1SCS</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>P1SDIV</name>
+ <position>9</position>
+ <width>6</width>
+ </field>
+ <field>
+ <name>PLL1EN</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>PLL1S</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <desc>LOCK1 bit</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>PLL1OFF</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>PLL1ON</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SCRATCH</name>
+ <title>CPM scratch pad register</title>
+ <instance>
+ <name>SCRATCH</name>
+ <address>0x34</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>SCRATCHPROT</name>
+ <title>CPM scratch pad protected register</title>
+ <instance>
+ <name>SCRATCHPROT</name>
+ <address>0x38</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>USBPARAM</name>
+ <title>OTG parameter control register</title>
+ <instance>
+ <name>USBPARAM</name>
+ <address>0x3c</address>
+ </instance>
+ <register>
+ <field>
+ <name>USB_MODE</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>AVLD_REG</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>IDPULLUP</name>
+ <desc>IDPULLUP_MASK bit</desc>
+ <position>28</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>INCRM</name>
+ <desc>INCR_MASK bit</desc>
+ <position>27</position>
+ </field>
+ <field>
+ <name>CLK12_EN</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>COMMONONN</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>VBUSVLDEXT</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>VBUSVLDEXTSEL</name>
+ <position>23</position>
+ </field>
+ <field>
+ <name>POR</name>
+ <position>22</position>
+ </field>
+ <field>
+ <name>SIDDQ</name>
+ <position>21</position>
+ </field>
+ <field>
+ <name>OTG_DISABLE</name>
+ <position>20</position>
+ </field>
+ <field>
+ <name>COMPDISTUNE</name>
+ <position>17</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>OTGTUNE</name>
+ <position>14</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>SQRXTUNE</name>
+ <position>11</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>TXFSLSTUNE</name>
+ <position>7</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TXPREEMPHTUNE</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>TXRISETUNE</name>
+ <position>4</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>TXVREFTUNE</name>
+ <position>0</position>
+ <width>4</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>USBRESET</name>
+ <title>OTG reset detect timer register</title>
+ <instance>
+ <name>USBRESET</name>
+ <address>0x40</address>
+ </instance>
+ <register>
+ <field>
+ <name>VBFIL_LD_EN</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>IDDIG_EN</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>IDDIG_REG</name>
+ <position>23</position>
+ </field>
+ <field>
+ <name>USBRDT</name>
+ <position>0</position>
+ <width>23</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>USBVBUS</name>
+ <instance>
+ <name>USBVBUS</name>
+ <address>0x44</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>USB</name>
+ <title>OTG PHY clock divider register</title>
+ <instance>
+ <name>USB</name>
+ <address>0x50</address>
+ </instance>
+ <register>
+ <field>
+ <name>UCS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>UPCS</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>OTGDIV</name>
+ <desc>USBCDR bit</desc>
+ <position>0</position>
+ <width>6</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>I2S</name>
+ <title>I2S device clock divider register</title>
+ <instance>
+ <name>I2S</name>
+ <address>0x60</address>
+ </instance>
+ <register>
+ <field>
+ <name>I2CS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>I2PCS</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>I2SDIV</name>
+ <desc>I2SCDR bit</desc>
+ <position>0</position>
+ <width>9</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>LCD</name>
+ <title>LCD pix clock divider register</title>
+ <instance>
+ <name>LCD</name>
+ <address>0x64</address>
+ </instance>
+ <register>
+ <field>
+ <name>LTCS</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>LPCS</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>PIXDIV</name>
+ <desc>LPCDR bit</desc>
+ <position>0</position>
+ <width>11</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>MSC</name>
+ <title>MSC clock divider register</title>
+ <instance>
+ <name>MSC</name>
+ <address>0x68</address>
+ </instance>
+ <register>
+ <field>
+ <name>MCS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>MSCDIV</name>
+ <desc>MSCCDR bit</desc>
+ <position>0</position>
+ <width>6</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>UHC</name>
+ <title>UHC device clock divider register</title>
+ <instance>
+ <name>UHC</name>
+ <address>0x6c</address>
+ </instance>
+ <register>
+ <field>
+ <name>UHPCS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>UHCDIV</name>
+ <desc>UHCCDR bit</desc>
+ <position>0</position>
+ <width>4</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SSI</name>
+ <title>SSI clock divider register</title>
+ <instance>
+ <name>SSI</name>
+ <address>0x74</address>
+ </instance>
+ <register>
+ <field>
+ <name>SCS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>SSIDIV</name>
+ <desc>SSICDR bit</desc>
+ <position>0</position>
+ <width>6</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CIM</name>
+ <title>CIM mclk clock divider register</title>
+ <instance>
+ <name>CIM</name>
+ <address>0x7c</address>
+ </instance>
+ <register>
+ <field>
+ <name>CIMDIV</name>
+ <desc>CIMCDR bit</desc>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>GPS</name>
+ <title>GPS clock divider register</title>
+ <instance>
+ <name>GPS</name>
+ <address>0x80</address>
+ </instance>
+ <register>
+ <field>
+ <name>GPCS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>GPSDIV</name>
+ <desc>GPSCDR bit</desc>
+ <position>0</position>
+ <width>4</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PCM</name>
+ <title>PCM device clock divider register</title>
+ <instance>
+ <name>PCM</name>
+ <address>0x84</address>
+ </instance>
+ <register>
+ <field>
+ <name>PCMS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>PCMPCS</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>PCMDIV</name>
+ <desc>PCMCDR bit</desc>
+ <position>0</position>
+ <width>9</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>GPU</name>
+ <instance>
+ <name>GPU</name>
+ <address>0x88</address>
+ </instance>
+ <register>
+ <field>
+ <name>GPCS</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>GPUDIV</name>
+ <desc>GPUCDR bit</desc>
+ <position>0</position>
+ <width>3</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PSWC0ST</name>
+ <instance>
+ <name>PSWC0ST</name>
+ <address>0x90</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PSWC1ST</name>
+ <instance>
+ <name>PSWC1ST</name>
+ <address>0x94</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PSWC2ST</name>
+ <instance>
+ <name>PSWC2ST</name>
+ <address>0x98</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PSWC3ST</name>
+ <instance>
+ <name>PSWC3ST</name>
+ <address>0x9c</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>INTC</name>
+ <title>INTC (Interrupt Controller)</title>
+ <instance>
+ <name>INTC</name>
+ <address>0xb0001000</address>
+ </instance>
+ <node>
+ <name>ISR</name>
+ <instance>
+ <name>ISR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">0x00 + (n) * 0x20</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>IMR</name>
+ <instance>
+ <name>IMR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">0x04 + (n) * 0x20</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>IMSR</name>
+ <instance>
+ <name>IMSR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">0x08 + (n) * 0x20</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>IMCR</name>
+ <instance>
+ <name>IMCR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">0x0c + (n) * 0x20</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>IPR</name>
+ <instance>
+ <name>IPR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">0x10 + (n) * 0x20</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>OST</name>
+ <title>Operating System Timer</title>
+ <instance>
+ <name>OST</name>
+ <address>0xb0002000</address>
+ </instance>
+ <node>
+ <name>DATA</name>
+ <title>Data register</title>
+ <instance>
+ <name>DATA</name>
+ <address>0xe0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>COUNTL</name>
+ <title>Count (low part)</title>
+ <instance>
+ <name>COUNTL</name>
+ <address>0xe4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>COUNTH</name>
+ <title>Count (high-part)</title>
+ <instance>
+ <name>COUNTH</name>
+ <address>0xe8</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CTRL</name>
+ <title>Operating system control register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0xec</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>CNT_MD</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>SD</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>PRESCALE</name>
+ <position>3</position>
+ <width>3</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>64</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>256</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>1024</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>EXT_EN</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RTC_EN</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>PCK_EN</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>COUNTH_BUF</name>
+ <instance>
+ <name>OSTCNTH_BUF</name>
+ <address>0xfc</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>TCU</name>
+ <title>Timer and counter unit module</title>
+ <instance>
+ <name>TCU</name>
+ <address>0xb0002000</address>
+ </instance>
+ <node>
+ <name>ENABLE</name>
+ <title>Timer counter enable register</title>
+ <instance>
+ <name>ENABLE</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>OSTEN</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>TCEN</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>STOP</name>
+ <title>Timer stop register</title>
+ <instance>
+ <name>STOP</name>
+ <address>0x1c</address>
+ </instance>
+ <register>
+ <field>
+ <name>WDT_STOP</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>OST_STOP</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>TIMER_STOP</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ <variant>
+ <type>set</type>
+ <offset>16</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>32</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>FLAG</name>
+ <title>Timer flag register</title>
+ <instance>
+ <name>FLAG</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <field>
+ <name>HFLAG</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>OSTFLAG</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>FFLAG</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>MASK</name>
+ <title>Timer mask register</title>
+ <instance>
+ <name>TMR</name>
+ <address>0x30</address>
+ </instance>
+ <register>
+ <field>
+ <name>HMASK</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>OSTMASK</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>FMASK</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>DATA_FULL</name>
+ <title>Timer data full register</title>
+ <instance>
+ <name>DATA_FULL</name>
+ <range>
+ <first>0</first>
+ <count>8</count>
+ <formula variable="n">(n) * 0x10 + 0x40</formula>
+ </range>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>TDFR</name>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DATA_HALF</name>
+ <title>Timer data half register</title>
+ <instance>
+ <name>DATA_HALF</name>
+ <range>
+ <first>0</first>
+ <count>8</count>
+ <formula variable="n">(n) * 0x10 + 0x44</formula>
+ </range>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>TDHR</name>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>COUNT</name>
+ <title>Timer counter register</title>
+ <instance>
+ <name>COUNT</name>
+ <range>
+ <first>0</first>
+ <count>8</count>
+ <formula variable="n">(n) * 0x10 + 0x48</formula>
+ </range>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>TCNT</name>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CTRL</name>
+ <title>Timer control register</title>
+ <instance>
+ <name>CTRL</name>
+ <range>
+ <first>0</first>
+ <count>8</count>
+ <formula variable="n">(n) * 0x10 + 0x4c</formula>
+ </range>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>CLRZ</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>SD_ABRUPT</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>INITL_HIGH</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>PWM_EN</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>PWM_IN_EN</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>PRESCALE</name>
+ <position>3</position>
+ <width>3</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>64</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>256</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>1024</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>EXT_EN</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RTC_EN</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>PCK_EN</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>STATUS</name>
+ <title>Timer status register</title>
+ <instance>
+ <name>TSTR</name>
+ <address>0xf0</address>
+ </instance>
+ <register>
+ <field>
+ <name>REAL2</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>REAL1</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>BUSY2</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>BUSY1</name>
+ <position>1</position>
+ </field>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>WDT</name>
+ <title>Watchdog timer module</title>
+ <instance>
+ <name>WDT</name>
+ <address>0xb0002000</address>
+ </instance>
+ <node>
+ <name>DATA</name>
+ <instance>
+ <name>DATA</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>ENABLE</name>
+ <title>Watchdog counter enable register</title>
+ <instance>
+ <name>ENABLE</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>TCEN</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>COUNT</name>
+ <instance>
+ <name>COUNT</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>CTRL</name>
+ <title>Watchdog control register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>PRESCALE</name>
+ <position>3</position>
+ <width>3</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>64</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>256</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>1024</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>CLKIN</name>
+ <position>0</position>
+ <width>3</width>
+ <enum>
+ <name>PCK</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>RTC</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>EXT</name>
+ <value>0x4</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>RTC</name>
+ <title>Real time clock module(RTC) address definition</title>
+ <instance>
+ <name>RTC</name>
+ <address>0xb0003000</address>
+ </instance>
+ <node>
+ <name>RTCCR</name>
+ <title>RTC control register</title>
+ <instance>
+ <name>RTCCR</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>WRDY</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>1HZ</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>1HZIE</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>AF</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>AIE</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>AE</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>SELEXC</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>RTCE</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RTCSR</name>
+ <instance>
+ <name>RTCSR</name>
+ <address>0x4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>RTCSAR</name>
+ <instance>
+ <name>RTCSAR</name>
+ <address>0x8</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>RTCGR</name>
+ <title>RTC regulator register</title>
+ <instance>
+ <name>RTCGR</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>LOCK</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>ADJC</name>
+ <position>16</position>
+ <width>10</width>
+ </field>
+ <field>
+ <name>NC1HZ</name>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HCR</name>
+ <title>Hibernate control register</title>
+ <instance>
+ <name>HCR</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <field>
+ <name>PD</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HWFCR</name>
+ <title>Hibernate wakeup filter counter register</title>
+ <instance>
+ <name>HWFCR</name>
+ <address>0x24</address>
+ </instance>
+ <register>
+ <field>
+ <name>HWFCR</name>
+ <position>5</position>
+ <width>11</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HRCR</name>
+ <title>Hibernate reset counter register</title>
+ <instance>
+ <name>HRCR</name>
+ <address>0x28</address>
+ </instance>
+ <register>
+ <field>
+ <name>HRCR</name>
+ <position>5</position>
+ <width>7</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HWCR</name>
+ <title>Hibernate wakeup control register</title>
+ <instance>
+ <name>HWCR</name>
+ <address>0x2c</address>
+ </instance>
+ <register>
+ <field>
+ <name>EPDET</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>WKUPVL</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>EALM</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HWRSR</name>
+ <title>Hibernate wakeup status register</title>
+ <instance>
+ <name>HWRSR</name>
+ <address>0x30</address>
+ </instance>
+ <register>
+ <field>
+ <name>APD</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>HR</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>PPR</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>PIN</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ALM</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HSPR</name>
+ <title>Hibernate scratch pattern register</title>
+ <instance>
+ <name>HSPR</name>
+ <address>0x34</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>WENR</name>
+ <title>write enable pattern register</title>
+ <instance>
+ <name>WENR</name>
+ <address>0x3c</address>
+ </instance>
+ <register>
+ <field>
+ <name>WEN</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>WENPAT</name>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>GPIO</name>
+ <title>General purpose I/O port module(GPIO) address definition</title>
+ <instance>
+ <name>GPIO</name>
+ <address>0xb0010000</address>
+ </instance>
+ <node>
+ <name>IN</name>
+ <title>Port IN</title>
+ <instance>
+ <name>IN</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x00</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>OUT</name>
+ <title>Port OUT</title>
+ <instance>
+ <name>OUT</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x10</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>FLGC</name>
+ <instance>
+ <name>FLGC</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x14</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MASK</name>
+ <instance>
+ <name>MASK</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x20</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>PULL</name>
+ <instance>
+ <name>PULL</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x30</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>FUN</name>
+ <title>Function</title>
+ <instance>
+ <name>FUN</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x40</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>SEL</name>
+ <title>Select</title>
+ <instance>
+ <name>SEL</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x50</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>DIR</name>
+ <title>Direction</title>
+ <instance>
+ <name>DIR</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x60</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>TRG</name>
+ <title>Trigger</title>
+ <instance>
+ <name>TRG</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x70</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>FLG</name>
+ <title>Flag</title>
+ <instance>
+ <name>FLG</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0x80</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DRIVE0</name>
+ <title>Drive strength 0</title>
+ <instance>
+ <name>DRIVE0</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0xc0</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>DRIVE1</name>
+ <instance>
+ <name>DRIVE1</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0xd0</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>DRIVE2</name>
+ <instance>
+ <name>DRIVE2</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0xe0</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>SLEW</name>
+ <title>Slew rate control</title>
+ <instance>
+ <name>SLEW</name>
+ <range>
+ <first>0</first>
+ <count>6</count>
+ <formula variable="n">(n)*0x100 + 0xf0</formula>
+ </range>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>AIC</name>
+ <title>AC97 and I2S controller module</title>
+ <instance>
+ <name>AIC</name>
+ <address>0xb0020000</address>
+ </instance>
+ <node>
+ <name>FR</name>
+ <title>AIC controller configuration register</title>
+ <instance>
+ <name>FR</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>RFTH</name>
+ <position>24</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TFTH</name>
+ <position>16</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>LSMP</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>ICDC</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>AUSEL</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RST</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>BCKD</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>SYNCD</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ENB</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CR</name>
+ <title>AIC controller common control register</title>
+ <instance>
+ <name>CR</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>PACK16</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>CHANNEL</name>
+ <position>24</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>OSS</name>
+ <position>19</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>ISS</name>
+ <position>16</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>RDMS</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>TDMS</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>M2S</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>ENDSW</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>AVSTSU</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>TFLUSH</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>RFLUSH</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>EROR</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>ETUR</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>ERFS</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>ETFS</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>ENLBF</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>ERPL</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>EREC</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ACCR1</name>
+ <title>AIC controller AC-link control register 1</title>
+ <instance>
+ <name>ACCR1</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>RS</name>
+ <position>16</position>
+ <width>10</width>
+ </field>
+ <field>
+ <name>XS</name>
+ <position>0</position>
+ <width>10</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ACCR2</name>
+ <title>AIC controller AC-link control register 2</title>
+ <instance>
+ <name>ACCR2</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>ERSTO</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>ESADR</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>ECADT</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>SO</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>SR</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>SS</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>SA</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>I2SCR</name>
+ <title>AIC controller i2s/msb-justified control register</title>
+ <instance>
+ <name>I2SCR</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <field>
+ <name>RFIRST</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>SWLH</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>STPBK</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>ESCLK</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>AMSL</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SR</name>
+ <title>AIC controller FIFO status register</title>
+ <instance>
+ <name>SR</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <field>
+ <name>RFL</name>
+ <position>24</position>
+ <width>6</width>
+ </field>
+ <field>
+ <name>TFL</name>
+ <position>8</position>
+ <width>6</width>
+ </field>
+ <field>
+ <name>ROR</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>TUR</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>RFS</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>TFS</name>
+ <position>3</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ACSR</name>
+ <title>AIC controller AC-link status register</title>
+ <instance>
+ <name>ACSR</name>
+ <address>0x18</address>
+ </instance>
+ <register>
+ <field>
+ <name>SLTERR</name>
+ <position>21</position>
+ </field>
+ <field>
+ <name>CRDY</name>
+ <position>20</position>
+ </field>
+ <field>
+ <name>CLPM</name>
+ <position>19</position>
+ </field>
+ <field>
+ <name>RSTO</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>SADR</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>CADT</name>
+ <position>16</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>I2SSR</name>
+ <title>AIC controller I2S/MSB-justified status register</title>
+ <instance>
+ <name>I2SSR</name>
+ <address>0x1c</address>
+ </instance>
+ <register>
+ <field>
+ <name>CHBSY</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>TBSY</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RBSY</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>BSY</name>
+ <position>2</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ACCAR</name>
+ <title>AIC controller AC97 codec command address register</title>
+ <instance>
+ <name>ACCAR</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <field>
+ <name>CAR</name>
+ <position>0</position>
+ <width>20</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ACCDR</name>
+ <title>AIC controller AC97 codec command data register</title>
+ <instance>
+ <name>ACCDR</name>
+ <address>0x24</address>
+ </instance>
+ <register>
+ <field>
+ <name>CDR</name>
+ <position>0</position>
+ <width>20</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ACSAR</name>
+ <title>AIC controller AC97 codec status address register</title>
+ <instance>
+ <name>ACSAR</name>
+ <address>0x28</address>
+ </instance>
+ <register>
+ <field>
+ <name>SAR</name>
+ <position>0</position>
+ <width>20</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ACSDR</name>
+ <title>AIC controller AC97 codec status data register</title>
+ <instance>
+ <name>ACSDR</name>
+ <address>0x2c</address>
+ </instance>
+ <register>
+ <field>
+ <name>SDR</name>
+ <position>0</position>
+ <width>20</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>I2SDIV</name>
+ <title>AIC controller I2S/MSB-justified clock divider register</title>
+ <instance>
+ <name>I2SDIV</name>
+ <address>0x30</address>
+ </instance>
+ <register>
+ <field>
+ <name>DIV</name>
+ <position>0</position>
+ <width>4</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DR</name>
+ <instance>
+ <name>DR</name>
+ <address>0x34</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>SPENA</name>
+ <title>SPDIF enable register</title>
+ <instance>
+ <name>SPENA</name>
+ <address>0x80</address>
+ </instance>
+ <register>
+ <field>
+ <name>SPEN</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SPCTRL</name>
+ <title>SPDIF control register</title>
+ <instance>
+ <name>SPCTRL</name>
+ <address>0x84</address>
+ </instance>
+ <register>
+ <field>
+ <name>DMAEN</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>DTYPE</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>SIGN</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>INVALID</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>RST</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>SPDIFI2S</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>MTRIG</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>MFFUR</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SPSTATE</name>
+ <title>SPDIF state register</title>
+ <instance>
+ <name>SPSTATE</name>
+ <address>0x88</address>
+ </instance>
+ <register>
+ <field>
+ <name>FLVL</name>
+ <position>8</position>
+ <width>7</width>
+ </field>
+ <field>
+ <name>BUSY</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>FTRIG</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>FUR</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SPCFG1</name>
+ <title>SPDIF configure 1 register</title>
+ <instance>
+ <name>SPCFG1</name>
+ <address>0x8c</address>
+ </instance>
+ <register>
+ <field>
+ <name>INITLVL</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>ZROVLD</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>TRIG</name>
+ <position>12</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>SRCNUM</name>
+ <position>8</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>CH1NUM</name>
+ <position>4</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>CH2NUM</name>
+ <position>0</position>
+ <width>4</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SPCFG2</name>
+ <title>SPDIF configure 2 register</title>
+ <instance>
+ <name>SPCFG2</name>
+ <address>0x90</address>
+ </instance>
+ <register>
+ <field>
+ <name>FS</name>
+ <position>26</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>ORGFRQ</name>
+ <position>22</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>SAMWL</name>
+ <position>19</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>MAXWL</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>CLKACU</name>
+ <position>16</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>CATCODE</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>CHMD</name>
+ <position>6</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>PRE</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>COPYN</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>AUDION</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>CONPRO</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SPFIFO</name>
+ <instance>
+ <name>SPFIFO</name>
+ <address>0x94</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>RGADW</name>
+ <title>ICDC internal register access control register</title>
+ <instance>
+ <name>RGADW</name>
+ <address>0xa4</address>
+ </instance>
+ <register>
+ <field>
+ <name>RGWR</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>RGADDR</name>
+ <position>8</position>
+ <width>7</width>
+ </field>
+ <field>
+ <name>RGDIN</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RGDATA</name>
+ <title>ICDC internal register data output register</title>
+ <instance>
+ <name>RGDATA</name>
+ <address>0xa8</address>
+ </instance>
+ <register>
+ <field>
+ <name>IRQ</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>RGDOUT</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>MSC</name>
+ <instance>
+ <name>MSC</name>
+ <range>
+ <first>0</first>
+ <address>0xb0021000</address>
+ <address>0xb0022000</address>
+ <address>0xb0023000</address>
+ </range>
+ </instance>
+ <node>
+ <name>STRPCL</name>
+ <title>MSC Clock and Control Register</title>
+ <instance>
+ <name>STRPCL</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>SEND_CCSD</name>
+ <desc>send command completion signal disable to ceata</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>SEND_AS_CCSD</name>
+ <desc>send internally generated stop after sending ccsd</desc>
+ <position>14</position>
+ </field>
+ <field>
+ <name>EXIT_MULTIPLE</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>EXIT_TRANSFER</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>START_READWAIT</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>STOP_READWAIT</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RESET</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>START_OP</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>CLOCK_CONTROL</name>
+ <desc>Start MMC/SD clock</desc>
+ <position>0</position>
+ <width>2</width>
+ <enum>
+ <name>STOP</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>START</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>STAT</name>
+ <title>MSC Status Register</title>
+ <instance>
+ <name>STAT</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>AUTO_CMD_DONE</name>
+ <desc>12 is internally generated by controller has finished</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>IS_RESETTING</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>SDIO_INT_ACTIVE</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>PRG_DONE</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>DATA_TRAN_DONE</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>END_CMD_RES</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>DATA_FIFO_AFULL</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>IS_READWAIT</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>CLK_EN</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>DATA_FIFO_FULL</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>DATA_FIFO_EMPTY</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>CRC_RES_ERR</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>CRC_READ_ERROR</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>CRC_WRITE_ERROR</name>
+ <desc>No CRC status is sent back</desc>
+ <position>2</position>
+ <width>2</width>
+ <enum>
+ <name>NO</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>DATA</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>NOSTS</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>TIME_OUT_RES</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>TIME_OUT_READ</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CLKRT</name>
+ <title>MSC Bus Clock Control Register</title>
+ <instance>
+ <name>CLKRT</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>CLK_RATE</name>
+ <desc>1/128 of CLK_SRC</desc>
+ <position>0</position>
+ <width>3</width>
+ <enum>
+ <name>DIV_1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>DIV_2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>DIV_4</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>DIV_8</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>DIV_16</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>DIV_32</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>DIV_64</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>DIV_128</name>
+ <value>0x7</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CMDAT</name>
+ <title>MSC Command Sequence Control Register</title>
+ <instance>
+ <name>CMDAT</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>CCS_EXPECTED</name>
+ <desc>interrupts are enabled in ce-ata</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>READ_CEATA</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>SDIO_PRDT</name>
+ <desc>exact 2 cycle</desc>
+ <position>17</position>
+ </field>
+ <field>
+ <name>SEND_AS_STOP</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>RTRG</name>
+ <desc>reset value</desc>
+ <position>14</position>
+ <width>2</width>
+ <enum>
+ <name>EQUALT_8</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>EQUALT_16</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>EQUALT_24</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>TTRG</name>
+ <desc>reset value</desc>
+ <position>12</position>
+ <width>2</width>
+ <enum>
+ <name>LESS_8</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>LESS_16</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>LESS_24</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>STOP_ABORT</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>BUS_WIDTH</name>
+ <desc>8-bit data bus</desc>
+ <position>9</position>
+ <width>2</width>
+ <enum>
+ <name>1BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4BIT</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>8BIT</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>DMA_EN</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>INIT</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>BUSY</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>STREAM_BLOCK</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>WRITE</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DATA_EN</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>RESPONSE</name>
+ <desc>Format R6</desc>
+ <position>0</position>
+ <width>3</width>
+ <enum>
+ <name>NONE</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>R1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>R2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>R3</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>R4</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>R5</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>R6</name>
+ <value>0x6</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RESTO</name>
+ <instance>
+ <name>RESTO</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>RDTO</name>
+ <instance>
+ <name>RDTO</name>
+ <address>0x14</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>BLKLEN</name>
+ <instance>
+ <name>BLKLEN</name>
+ <address>0x18</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>NOB</name>
+ <instance>
+ <name>NOB</name>
+ <address>0x1c</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>SNOB</name>
+ <instance>
+ <name>SNOB</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>IMASK</name>
+ <title>MSC Interrupts Mask Register</title>
+ <instance>
+ <name>IMASK</name>
+ <address>0x24</address>
+ </instance>
+ <register>
+ <field>
+ <name>AUTO_CMD_DONE</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>DATA_FIFO_FULL</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>DATA_FIFO_EMP</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>CRC_RES_ERR</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>CRC_READ_ERR</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>CRC_WRITE_ERR</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>TIMEOUT_RES</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>TIMEOUT_READ</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>SDIO</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>TXFIFO_WR_REQ</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>RXFIFO_RD_REQ</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>END_CMD_RES</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>PRG_DONE</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DATA_TRAN_DONE</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>IREG</name>
+ <title>MSC Interrupts Status Register</title>
+ <instance>
+ <name>IREG</name>
+ <address>0x28</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>AUTO_CMD_DONE</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>DATA_FIFO_FULL</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>DATA_FIFO_EMP</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>CRC_RES_ERR</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>CRC_READ_ERR</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>CRC_WRITE_ERR</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>TIMEOUT_RES</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>TIMEOUT_READ</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>SDIO</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>TXFIFO_WR_REQ</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>RXFIFO_RD_REQ</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>END_CMD_RES</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>PRG_DONE</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DATA_TRAN_DONE</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CMD</name>
+ <instance>
+ <name>CMD</name>
+ <address>0x2c</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>ARG</name>
+ <instance>
+ <name>ARG</name>
+ <address>0x30</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>RES</name>
+ <instance>
+ <name>RES</name>
+ <address>0x34</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>RXFIFO</name>
+ <instance>
+ <name>RXFIFO</name>
+ <address>0x38</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>TXFIFO</name>
+ <instance>
+ <name>TXFIFO</name>
+ <address>0x3c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>LPM</name>
+ <title>MSC Low Power Mode Register</title>
+ <instance>
+ <name>LPM</name>
+ <address>0x40</address>
+ </instance>
+ <register>
+ <field>
+ <name>LPM</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>UART</name>
+ <instance>
+ <name>UART</name>
+ <range>
+ <first>0</first>
+ <address>0xb0030000</address>
+ <address>0xb0031000</address>
+ <address>0xb0032000</address>
+ <address>0xb0033000</address>
+ </range>
+ </instance>
+ <node>
+ <name>DLLR</name>
+ <instance>
+ <name>DLLR</name>
+ <address>0x0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>RDR</name>
+ <instance>
+ <name>RDR</name>
+ <address>0x0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>TDR</name>
+ <instance>
+ <name>TDR</name>
+ <address>0x0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DLHR</name>
+ <instance>
+ <name>DLHR</name>
+ <address>0x4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>IER</name>
+ <instance>
+ <name>IER</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>RTIE</name>
+ <desc>0: receive timeout interrupt disable</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>MIE</name>
+ <desc>0: modem status interrupt disable</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>RLIE</name>
+ <desc>0: receive line status interrupt disable</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>TIE</name>
+ <desc>0: transmit fifo empty interrupt disable</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>RIE</name>
+ <desc>0: receive fifo full interrupt disable</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>FCR</name>
+ <instance>
+ <name>FCR</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>RTRG_4</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>UUE</name>
+ <desc>0: disable UART</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DMS</name>
+ <desc>0: disable DMA mode</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>TFLS</name>
+ <desc>write 1 to flush transmit FIFO</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RFLS</name>
+ <desc>write 1 to flush receive FIFO</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>FE</name>
+ <desc>0: non-FIFO mode 1: FIFO mode</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ISR</name>
+ <instance>
+ <name>ISR</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>IID_THRI</name>
+ <desc>Transmitter holding register empty</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>IP</name>
+ <desc>0: interrupt is pending 1: no interrupt</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>LCR</name>
+ <instance>
+ <name>LCR</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>DLAB</name>
+ <desc>0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>SBRK</name>
+ <desc>write 0 normal, write 1 send break</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>SPAR</name>
+ <desc>0: sticky parity disable</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>PROE</name>
+ <desc>0: even parity 1: odd parity</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>PE</name>
+ <desc>0: parity disable</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>STOP2</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>WLEN_6</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>MCR</name>
+ <instance>
+ <name>MCR</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <field>
+ <name>MCE</name>
+ <desc>0: modem function is disable</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>FCM</name>
+ <desc>0: software 1: hardware</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>LOOP</name>
+ <desc>0: normal 1: loopback mode</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RTS</name>
+ <desc>0: RTS_ output high, 1: RTS_ output low</desc>
+ <position>1</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>LSR</name>
+ <instance>
+ <name>LSR</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <field>
+ <name>RFER</name>
+ <desc>0: no receive error 1: receive error in FIFO mode</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>TEMT</name>
+ <desc>1: transmit FIFO and shift registers empty</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>TDRQ</name>
+ <desc>1: transmit FIFO half 'empty'</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>BRK</name>
+ <desc>0: no break detected 1: receive a break signal</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>FER</name>
+ <desc>0; no framing error</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>PER</name>
+ <desc>0: no parity error</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>ORER</name>
+ <desc>0: no overrun error</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DR</name>
+ <desc>0: receive FIFO is empty 1: receive data is ready</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>MSR</name>
+ <instance>
+ <name>MSR</name>
+ <address>0x18</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>SPR</name>
+ <instance>
+ <name>SPR</name>
+ <address>0x1c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>SIRCR</name>
+ <instance>
+ <name>SIRCR</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <field>
+ <name>RDPL</name>
+ <desc>0: decoder interprets positive pulse as 0</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>TDPL</name>
+ <desc>0: encoder generates a positive pulse for 0</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>TPWS</name>
+ <desc>0: transmit 0 pulse width is 3/16 of bit length, 1: 0 pulse width is 1.6us for 115.2Kbps</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RSIRE</name>
+ <desc>0: receiver is in UART mode 1: SIR mode</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>TSIRE</name>
+ <desc>0: transmitter is in UART mode 1: SIR mode</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>UMR</name>
+ <instance>
+ <name>UMR</name>
+ <address>0x24</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>UACR</name>
+ <instance>
+ <name>UACR</name>
+ <address>0x28</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>SCC</name>
+ <instance>
+ <name>SCC</name>
+ <address>0xb0040000</address>
+ </instance>
+ <node>
+ <name>DR</name>
+ <instance>
+ <name>DR</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>FDR</name>
+ <title>SCC FIFO Data Count Register</title>
+ <instance>
+ <name>FDR</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CR</name>
+ <title>SCC Control Register</title>
+ <instance>
+ <name>CR</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>SCCE</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>TRS</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>T2R</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>FDIV</name>
+ <desc>SCC_CLK frequency is half of device clock</desc>
+ <position>24</position>
+ <width>2</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ <field>
+ <name>FLUSH</name>
+ <position>23</position>
+ </field>
+ <field>
+ <name>TRIG</name>
+ <desc>Receive/Transmit-FIFO Trigger is 14</desc>
+ <position>16</position>
+ <width>2</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>14</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>TP</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>CONV</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>TXIE</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>RXIE</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>TENDIE</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>RTOIE</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>ECIE</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>EPIE</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>RETIE</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>EOIE</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>TSEND</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>PX</name>
+ <desc>SCC_CLK stops at state high</desc>
+ <position>1</position>
+ <width>2</width>
+ <enum>
+ <name>NOT_SUPPORT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>STOP_LOW</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>STOP_HIGH</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>CLKSTP</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SR</name>
+ <title>SCC Status Register</title>
+ <instance>
+ <name>SR</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>TRANS</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>ORER</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>RTO</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>PER</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>TFTG</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>RFTG</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>TEND</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>RETR_3</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>ECNTO</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>TFR</name>
+ <instance>
+ <name>TFR</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>EGTR</name>
+ <instance>
+ <name>EGTR</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>ECR</name>
+ <instance>
+ <name>ECR</name>
+ <address>0x18</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>RTOR</name>
+ <instance>
+ <name>RTOR</name>
+ <address>0x1c</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>SSI</name>
+ <title>SSI (Synchronous Serial Interface)</title>
+ <instance>
+ <name>SSI</name>
+ <range>
+ <first>0</first>
+ <address>0xb0043000</address>
+ <address>0xb0044000</address>
+ <address>0xb0045000</address>
+ </range>
+ </instance>
+ <node>
+ <name>DR</name>
+ <title>SSI Data Register</title>
+ <instance>
+ <name>DR</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>GPC</name>
+ <position>0</position>
+ <width>9</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CR0</name>
+ <title>SSI Control Register 0</title>
+ <instance>
+ <name>CR0</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>SSIE</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>TIE</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>RIE</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>REIE</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>LOOP</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>RFINE</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>RFINC</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>EACLRUN</name>
+ <desc>hardware auto clear underrun when TxFifo no empty</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>FSEL</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>TFLUSH</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RFLUSH</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DISREV</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CR1</name>
+ <title>SSI Control Register 1</title>
+ <instance>
+ <name>CR1</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>FRMHL</name>
+ <desc>SSI_CE_ is high valid and SSI_CE2_ is high valid</desc>
+ <position>30</position>
+ <width>2</width>
+ <enum>
+ <name>CELOW_CE2LOW</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>CEHIGH_CE2LOW</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>CELOW_CE2HIGH</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>CEHIGH_CE2HIGH</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>TFVCK</name>
+ <position>28</position>
+ <width>2</width>
+ <enum>
+ <name>0</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>TCKFI</name>
+ <position>26</position>
+ <width>2</width>
+ <enum>
+ <name>0</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>LFST</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>ITFRM</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>UNFIN</name>
+ <position>23</position>
+ </field>
+ <field>
+ <name>MULTS</name>
+ <position>22</position>
+ </field>
+ <field>
+ <name>FMAT</name>
+ <desc>National Microwire 2 format</desc>
+ <position>20</position>
+ <width>2</width>
+ <enum>
+ <name>SPI</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>SSP</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>MW1</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>MW2</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>TTRG</name>
+ <desc>SSI1 TX trigger</desc>
+ <position>16</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>MCOM</name>
+ <desc>16-bit command selected</desc>
+ <position>12</position>
+ <width>4</width>
+ <enum>
+ <name>1BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2BIT</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>3BIT</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>4BIT</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>5BIT</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>6BIT</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>7BIT</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>8BIT</name>
+ <value>0x7</value>
+ </enum>
+ <enum>
+ <name>9BIT</name>
+ <value>0x8</value>
+ </enum>
+ <enum>
+ <name>10BIT</name>
+ <value>0x9</value>
+ </enum>
+ <enum>
+ <name>11BIT</name>
+ <value>0xa</value>
+ </enum>
+ <enum>
+ <name>12BIT</name>
+ <value>0xb</value>
+ </enum>
+ <enum>
+ <name>13BIT</name>
+ <value>0xc</value>
+ </enum>
+ <enum>
+ <name>14BIT</name>
+ <value>0xd</value>
+ </enum>
+ <enum>
+ <name>15BIT</name>
+ <value>0xe</value>
+ </enum>
+ <enum>
+ <name>16BIT</name>
+ <value>0xf</value>
+ </enum>
+ </field>
+ <field>
+ <name>RTRG</name>
+ <desc>SSI RX trigger</desc>
+ <position>8</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>FLEN</name>
+ <position>4</position>
+ <width>4</width>
+ <enum>
+ <name>2BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>3BIT</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>4BIT</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>5BIT</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>6BIT</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>7BIT</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>8BIT</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>9BIT</name>
+ <value>0x7</value>
+ </enum>
+ <enum>
+ <name>10BIT</name>
+ <value>0x8</value>
+ </enum>
+ <enum>
+ <name>11BIT</name>
+ <value>0x9</value>
+ </enum>
+ <enum>
+ <name>12BIT</name>
+ <value>0xa</value>
+ </enum>
+ <enum>
+ <name>13BIT</name>
+ <value>0xb</value>
+ </enum>
+ <enum>
+ <name>14BIT</name>
+ <value>0xc</value>
+ </enum>
+ <enum>
+ <name>15BIT</name>
+ <value>0xd</value>
+ </enum>
+ <enum>
+ <name>16BIT</name>
+ <value>0xe</value>
+ </enum>
+ <enum>
+ <name>17BIT</name>
+ <value>0xf</value>
+ </enum>
+ </field>
+ <field>
+ <name>PHA</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>POL</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SR</name>
+ <title>SSI Status Register</title>
+ <instance>
+ <name>SR</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>TFIFONUM</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>RFIFONUM</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>END</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>BUSY</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>TFF</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>RFE</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>TFHE</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>RFHF</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>UNDR</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>OVER</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ITR</name>
+ <title>SSI Interval Time Control Register</title>
+ <instance>
+ <name>ITR</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>CNTCLK</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>IVLTM</name>
+ <position>0</position>
+ <width>15</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ICR</name>
+ <instance>
+ <name>ICR</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>GR</name>
+ <instance>
+ <name>GR</name>
+ <address>0x18</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>I2C</name>
+ <title>I2C</title>
+ <instance>
+ <name>I2C</name>
+ <range>
+ <first>0</first>
+ <address>0xb0050000</address>
+ <address>0xb0051000</address>
+ <address>0xb0055000</address>
+ </range>
+ </instance>
+ <node>
+ <name>CTRL</name>
+ <title>I2C Control Register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>STPHLD</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>SLVDIS</name>
+ <desc>after reset slave is disabled</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>REST</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>MATP</name>
+ <desc>1: 10bit address 0: 7bit addressing</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>SATP</name>
+ <desc>standard mode 100kbps</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>SPD</name>
+ <desc>standard mode 100kbps</desc>
+ <position>1</position>
+ <width>2</width>
+ <enum>
+ <name>SPDS</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>SPDF</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>MD</name>
+ <desc>master enabled</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>TAR</name>
+ <title>I2C target address</title>
+ <instance>
+ <name>TAR</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>MATP</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>SPECIAL</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>GC_OR_START</name>
+ <position>10</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SAR</name>
+ <instance>
+ <name>SAR</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>DC</name>
+ <title>I2C data buffer and command</title>
+ <instance>
+ <name>DC</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>CMD</name>
+ <desc>1 read 0 write</desc>
+ <position>8</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SHCNT</name>
+ <title>I2C standard mode high count register</title>
+ <instance>
+ <name>SHCNT</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>SLCNT</name>
+ <title>I2C standard mode low count register</title>
+ <instance>
+ <name>SLCNT</name>
+ <address>0x18</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>FHCNT</name>
+ <title>I2C fast mode high count register</title>
+ <instance>
+ <name>FHCNT</name>
+ <address>0x1c</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>FLCNT</name>
+ <title>I2C fast mode low count register</title>
+ <instance>
+ <name>FLCNT</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>INTST</name>
+ <title>i2c interrupt status</title>
+ <instance>
+ <name>INTST</name>
+ <address>0x2c</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>IGC</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>ISTT</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>ISTP</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>IACT</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>RXDN</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>TXABT</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>RDREQ</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>TXEMP</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>TXOF</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>RXFL</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RXOF</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>RXUF</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>INTM</name>
+ <title>i2c interrupt mask status</title>
+ <instance>
+ <name>INTM</name>
+ <address>0x30</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>MIGC</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>MISTT</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>MISTP</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>MIACT</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>MRXDN</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>MTXABT</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>MRDREQ</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>MTXEMP</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>MTXOF</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>MRXFL</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>MRXOF</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>MRXUF</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RXTL</name>
+ <instance>
+ <name>RXTL</name>
+ <address>0x38</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>TXTL</name>
+ <instance>
+ <name>TXTL</name>
+ <address>0x3c</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CINTR</name>
+ <title>I2C Clear Combined and Individual Interrupts</title>
+ <instance>
+ <name>CINTR</name>
+ <address>0x40</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CRXUF</name>
+ <instance>
+ <name>CRXUF</name>
+ <address>0x44</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CRXOF</name>
+ <instance>
+ <name>CRXOF</name>
+ <address>0x48</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CTXOF</name>
+ <instance>
+ <name>CTXOF</name>
+ <address>0x4c</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CRXREQ</name>
+ <instance>
+ <name>CRXREQ</name>
+ <address>0x50</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CTXABRT</name>
+ <instance>
+ <name>CTXABRT</name>
+ <address>0x54</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CRXDONE</name>
+ <instance>
+ <name>CRXDONE</name>
+ <address>0x58</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CACT</name>
+ <instance>
+ <name>CACT</name>
+ <address>0x5c</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CSTP</name>
+ <instance>
+ <name>CSTP</name>
+ <address>0x60</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>CSTT</name>
+ <instance>
+ <name>CSTT</name>
+ <address>0x64</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>CGC</name>
+ <instance>
+ <name>CGC</name>
+ <address>0x68</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>ENB</name>
+ <title>I2C Enable</title>
+ <instance>
+ <name>ENB</name>
+ <address>0x6c</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>I2CENB</name>
+ <desc>Enable the i2c</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>STA</name>
+ <title>I2C Status Register</title>
+ <instance>
+ <name>STA</name>
+ <address>0x70</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>SLVACT</name>
+ <desc>Slave FSM is not in IDLE state</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>MSTACT</name>
+ <desc>Master FSM is not in IDLE state</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>RFF</name>
+ <desc>RFIFO if full</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RFNE</name>
+ <desc>RFIFO is not empty</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>TFE</name>
+ <desc>TFIFO is empty</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>TFNF</name>
+ <desc>TFIFO is not full</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ACT</name>
+ <desc>I2C Activity Status</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>TXFLR</name>
+ <instance>
+ <name>TXFLR</name>
+ <address>0x74</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>RXFLR</name>
+ <instance>
+ <name>RXFLR</name>
+ <address>0x78</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>TXABRT</name>
+ <title>I2C Transmit Abort Status Register</title>
+ <instance>
+ <name>TXABRT</name>
+ <address>0x80</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>SLVRD_INTX</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>SLV_ARBLOST</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>SLVFLUSH_TXFIFO</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>ARB_LOST</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>ABRT_MASTER_DIS</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>ABRT_10B_RD_NORSTRT</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>SBYTE_NORSTRT</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>ABRT_HS_NORSTRT</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>SBYTE_ACKDET</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>ABRT_HS_ACKD</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>ABRT_GCALL_READ</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>ABRT_GCALL_NOACK</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>ABRT_XDATA_NOACK</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>ABRT_10ADDR2_NOACK</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>ABRT_10ADDR1_NOACK</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ABRT_7B_ADDR_NOACK</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DMACR</name>
+ <instance>
+ <name>DMACR</name>
+ <address>0x88</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>DMATDLR</name>
+ <instance>
+ <name>DMATDLR</name>
+ <address>0x8c</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>DMARDLR</name>
+ <instance>
+ <name>DMARDLR</name>
+ <address>0x90</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>SDASU</name>
+ <instance>
+ <name>SDASU</name>
+ <address>0x94</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>ACKGC</name>
+ <instance>
+ <name>ACKGC</name>
+ <address>0x98</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>ENSTA</name>
+ <title>I2C Enable Status Register</title>
+ <instance>
+ <name>ENSTA</name>
+ <address>0x9c</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>SLVRDLST</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>SLVDISB</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>I2CEN</name>
+ <desc>when read as 1, i2c is deemed to be in an enabled state, when read as 0, i2c is deemed completely inactive. The cpu can, safely read this bit anytime .When this bit is read as 0 ,the cpu can, safely read SLVRDLST and SLVDISB</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SDAHD</name>
+ <instance>
+ <name>SDAHD</name>
+ <address>0xd0</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>HOLD_TIME_EN</name>
+ <position>8</position>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>PS2</name>
+ <title>APB BUS Devices Base</title>
+ <instance>
+ <name>PS2</name>
+ <address>0xb0060000</address>
+ </instance>
+ </node>
+ <node>
+ <name>SADC</name>
+ <title>SAR A/D Controller</title>
+ <instance>
+ <name>SADC</name>
+ <address>0xb0070000</address>
+ </instance>
+ <node>
+ <name>ADENA</name>
+ <title>ADC Enable Register</title>
+ <instance>
+ <name>ADENA</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>POWER</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>SLP_MD</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>TCHEN</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>VBATEN</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>AUXEN</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADCFG</name>
+ <title>ADC Configure Register</title>
+ <instance>
+ <name>ADCFG</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>SPZZ</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>DMA_EN</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>XYZ</name>
+ <position>13</position>
+ <width>2</width>
+ <enum>
+ <name>XYS</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>XYD</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>XYZ1Z2</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>SNUM</name>
+ <position>10</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>CMD</name>
+ <position>0</position>
+ <width>2</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADCTRL</name>
+ <title>ADC Control Register</title>
+ <instance>
+ <name>ADCTRL</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>SLPENDM</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>PENDM</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>PENUM</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>DTCHM</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>VRDYM</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ARDYM</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADSTATE</name>
+ <title>ADC Status Register</title>
+ <instance>
+ <name>ADSTATE</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>SLP_RDY</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>SLPEND</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>PEND</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>PENU</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>DTCH</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>VRDY</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ARDY</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADSAME</name>
+ <title>ADC Same Point Time Register</title>
+ <instance>
+ <name>ADSAME</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>SCNT</name>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADWAIT</name>
+ <title>ADC Wait Pen Down Time Register</title>
+ <instance>
+ <name>ADWAIT</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>WCNT</name>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADTCH</name>
+ <title>ADC Touch Screen Data Register</title>
+ <instance>
+ <name>ADTCH</name>
+ <address>0x18</address>
+ </instance>
+ <register>
+ <field>
+ <name>TYPE1</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>DATA1</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>TYPE0</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>DATA0</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADVDAT</name>
+ <title>ADC VBAT Date Register</title>
+ <instance>
+ <name>ADVDAT</name>
+ <address>0x1c</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>VDATA</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADADAT</name>
+ <title>ADC AUX Data Register</title>
+ <instance>
+ <name>ADADAT</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>ADATA</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADFLT</name>
+ <title>ADC Filter Register</title>
+ <instance>
+ <name>ADFLT</name>
+ <address>0x24</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>FLT_EN</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>FLT_D</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADCLK</name>
+ <title>ADC Clock Divide Register</title>
+ <instance>
+ <name>ADCLK</name>
+ <address>0x28</address>
+ </instance>
+ <register>
+ <field>
+ <name>CLKDIV_MS</name>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>CLKDIV_US</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>PCM</name>
+ <title>Pulse-code modulation module(PCM) address definition</title>
+ <instance>
+ <name>PCM</name>
+ <range>
+ <first>0</first>
+ <address>0xb0071000</address>
+ <address>0xb0074000</address>
+ </range>
+ </instance>
+ <node>
+ <name>PCTL</name>
+ <title>PCM controller control register</title>
+ <instance>
+ <name>PCTL</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>ERDMA</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>ETDMA</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>LSMP</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>ERPL</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>EREC</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>FLUSH</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RST</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>CLKEN</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>PCMEN</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PCFG</name>
+ <title>PCM controller configure register</title>
+ <instance>
+ <name>PCFG</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>SLOT</name>
+ <position>13</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>ISS_16BIT</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>OSS_16BIT</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>IMSBPOS</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>OMSBPOS</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>RFTH</name>
+ <position>5</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TFTH</name>
+ <position>1</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>MODE_SLAVE</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PDP</name>
+ <instance>
+ <name>PDP</name>
+ <address>0x8</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PINTC</name>
+ <title>PCM controller interrupt control register</title>
+ <instance>
+ <name>PINTC</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>ETFS</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>ETUR</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>ERFS</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>EROR</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PINTS</name>
+ <title>PCM controller interrupt status register</title>
+ <instance>
+ <name>PINTS</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <field>
+ <name>RSTS</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>TFL</name>
+ <position>9</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>TFS</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>TUR</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>RFL</name>
+ <position>2</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>RFS</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ROR</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PDIV</name>
+ <title>PCM controller clock division register</title>
+ <instance>
+ <name>PDIV</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <field>
+ <name>SYNL</name>
+ <position>11</position>
+ <width>6</width>
+ </field>
+ <field>
+ <name>SYNDIV</name>
+ <position>6</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <position>0</position>
+ <width>6</width>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>OWI</name>
+ <instance>
+ <name>OWI</name>
+ <address>0xb0072000</address>
+ </instance>
+ <node>
+ <name>OWICFG</name>
+ <title>OWI configure register</title>
+ <instance>
+ <name>OWICFG</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>MODE</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>RDDATA</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>WRDATA</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>RDST</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>WR1RD</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>WR0</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RST</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ENA</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OWICTL</name>
+ <title>OWI control register</title>
+ <instance>
+ <name>OWICTL</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>EBYTE</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>EBIT</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ERST</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OWISTS</name>
+ <title>OWI status register</title>
+ <instance>
+ <name>OWISTS</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>PST</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>BYTE_RDY</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>BIT_RDY</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>PST_RDY</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OWIDAT</name>
+ <instance>
+ <name>OWIDAT</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>OWIDIV</name>
+ <title>OWI clock divide register</title>
+ <instance>
+ <name>OWIDIV</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>CLKDIV</name>
+ <position>0</position>
+ <width>6</width>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>TSSI</name>
+ <title>TSSI MPEG 2-TS slave interface</title>
+ <instance>
+ <name>TSSI</name>
+ <address>0xb0073000</address>
+ </instance>
+ <node>
+ <name>ENA</name>
+ <title>TSSI enable register</title>
+ <instance>
+ <name>ENA</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>SFT_RST</name>
+ <desc>soft reset bit</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>FAIL</name>
+ <desc>fail signal bit</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>PEN_0</name>
+ <desc>PID filter enable bit for PID</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>PID_EN</name>
+ <desc>soft filtering function enable bit</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DMA_EN</name>
+ <desc>DMA enable bit</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ENA</name>
+ <desc>TSSI enable bit</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CFG</name>
+ <title>TSSI configure register</title>
+ <instance>
+ <name>CFG</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>TRIG</name>
+ <desc>fifo trig number</desc>
+ <position>14</position>
+ <width>2</width>
+ <enum>
+ <name>4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>TRANS_MD</name>
+ <position>10</position>
+ <width>2</width>
+ <enum>
+ <name>0</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>END_WD</name>
+ <desc>order of data in word</desc>
+ <position>9</position>
+ </field>
+ <field>
+ <name>END_BT</name>
+ <desc>order of data in byte</desc>
+ <position>8</position>
+ </field>
+ <field>
+ <name>TSDI_H</name>
+ <desc>data pin polarity</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>USE_0</name>
+ <desc>serial mode data pin select: 0 for TSDI7, 1 for TSDI0</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>TSCLK_CH</name>
+ <desc>clk channel select</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>PARAL</name>
+ <desc>mode select</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>TSCLK_P</name>
+ <desc>clk edge select</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>TSFRM_H</name>
+ <desc>TSFRM polarity select</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>TSSTR_H</name>
+ <desc>TSSTR polarity select</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>TSFAIL_H</name>
+ <desc>TSFAIL polarity select</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CTRL</name>
+ <title>TSSI control register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>DTRM</name>
+ <desc>FIFO data trigger interrupt mask bit</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>OVRNM</name>
+ <desc>FIFO overrun interrupt mask bit</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>TRIGM</name>
+ <desc>FIFO trigger interrupt mask bit</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>STAT</name>
+ <title>TSSI state register</title>
+ <instance>
+ <name>STAT</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>DTR</name>
+ <desc>FIFO data trigger interrupt flag bit</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>OVRN</name>
+ <desc>FIFO overrun interrupt flag bit</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>TRIG</name>
+ <desc>FIFO trigger interrupt flag bit</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>FIFO</name>
+ <title>TSSI FIFO register</title>
+ <instance>
+ <name>FIFO</name>
+ <address>0x10</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PEN</name>
+ <title>TSSI PID enable register</title>
+ <instance>
+ <name>PEN</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <field>
+ <name>EN151</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>EN141</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>EN131</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>EN121</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>EN111</name>
+ <position>27</position>
+ </field>
+ <field>
+ <name>EN101</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>EN91</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>EN81</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>EN71</name>
+ <position>23</position>
+ </field>
+ <field>
+ <name>EN61</name>
+ <position>22</position>
+ </field>
+ <field>
+ <name>EN51</name>
+ <position>21</position>
+ </field>
+ <field>
+ <name>EN41</name>
+ <position>20</position>
+ </field>
+ <field>
+ <name>EN31</name>
+ <position>19</position>
+ </field>
+ <field>
+ <name>EN21</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>EN11</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>EN01</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>EN150</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>EN140</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>EN130</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>EN120</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>EN110</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>EN100</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>EN90</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>EN80</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>EN70</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>EN60</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>EN50</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>EN40</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>EN30</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>EN20</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>EN10</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>EN00</name>
+ <desc>enable PID n</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>NUM</name>
+ <instance>
+ <name>NUM</name>
+ <address>0x18</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DTR</name>
+ <instance>
+ <name>DTR</name>
+ <address>0x1c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PID</name>
+ <title>TSSI PID filter register</title>
+ <instance>
+ <name>PID</name>
+ <range>
+ <first>0</first>
+ <count>16</count>
+ <formula variable="n">0x20 + 4*(n)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>PID1</name>
+ <position>16</position>
+ <width>13</width>
+ </field>
+ <field>
+ <name>PID0</name>
+ <position>0</position>
+ <width>13</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DDA</name>
+ <instance>
+ <name>DDA</name>
+ <address>0x60</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DTA</name>
+ <instance>
+ <name>DTA</name>
+ <address>0x64</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DID</name>
+ <instance>
+ <name>DID</name>
+ <address>0x68</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DCMD</name>
+ <instance>
+ <name>DCMD</name>
+ <address>0x6c</address>
+ </instance>
+ <register>
+ <field>
+ <name>TLEN</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>TEFE</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>TSZ</name>
+ <position>2</position>
+ <width>2</width>
+ <enum>
+ <name>4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>LINK</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DST</name>
+ <instance>
+ <name>DST</name>
+ <address>0x70</address>
+ </instance>
+ <register>
+ <field>
+ <name>DID</name>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>TEND</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>TC</name>
+ <instance>
+ <name>TC</name>
+ <address>0x74</address>
+ </instance>
+ <register>
+ <field>
+ <name>OP</name>
+ <position>4</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>OPE</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>EME</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>APM</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>HARB0</name>
+ <title>AHB0 BUS Devices Base</title>
+ <instance>
+ <name>HARB0</name>
+ <address>0xb3000000</address>
+ </instance>
+ </node>
+ <node>
+ <name>EMC</name>
+ <title>EMC (External Memory Controller)</title>
+ <instance>
+ <name>EMC</name>
+ <address>0xb3010000</address>
+ </instance>
+ <node>
+ <name>BCR</name>
+ <title>Bus Control Register</title>
+ <instance>
+ <name>BCR</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>BT_SEL</name>
+ <position>30</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>PK_SEL</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>BSR</name>
+ <desc>Nand and SDRAM Bus Share Select: 0, share; 1, unshare</desc>
+ <position>2</position>
+ <enum>
+ <name>SHARE</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>UNSHARE</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ <field>
+ <name>BRE</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ENDIAN</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SMCR</name>
+ <title>Static Memory Control Register</title>
+ <instance>
+ <name>SMCR</name>
+ <range>
+ <first>0</first>
+ <count>7</count>
+ <formula variable="n">0x10 + (n)*4</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>STRV</name>
+ <position>24</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TAW</name>
+ <position>20</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TBP</name>
+ <position>16</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TAH</name>
+ <position>12</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>TAS</name>
+ <position>8</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>BW</name>
+ <position>6</position>
+ <width>2</width>
+ <enum>
+ <name>8BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>16BIT</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>32BIT</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>BCM</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>BL</name>
+ <position>1</position>
+ <width>2</width>
+ <enum>
+ <name>4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>SMT</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SACR</name>
+ <title>Static Memory Bank Addr Config Reg</title>
+ <instance>
+ <name>SACR</name>
+ <range>
+ <first>0</first>
+ <count>5</count>
+ <formula variable="n">0x30 + (n)*4</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>BASE</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>MASK</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>NFCSR</name>
+ <title>NAND Flash Control/Status Register</title>
+ <instance>
+ <name>NFCSR</name>
+ <address>0x50</address>
+ </instance>
+ <register>
+ <field>
+ <name>NFCE4</name>
+ <desc>NAND Flash Enable</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>NFE4</name>
+ <desc>NAND Flash FCE# Assertion Enable</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>NFCE3</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>NFE3</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>NFCE2</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>NFE2</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>NFCE1</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>NFE1</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DMCR</name>
+ <title>DRAM Control Register</title>
+ <instance>
+ <name>DMCR</name>
+ <address>0x80</address>
+ </instance>
+ <register>
+ <field>
+ <name>BW</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>CA</name>
+ <position>26</position>
+ <width>3</width>
+ <enum>
+ <name>8</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>9</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>10</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>11</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>12</name>
+ <value>0x4</value>
+ </enum>
+ </field>
+ <field>
+ <name>RMODE</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>RFSH</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>MRSET</name>
+ <position>23</position>
+ </field>
+ <field>
+ <name>RA</name>
+ <position>20</position>
+ <width>2</width>
+ <enum>
+ <name>11</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>12</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>13</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>BA</name>
+ <position>19</position>
+ </field>
+ <field>
+ <name>PDM</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>EPIN</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>MBSEL</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>TRAS</name>
+ <position>13</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>RCD</name>
+ <position>11</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>TPC</name>
+ <position>8</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>TRWL</name>
+ <position>5</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>TRC</name>
+ <position>2</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>TCL</name>
+ <position>0</position>
+ <width>2</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RTCSR</name>
+ <title>Refresh Time Control/Status Register</title>
+ <instance>
+ <name>RTCSR</name>
+ <address>0x84</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>SFR</name>
+ <desc>self refresh flag</desc>
+ <position>8</position>
+ </field>
+ <field>
+ <name>CMF</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>CKS</name>
+ <position>0</position>
+ <width>3</width>
+ <enum>
+ <name>DISABLE</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>64</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>256</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>1024</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>2048</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>4096</name>
+ <value>0x7</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RTCNT</name>
+ <title>Refresh Timer Counter</title>
+ <instance>
+ <name>RTCNT</name>
+ <address>0x88</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>RTCOR</name>
+ <title>Refresh Time Constant Register</title>
+ <instance>
+ <name>RTCOR</name>
+ <address>0x8c</address>
+ </instance>
+ <register>
+ <width>16</width>
+ </register>
+ </node>
+ <node>
+ <name>DMAR</name>
+ <title>SDRAM Bank Address Configuration Register</title>
+ <instance>
+ <name>DMAR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">0x90 + (n)*4</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>BASE</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>MASK</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PMEMBS1</name>
+ <instance>
+ <name>PMEMBS1</name>
+ <address>0x6004</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PMEMBS0</name>
+ <instance>
+ <name>PMEMBS0</name>
+ <address>0x6008</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>SDMR</name>
+ <title>Mode Register of SDRAM bank</title>
+ <instance>
+ <name>SDMR</name>
+ <address>0xa000</address>
+ </instance>
+ <register>
+ <field>
+ <name>BM</name>
+ <desc>Write Burst Mode</desc>
+ <position>9</position>
+ </field>
+ <field>
+ <name>OM</name>
+ <desc>Operating Mode</desc>
+ <position>7</position>
+ <width>2</width>
+ <enum>
+ <name>NORMAL</name>
+ <value>0x0</value>
+ </enum>
+ </field>
+ <field>
+ <name>CAS</name>
+ <desc>CAS Latency</desc>
+ <position>4</position>
+ <width>3</width>
+ <enum>
+ <name>1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>BT</name>
+ <desc>Interleave</desc>
+ <position>3</position>
+ <enum>
+ <name>SEQ</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>INT</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ <field>
+ <name>BL</name>
+ <desc>Burst Length</desc>
+ <position>0</position>
+ <width>3</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>OTP</name>
+ <title>OTP (One Time Programmable Module) [not sure about the address]</title>
+ <instance>
+ <name>OTP</name>
+ <address>0xb3012000</address>
+ </instance>
+ <node>
+ <name>ID0</name>
+ <title>ID0 Register</title>
+ <instance>
+ <name>ID0</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>WID</name>
+ <desc>Wafer ID</desc>
+ <position>24</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>MID</name>
+ <desc>MASK ID</desc>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>FID</name>
+ <desc>Foundary ID</desc>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PID</name>
+ <desc>Product ID</desc>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ID1</name>
+ <title>ID1 Register</title>
+ <instance>
+ <name>ID1</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>LID</name>
+ <desc>Lot ID</desc>
+ <position>8</position>
+ <width>24</width>
+ </field>
+ <field>
+ <name>TID</name>
+ <desc>Test House ID</desc>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ID2</name>
+ <title>ID2 Register</title>
+ <instance>
+ <name>ID2</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>XADR</name>
+ <desc>Die X-dir Address</desc>
+ <position>24</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>YADR</name>
+ <desc>Die Y-dir Address</desc>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>TDATE</name>
+ <desc>Testing Date</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ID3</name>
+ <title>ID3 Register</title>
+ <instance>
+ <name>ID3</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>CID</name>
+ <desc>Customer ID</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>CP</name>
+ <desc>Chip Parameters</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>BR0</name>
+ <title>BOOTROM0 Register</title>
+ <instance>
+ <name>BR0</name>
+ <address>0x10</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>BR1</name>
+ <title>BOOTROM1 Register</title>
+ <instance>
+ <name>BR1</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <field>
+ <name>UDCBOOT</name>
+ <desc>27MHz OSC</desc>
+ <position>0</position>
+ <width>8</width>
+ <enum>
+ <name>27M</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>26M</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>13M</name>
+ <value>0xc</value>
+ </enum>
+ <enum>
+ <name>24M</name>
+ <value>0xf</value>
+ </enum>
+ <enum>
+ <name>AUTO</name>
+ <value>0xf0</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HW0</name>
+ <title>Chip Hardware 0 Register</title>
+ <instance>
+ <name>HW0</name>
+ <address>0x18</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>HW1</name>
+ <title>Chip Hardware 1 Register</title>
+ <instance>
+ <name>HW1</name>
+ <address>0x1c</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>DDRC</name>
+ <instance>
+ <name>DDRC</name>
+ <address>0xb3020000</address>
+ </instance>
+ <node>
+ <name>STATUS</name>
+ <title>DDR Status Register</title>
+ <instance>
+ <name>STATUS</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>ENDIAN</name>
+ <desc>0 Little data endian, 1 Big data endian</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>MISS</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>DPDN</name>
+ <desc>0 DDR memory is NOT in deep-power-down state, 1 DDR memory is in deep-power-down state</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>PDN</name>
+ <desc>0 DDR memory is NOT in power-down state, 1 DDR memory is in power-down state</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>AREF</name>
+ <desc>0 DDR memory is NOT in auto-refresh state, 1 DDR memory is in auto-refresh state</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>SREF</name>
+ <desc>0 DDR memory is NOT in self-refresh state, 1 DDR memory is in self-refresh state</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>CKE1</name>
+ <desc>0 CKE1 Pin is low, 1 CKE1 Pin is high</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>CKE0</name>
+ <desc>0 CKE0 Pin is low, 1 CKE0 Pin is high</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CFG</name>
+ <title>DDR Configure Register</title>
+ <instance>
+ <name>CFG</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>ROW1</name>
+ <desc>Row Address width.</desc>
+ <position>27</position>
+ <width>2</width>
+ <enum>
+ <name>12</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>13</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>14</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>COL1</name>
+ <desc>Row Address width.</desc>
+ <position>25</position>
+ <width>2</width>
+ <enum>
+ <name>8</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>9</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>10</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>11</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>BA1_BIT</name>
+ <desc>bank width</desc>
+ <position>24</position>
+ <enum>
+ <name>4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ <field>
+ <name>IMBA</name>
+ <position>23</position>
+ </field>
+ <field>
+ <name>BTRUN</name>
+ <position>21</position>
+ </field>
+ <field>
+ <name>MPRT</name>
+ <desc>Miss CS protect: 0 will lock the bus on fault, 1 will return random data</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>TYPE</name>
+ <position>12</position>
+ <width>3</width>
+ <enum>
+ <name>DDR1</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>MDDR</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>DDR2</name>
+ <value>0x4</value>
+ </enum>
+ </field>
+ <field>
+ <name>ROW0</name>
+ <desc>Row Address width.</desc>
+ <position>10</position>
+ <width>2</width>
+ <enum>
+ <name>12</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>13</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>14</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>COL0</name>
+ <desc>Row Address width.</desc>
+ <position>8</position>
+ <width>2</width>
+ <enum>
+ <name>8</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>9</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>10</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>11</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>CS1EN</name>
+ <desc>0 DDR Pin CS1 un-used, 1 There're DDR memory connected to CS1</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>CS0EN</name>
+ <desc>0 DDR Pin CS0 un-used, 1 There're DDR memory connected to CS0</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>CL</name>
+ <desc>CAS latency</desc>
+ <position>2</position>
+ <width>4</width>
+ <enum>
+ <name>3</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>5</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>6</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>BA0</name>
+ <desc>bank width</desc>
+ <position>1</position>
+ <enum>
+ <name>4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ <field>
+ <name>DW</name>
+ <desc>External memory data width</desc>
+ <position>0</position>
+ <enum>
+ <name>16</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CTRL</name>
+ <title>DDR Control Register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>ACTPD</name>
+ <desc>0 Precharge all banks before entering power-down, 1 Do not precharge banks before entering power-down</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>PDT</name>
+ <desc>Enter power-down after 128 tCK idle</desc>
+ <position>12</position>
+ <width>3</width>
+ <enum>
+ <name>DIS</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>64</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>128</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>PRET</name>
+ <desc>Precharge active bank after 128 tCK idle</desc>
+ <position>8</position>
+ <width>3</width>
+ <enum>
+ <name>DIS</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>64</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>128</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>SR</name>
+ <desc>1 Drive external DDR device entering self-refresh mode, 0 Drive external DDR device exiting self-refresh mode</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>UNALIGN</name>
+ <desc>0 Disable unaligned transfer on AXI BUS, 1 Enable unaligned transfer on AXI BUS</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>ALH</name>
+ <desc>Advanced Latency Hiding: 0 Disable ALH, 1 Enable ALH</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>RDC</name>
+ <desc>0 dclk clock frequency is lower than 60MHz, 1 dclk clock frequency is higher than 60MHz</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>CKE</name>
+ <desc>0 Not set CKE Pin High, 1 Set CKE Pin HIGH</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>RESET</name>
+ <desc>0 End resetting ddrc_controller, 1 Resetting ddrc_controller</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>LMR</name>
+ <title>DDR Load-Mode-Register</title>
+ <instance>
+ <name>LMR</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>DDR_ADDR</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>BA</name>
+ <desc>(For mobile DDR) Status Register set</desc>
+ <position>8</position>
+ <width>3</width>
+ <enum>
+ <name>MRS</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>M_MRS</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>EMRS1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>M_SR</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>EMRS2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>M_EMRS</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>EMRS3</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>CMD</name>
+ <desc>Load Mode Register</desc>
+ <position>4</position>
+ <width>2</width>
+ <enum>
+ <name>PREC</name>
+ <desc>Precharge one/all bank</desc>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>AUREF</name>
+ <desc>Auto-refresh</desc>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>LMR</name>
+ <desc>Load-Mode reister</desc>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>START</name>
+ <desc>0 No command is performed, 1 On the posedge of START, perform a command defined by CMD field</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>TIMING1</name>
+ <title>DDR Timing Config Register 1</title>
+ <instance>
+ <name>TIMING1</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <field>
+ <name>TRAS</name>
+ <desc>ACTIVE to PRECHARGE command period (2 * tRAS + 1)</desc>
+ <position>28</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TRTP</name>
+ <desc>READ to PRECHARGE command period.</desc>
+ <position>24</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>TRP</name>
+ <desc>PRECHARGE command period.</desc>
+ <position>20</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>TRCD</name>
+ <desc>ACTIVE to READ or WRITE command period.</desc>
+ <position>16</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>TRC</name>
+ <desc>ACTIVE to ACTIVE command period.</desc>
+ <position>12</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TRRD</name>
+ <desc>ACTIVE bank A to ACTIVE bank B command period.</desc>
+ <position>8</position>
+ <width>2</width>
+ <enum>
+ <name>DISABLE</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>TWR</name>
+ <desc>WRITE Recovery Time defined by register MR of DDR2 memory</desc>
+ <position>4</position>
+ <width>3</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>5</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>6</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>TWTR</name>
+ <desc>WRITE to READ command delay.</desc>
+ <position>0</position>
+ <width>2</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>TIMING2</name>
+ <title>DDR Timing Config Register 2</title>
+ <instance>
+ <name>TIMING2</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <field>
+ <name>TRFC</name>
+ <desc>AUTO-REFRESH command period.</desc>
+ <position>24</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>RWCOV</name>
+ <desc>Equal to Tsel of MDELAY.</desc>
+ <position>19</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>TMINSR</name>
+ <desc>Minimum Self-Refresh / Deep-Power-Down time</desc>
+ <position>8</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TXP</name>
+ <desc>EXIT-POWER-DOWN to next valid command period.</desc>
+ <position>4</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>TMRD</name>
+ <desc>Load-Mode-Register to next valid command period.</desc>
+ <position>0</position>
+ <width>2</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>REFCNT</name>
+ <title>DDR Auto-Refresh Counter</title>
+ <instance>
+ <name>REFCNT</name>
+ <address>0x18</address>
+ </instance>
+ <register>
+ <field>
+ <name>CON</name>
+ <desc>Constant value used to compare with CNT value.</desc>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>CNT</name>
+ <desc>8-bit counter</desc>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <desc>Clock Divider for auto-refresh counter.</desc>
+ <position>1</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>REF_EN</name>
+ <desc>Enable Refresh Counter</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DQS</name>
+ <title>DDR DQS Delay Control Register</title>
+ <instance>
+ <name>DQS</name>
+ <address>0x1c</address>
+ </instance>
+ <register>
+ <field>
+ <name>ERROR</name>
+ <desc>ahb_clk Delay Detect ERROR, read-only.</desc>
+ <position>29</position>
+ </field>
+ <field>
+ <name>READY</name>
+ <desc>ahb_clk Delay Detect READY, read-only.</desc>
+ <position>28</position>
+ </field>
+ <field>
+ <name>SRDET</name>
+ <desc>Hardware auto-redetect &amp; set delay line</desc>
+ <position>25</position>
+ </field>
+ <field>
+ <name>DET</name>
+ <desc>Start delay detecting.</desc>
+ <position>24</position>
+ </field>
+ <field>
+ <name>AUTO</name>
+ <desc>Hardware auto-detect &amp; set delay line</desc>
+ <position>23</position>
+ </field>
+ <field>
+ <name>CLKD</name>
+ <desc>CLKD is reference value for setting WDQS and RDQS.</desc>
+ <position>16</position>
+ <width>7</width>
+ </field>
+ <field>
+ <name>WDQS</name>
+ <desc>Set delay element number to write DQS delay-line.</desc>
+ <position>8</position>
+ <width>6</width>
+ </field>
+ <field>
+ <name>RDQS</name>
+ <desc>Set delay element number to read DQS delay-line.</desc>
+ <position>0</position>
+ <width>6</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DQSADJ</name>
+ <title>DDR DQS Delay Adjust Register</title>
+ <instance>
+ <name>DQSADJ</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <field>
+ <name>WSIGN</name>
+ <desc>The sign of WDQS value for WRITE DQS delay</desc>
+ <position>13</position>
+ </field>
+ <field>
+ <name>WDQS</name>
+ <desc>The adjust value for WRITE DQS delay</desc>
+ <position>8</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>RSIGN</name>
+ <desc>The sign of RDQS value for READ DQS delay </desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>RDQS</name>
+ <desc>The adjust value for READ DQS delay</desc>
+ <position>0</position>
+ <width>5</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>MMAP</name>
+ <title>DDR Memory Map Config Register</title>
+ <instance>
+ <name>MMAP</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">0x24 + 4*(n)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>BASE</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>MASK</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DELAYCTRL</name>
+ <instance>
+ <name>DELAYCTRL</name>
+ <address>0x2c</address>
+ </instance>
+ <register>
+ <field>
+ <name>TSEL</name>
+ <desc>Ready delay select: adds betweee 0 and 3tCK</desc>
+ <position>18</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>MSEL</name>
+ <desc>Mask delay select: adds betweee 0 and 3tCK</desc>
+ <position>16</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>HL</name>
+ <desc>Half-clock delay: 1 adds 1/2tCK</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>QUAR</name>
+ <desc> Quarter clock delay select: 1 adds 1/4tCK</desc>
+ <position>14</position>
+ </field>
+ <field>
+ <name>MAUTO</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>MSIGN</name>
+ <desc>Mask sign</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>MASK_DELAY_SEL_ADJ</name>
+ <position>0</position>
+ <width>5</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DELAYCTRL2</name>
+ <instance>
+ <name>DELAYCTRL2</name>
+ <address>0x30</address>
+ </instance>
+ <register>
+ <field>
+ <name>MASK_DELAY_SEL</name>
+ <position>0</position>
+ <width>5</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PADCTRL0</name>
+ <title>Pad control 0</title>
+ <instance>
+ <name>PADCTRL0</name>
+ <address>0x50</address>
+ </instance>
+ <register>
+ <field>
+ <name>PDDQS</name>
+ <position>28</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>PDDQ</name>
+ <position>24</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>SCHMITT_TRIGGER_DQS</name>
+ <position>20</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>SCHMITT_TRIGGER_DQ</name>
+ <position>16</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>ENPULL_DQS</name>
+ <position>12</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>ENPULL_DQ</name>
+ <position>8</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>PULLUP_DQS</name>
+ <position>4</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>PULLUP_DQ</name>
+ <position>0</position>
+ <width>4</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PADCTRL1</name>
+ <title>Pad Control 1</title>
+ <instance>
+ <name>PADCTRL1</name>
+ <address>0x54</address>
+ </instance>
+ <register>
+ <field>
+ <name>INEDQS</name>
+ <position>28</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>INEDQ</name>
+ <position>24</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>SSTL_MODE</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>STRENGTH_DQS</name>
+ <position>8</position>
+ <width>8</width>
+ <enum>
+ <name>HALF_DDR1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>HALF_MDDR</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>HALF_SDRAM_12MA</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>HALF_DDR2</name>
+ <value>0x55</value>
+ </enum>
+ <enum>
+ <name>HALF_SDRAM_16MA</name>
+ <value>0x55</value>
+ </enum>
+ <enum>
+ <name>FULL_DDR1</name>
+ <value>0xaa</value>
+ </enum>
+ <enum>
+ <name>FULL_SDRAM_24MA</name>
+ <value>0xaa</value>
+ </enum>
+ <enum>
+ <name>FULL_DDR2</name>
+ <value>0xff</value>
+ </enum>
+ <enum>
+ <name>FULL_MDDR</name>
+ <value>0xff</value>
+ </enum>
+ <enum>
+ <name>FULL_SDRAM_30MA</name>
+ <value>0xff</value>
+ </enum>
+ </field>
+ <field>
+ <name>STRENGTH_DQ</name>
+ <position>0</position>
+ <width>8</width>
+ <enum>
+ <name>HALF_DDR1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>HALF_MDDR</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>HALF_SDRAM_12MA</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>HALF_DDR2</name>
+ <value>0x55</value>
+ </enum>
+ <enum>
+ <name>HALF_SDRAM_16MA</name>
+ <value>0x55</value>
+ </enum>
+ <enum>
+ <name>FULL_DDR1</name>
+ <value>0xaa</value>
+ </enum>
+ <enum>
+ <name>FULL_SDRAM_24MA</name>
+ <value>0xaa</value>
+ </enum>
+ <enum>
+ <name>FULL_DDR2</name>
+ <value>0xff</value>
+ </enum>
+ <enum>
+ <name>FULL_MDDR</name>
+ <value>0xff</value>
+ </enum>
+ <enum>
+ <name>FULL_SDRAM_30MA</name>
+ <value>0xff</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PADCTRL2</name>
+ <title>Pad Control 2</title>
+ <instance>
+ <name>PADCTRL2</name>
+ <address>0x58</address>
+ </instance>
+ <register>
+ <field>
+ <name>STRENGTH_CKO</name>
+ <position>18</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>STRENGTH_CKE</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>STRENGTH_ADDR</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>STRENGTH_DM3</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>STRENGTH_DM2</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>STRENGTH_DM1</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>STRENGTH_DM0</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>STRENGTH_CMD</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>STRENGTH_CS1</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>STRENGTH_CS0</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PADCTRL3</name>
+ <title>Pad Control 3</title>
+ <instance>
+ <name>PADCTRL3</name>
+ <address>0x5c</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>MDMAC</name>
+ <title>Memory Copy DMAC</title>
+ <instance>
+ <name>MDMAC</name>
+ <address>0xb3030000</address>
+ </instance>
+ <node>
+ <name>CH_SOURCE</name>
+ <title>DMA source address</title>
+ <instance>
+ <name>CH_SOURCE</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">(0x00 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CH_TARGET</name>
+ <title>DMA target address</title>
+ <instance>
+ <name>CH_TARGET</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">(0x04 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CH_COUNT</name>
+ <title>DMA transfer count</title>
+ <desc> </desc>
+ <instance>
+ <name>CH_COUNT</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">(0x08 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CH_REQUEST</name>
+ <title>DMA request source</title>
+ <instance>
+ <name>CH_REQUEST</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">(0x0c + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CH_CTRL</name>
+ <title>DMA control/status</title>
+ <instance>
+ <name>CH_CTRL</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">(0x10 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CH_CMD</name>
+ <title>DMA command</title>
+ <instance>
+ <name>CH_CMD</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">(0x14 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CH_DESC</name>
+ <title>DMA descriptor address</title>
+ <instance>
+ <name>CH_DESC</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">(0x18 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CH_STRIDE</name>
+ <title>DMA Stride Address</title>
+ <instance>
+ <name>CH_STRIDE</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="n">(0xc0 + (n) * 0x04)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CTRL</name>
+ <title>DMA control register</title>
+ <instance>
+ <name>DMACR</name>
+ <address>0x300</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>IRQ</name>
+ <title>DMA interrupt pending</title>
+ <instance>
+ <name>IRQ</name>
+ <address>0x304</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DOORBELL</name>
+ <title>DMA doorbell</title>
+ <instance>
+ <name>DOORBELL</name>
+ <address>0x308</address>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>CLOCK</name>
+ <instance>
+ <name>CLOCK</name>
+ <address>0x310</address>
+ </instance>
+ <register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>0</offset>
+ </variant>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>EPD</name>
+ <title>EPD</title>
+ <instance>
+ <name>EPD</name>
+ <address>0xb3050000</address>
+ </instance>
+ <node>
+ <name>CTRL</name>
+ <instance>
+ <name>CTRL</name>
+ <address>0x200</address>
+ </instance>
+ <register>
+ <field>
+ <name>PPL7_FRM_INTM</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>PPL6_FRM_INTM</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>PPL5_FRM_INTM</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>PPL4_FRM_INTM</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>PPL3_FRM_INTM</name>
+ <position>27</position>
+ </field>
+ <field>
+ <name>PPL2_FRM_INTM</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>PPL1_FRM_INTM</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>PPL0_FRM_INTM</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>FRM_VCOM_INTM</name>
+ <position>22</position>
+ </field>
+ <field>
+ <name>IMG_DONE_INTM</name>
+ <position>21</position>
+ </field>
+ <field>
+ <name>FRM_DONE_INTM</name>
+ <position>20</position>
+ </field>
+ <field>
+ <name>FRM_ABT_INTM</name>
+ <position>19</position>
+ </field>
+ <field>
+ <name>PWR_OFF_INTM</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>PWR_ON_INTM</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>DMA_DONE_INTM</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>PPL7_FRM_ENA</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>PPL6_FRM_ENA</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>PPL5_FRM_ENA</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>PPL4_FRM_ENA</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>PPL3_FRM_ENA</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>PPL2_FRM_ENA</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>PPL1_FRM_ENA</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>PPL0_FRM_ENA</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>IMG_REF_ABT</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>IMG_REF_ENA</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>PWROFF</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>PWRON</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>EPD_DMA_MODE</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>EPD_ENA</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>STA</name>
+ <instance>
+ <name>STA</name>
+ <address>0x204</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>ISR</name>
+ <instance>
+ <name>ISR</name>
+ <address>0x208</address>
+ </instance>
+ <register>
+ <field>
+ <name>PPL7_FRM_INT</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>PPL6_FRM_INT</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>PPL5_FRM_INT</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>PPL4_FRM_INT</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>PPL3_FRM_INT</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>PPL2_FRM_INT</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>PPL1_FRM_INT</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>PPL0_FRM_INT</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>FRM_VCOM_INT</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>IMG_DONE_INT</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>FRM_DONE_INT</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>FRM_ABT_INT</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>PWR_OFF_INT</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>PWR_ON_INT</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DMA_DONE_INT</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CFG0</name>
+ <instance>
+ <name>CFG0</name>
+ <address>0x20c</address>
+ </instance>
+ <register>
+ <field>
+ <name>DUAL_GATE</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>COLOR_MODE</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>COLOR_FORMAT</name>
+ <position>27</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>SDSP_CAS</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>SDSP_MODE</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>GDCLK_MODE</name>
+ <position>24</position>
+ </field>
+ <field>
+ <name>GDOE_MODE</name>
+ <position>22</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>GDUD</name>
+ <position>21</position>
+ </field>
+ <field>
+ <name>SDRL</name>
+ <position>20</position>
+ </field>
+ <field>
+ <name>GDCLK_POL</name>
+ <position>19</position>
+ </field>
+ <field>
+ <name>GDOE_POL</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>GDSP_POL</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>SDCLK_POL</name>
+ <position>16</position>
+ </field>
+ <field>
+ <name>SDOE_POL</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>SDSP_POL</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>SDCE_POL</name>
+ <position>13</position>
+ </field>
+ <field>
+ <name>SDLE_POL</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>GDSP_CAS</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>COMP_MODE</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>EPD_OBPP</name>
+ <position>1</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>EPD_OMODE</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CFG1</name>
+ <instance>
+ <name>CFG1</name>
+ <address>0x210</address>
+ </instance>
+ <register>
+ <field>
+ <name>SDDO_REV</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>PDAT_SWAP</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>SDCE_REV</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>SDOS</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PADDING_DAT</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>SDCE_STN</name>
+ <position>4</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>SDCE_NUM</name>
+ <position>0</position>
+ <width>4</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PPL0</name>
+ <instance>
+ <name>PPL0</name>
+ <address>0x214</address>
+ </instance>
+ <register>
+ <field>
+ <name>PPL3_FRM_NUM</name>
+ <position>24</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PPL2_FRM_NUM</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PPL1_FRM_NUM</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PPL0_FRM_NUM</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PPL1</name>
+ <instance>
+ <name>PPL1</name>
+ <address>0x218</address>
+ </instance>
+ <register>
+ <field>
+ <name>PPL7_FRM_NUM</name>
+ <position>24</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PPL6_FRM_NUM</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PPL5_FRM_NUM</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PPL4_FRM_NUM</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>VAT</name>
+ <instance>
+ <name>VAT</name>
+ <address>0x21c</address>
+ </instance>
+ <register>
+ <field>
+ <name>VT</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>HT</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DAV</name>
+ <instance>
+ <name>DAV</name>
+ <address>0x220</address>
+ </instance>
+ <register>
+ <field>
+ <name>VDE</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>VDS</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DAH</name>
+ <instance>
+ <name>DAH</name>
+ <address>0x224</address>
+ </instance>
+ <register>
+ <field>
+ <name>HDE</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>HDS</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>VSYNC</name>
+ <instance>
+ <name>VSYNC</name>
+ <address>0x228</address>
+ </instance>
+ <register>
+ <field>
+ <name>VPE</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>VPS</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HSYNC</name>
+ <instance>
+ <name>HSYNC</name>
+ <address>0x22c</address>
+ </instance>
+ <register>
+ <field>
+ <name>HPE</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>HPS</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>GDCLK</name>
+ <instance>
+ <name>GDCLK</name>
+ <address>0x230</address>
+ </instance>
+ <register>
+ <field>
+ <name>DIS</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>ENA</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>GDOE</name>
+ <instance>
+ <name>GDOE</name>
+ <address>0x234</address>
+ </instance>
+ <register>
+ <field>
+ <name>DIS</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>ENA</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>GDSP</name>
+ <instance>
+ <name>GDSP</name>
+ <address>0x238</address>
+ </instance>
+ <register>
+ <field>
+ <name>DIS</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>ENA</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SDOE</name>
+ <instance>
+ <name>SDOE</name>
+ <address>0x23c</address>
+ </instance>
+ <register>
+ <field>
+ <name>DIS</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>ENA</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SDSP</name>
+ <instance>
+ <name>SDSP</name>
+ <address>0x240</address>
+ </instance>
+ <register>
+ <field>
+ <name>DIS</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>ENA</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PMGR0</name>
+ <instance>
+ <name>PMGR0</name>
+ <address>0x244</address>
+ </instance>
+ <register>
+ <field>
+ <name>PWR_DLY12</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>PWR_DLY01</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PMGR1</name>
+ <instance>
+ <name>PMGR1</name>
+ <address>0x248</address>
+ </instance>
+ <register>
+ <field>
+ <name>PWR_DLY34</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>PWR_DLY23</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PMGR2</name>
+ <instance>
+ <name>PMGR2</name>
+ <address>0x24c</address>
+ </instance>
+ <register>
+ <field>
+ <name>PWR_DLY56</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>PWR_DLY45</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PMGR3</name>
+ <instance>
+ <name>PMGR3</name>
+ <address>0x250</address>
+ </instance>
+ <register>
+ <field>
+ <name>VCOM_IDLE</name>
+ <position>30</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>PWRCOM_POL</name>
+ <position>29</position>
+ </field>
+ <field>
+ <name>UNI_POL</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>PPL7_BDR_ENA</name>
+ <position>27</position>
+ </field>
+ <field>
+ <name>BDR_LEVEL</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>BDR_VALUE</name>
+ <position>24</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>PWR_POL</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PWR_DLY67</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PMGR4</name>
+ <instance>
+ <name>PMGR4</name>
+ <address>0x254</address>
+ </instance>
+ <register>
+ <field>
+ <name>PWR_VAL</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>PWR_ENA</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>VCOM0</name>
+ <instance>
+ <name>VCOM0</name>
+ <address>0x258</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>VCOM1</name>
+ <instance>
+ <name>VCOM1</name>
+ <address>0x25c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>VCOM2</name>
+ <instance>
+ <name>VCOM2</name>
+ <address>0x260</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>VCOM3</name>
+ <instance>
+ <name>VCOM3</name>
+ <address>0x264</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>VCOM4</name>
+ <instance>
+ <name>VCOM4</name>
+ <address>0x268</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>VCOM5</name>
+ <instance>
+ <name>VCOM5</name>
+ <address>0x26c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>BORDR</name>
+ <instance>
+ <name>BORDR</name>
+ <address>0x270</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PPL_POS</name>
+ <instance>
+ <name>PPL_POS</name>
+ <range>
+ <first>0</first>
+ <address>0x280</address>
+ <address>0x288</address>
+ <address>0x290</address>
+ <address>0x298</address>
+ <address>0x2a0</address>
+ <address>0x2a8</address>
+ <address>0x2b0</address>
+ <address>0x2b8</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>PPL_YPOS</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>PPL_XPOS</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PPL_SIZE</name>
+ <instance>
+ <name>PPL_SIZE</name>
+ <range>
+ <first>1</first>
+ <address>0x28c</address>
+ <address>0x294</address>
+ <address>0x29c</address>
+ <address>0x2a4</address>
+ <address>0x2ac</address>
+ <address>0x2b4</address>
+ <address>0x2bc</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>PPL_HEIGHT</name>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>PPL_WIDTH</name>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>LCD</name>
+ <title>LCD (LCD Controller)</title>
+ <instance>
+ <name>LCD</name>
+ <address>0xb3050000</address>
+ </instance>
+ <node>
+ <name>CFG</name>
+ <title>LCD Configure Register</title>
+ <instance>
+ <name>CFG</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>LCDPIN</name>
+ <desc>LCD pins selection</desc>
+ <position>31</position>
+ <enum>
+ <name>LCD</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>SLCD</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ <field>
+ <name>TVEPEH</name>
+ <desc>TVE PAL enable extra halfline signal</desc>
+ <position>30</position>
+ </field>
+ <field>
+ <name>FUHOLD</name>
+ <desc>hold pixel clock when outFIFO underrun</desc>
+ <position>29</position>
+ </field>
+ <field>
+ <name>NEWDES</name>
+ <desc>use new descripter. old: 4words, new:8words</desc>
+ <position>28</position>
+ </field>
+ <field>
+ <name>PALBP</name>
+ <desc>bypass data format and alpha blending</desc>
+ <position>27</position>
+ </field>
+ <field>
+ <name>TVEN</name>
+ <desc>indicate the terminal is lcd or tv</desc>
+ <position>26</position>
+ </field>
+ <field>
+ <name>RECOVER</name>
+ <desc>Auto recover when output fifo underrun</desc>
+ <position>25</position>
+ </field>
+ <field>
+ <name>DITHER</name>
+ <desc>Dither function</desc>
+ <position>24</position>
+ </field>
+ <field>
+ <name>PSM</name>
+ <desc>PS signal mode</desc>
+ <position>23</position>
+ </field>
+ <field>
+ <name>CLSM</name>
+ <desc>CLS signal mode</desc>
+ <position>22</position>
+ </field>
+ <field>
+ <name>SPLM</name>
+ <desc>SPL signal mode</desc>
+ <position>21</position>
+ </field>
+ <field>
+ <name>REVM</name>
+ <desc>REV signal mode</desc>
+ <position>20</position>
+ </field>
+ <field>
+ <name>HSYNM</name>
+ <desc>HSYNC signal mode</desc>
+ <position>19</position>
+ </field>
+ <field>
+ <name>PCLKM</name>
+ <desc>PCLK signal mode</desc>
+ <position>18</position>
+ </field>
+ <field>
+ <name>INVDAT</name>
+ <desc>Inverse output data</desc>
+ <position>17</position>
+ </field>
+ <field>
+ <name>SYNDIR_IN</name>
+ <desc>VSYNC&amp;HSYNC direction</desc>
+ <position>16</position>
+ </field>
+ <field>
+ <name>PSP</name>
+ <desc>PS pin reset state</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>CLSP</name>
+ <desc>CLS pin reset state</desc>
+ <position>14</position>
+ </field>
+ <field>
+ <name>SPLP</name>
+ <desc>SPL pin reset state</desc>
+ <position>13</position>
+ </field>
+ <field>
+ <name>REVP</name>
+ <desc>REV pin reset state</desc>
+ <position>12</position>
+ </field>
+ <field>
+ <name>HSP</name>
+ <desc>HSYNC polarity:0-active high,1-active low</desc>
+ <position>11</position>
+ </field>
+ <field>
+ <name>PCP</name>
+ <desc>PCLK polarity:0-rising,1-falling</desc>
+ <position>10</position>
+ </field>
+ <field>
+ <name>DEP</name>
+ <desc>DE polarity:0-active high,1-active low</desc>
+ <position>9</position>
+ </field>
+ <field>
+ <name>VSP</name>
+ <desc>VSYNC polarity:0-rising,1-falling</desc>
+ <position>8</position>
+ </field>
+ <field>
+ <name>MODE_TFT_18BIT</name>
+ <desc>18bit TFT</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>MODE_TFT_24BIT</name>
+ <desc>24bit TFT</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>PDW</name>
+ <desc>LCD_D[0:7]/LCD_D[8:15]</desc>
+ <position>4</position>
+ <width>2</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>MODE</name>
+ <desc>16,18 bit TFT</desc>
+ <position>0</position>
+ <width>4</width>
+ <enum>
+ <name>GENERIC_TFT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>SPECIAL_TFT_1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>SPECIAL_TFT_2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>SPECIAL_TFT_3</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>NONINTER_CCIR656</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>INTER_CCIR656</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>SINGLE_CSTN</name>
+ <value>0x8</value>
+ </enum>
+ <enum>
+ <name>SINGLE_MSTN</name>
+ <value>0x9</value>
+ </enum>
+ <enum>
+ <name>DUAL_CSTN</name>
+ <value>0xa</value>
+ </enum>
+ <enum>
+ <name>DUAL_MSTN</name>
+ <value>0xb</value>
+ </enum>
+ <enum>
+ <name>SERIAL_TFT</name>
+ <value>0xc</value>
+ </enum>
+ <enum>
+ <name>LCM</name>
+ <value>0xd</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>VSYNC</name>
+ <title>Vertical Synchronize Register</title>
+ <instance>
+ <name>VSYNC</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>VPS</name>
+ <desc>VSYNC pulse start in line clock, fixed to 0</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>VPE</name>
+ <desc>VSYNC pulse end in line clock</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>HSYNC</name>
+ <title>Horizontal Synchronize Register</title>
+ <instance>
+ <name>HSYNC</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>HPS</name>
+ <desc>HSYNC pulse start position in dot clock</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>HPE</name>
+ <desc>HSYNC pulse end position in dot clock</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>VAT</name>
+ <title>Virtual Area Setting Register</title>
+ <instance>
+ <name>VAT</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>HT</name>
+ <desc>Horizontal Total size in dot clock</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>VT</name>
+ <desc>Vertical Total size in dot clock</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DAH</name>
+ <title>Display Area Horizontal Start/End Point</title>
+ <instance>
+ <name>DAH</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <field>
+ <name>HDS</name>
+ <desc>Horizontal display area start in dot clock</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>HDE</name>
+ <desc>Horizontal display area end in dot clock</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DAV</name>
+ <title>Display Area Vertical Start/End Point</title>
+ <instance>
+ <name>DAV</name>
+ <address>0x14</address>
+ </instance>
+ <register>
+ <field>
+ <name>VDS</name>
+ <desc>Vertical display area start in line clock</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>VDE</name>
+ <desc>Vertical display area end in line clock</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PS</name>
+ <title>PS Signal Setting</title>
+ <instance>
+ <name>PS</name>
+ <address>0x18</address>
+ </instance>
+ <register>
+ <field>
+ <name>PSS</name>
+ <desc>PS signal start position in dot clock</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>PSE</name>
+ <desc>PS signal end position in dot clock</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CLS</name>
+ <title>CLS Signal Setting</title>
+ <instance>
+ <name>CLS</name>
+ <address>0x1c</address>
+ </instance>
+ <register>
+ <field>
+ <name>CLSS</name>
+ <desc>CLS signal start position in dot clock</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>CLSE</name>
+ <desc>CLS signal end position in dot clock</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SPL</name>
+ <title>SPL Signal Setting</title>
+ <instance>
+ <name>SPL</name>
+ <address>0x20</address>
+ </instance>
+ <register>
+ <field>
+ <name>SPLS</name>
+ <desc>SPL signal start position in dot clock</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>SPLE</name>
+ <desc>SPL signal end position in dot clock</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>REV</name>
+ <title>REV Signal Setting</title>
+ <instance>
+ <name>REV</name>
+ <address>0x24</address>
+ </instance>
+ <register>
+ <field>
+ <name>REVS</name>
+ <desc>REV signal start position in dot clock</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CTRL</name>
+ <title>LCD Control Register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0x30</address>
+ </instance>
+ <register>
+ <field>
+ <name>PINMD</name>
+ <desc>This register set Pin distribution in 16-bit parallel mode, 0: 16-bit data correspond with LCD_D[15:0], 1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1]</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>BST</name>
+ <desc>16-word contiue</desc>
+ <position>28</position>
+ <width>3</width>
+ <enum>
+ <name>4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>64</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>16_CTN</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>C16</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>RGB555</name>
+ <desc>RGB555 mode(foreground 0 in OSD mode)</desc>
+ <position>27</position>
+ </field>
+ <field>
+ <name>OFUP</name>
+ <desc>Output FIFO underrun protection enable</desc>
+ <position>26</position>
+ </field>
+ <field>
+ <name>FRC</name>
+ <desc>2 grayscale</desc>
+ <position>24</position>
+ <width>2</width>
+ <enum>
+ <name>16</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>PDD</name>
+ <desc>Load Palette Delay Counter</desc>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>EOFM</name>
+ <desc>EOF interrupt mask</desc>
+ <position>13</position>
+ </field>
+ <field>
+ <name>SOFM</name>
+ <desc>SOF interrupt mask</desc>
+ <position>12</position>
+ </field>
+ <field>
+ <name>OFUM</name>
+ <desc>Output FIFO underrun interrupt mask</desc>
+ <position>11</position>
+ </field>
+ <field>
+ <name>IFUM0</name>
+ <desc>Input FIFO 0 underrun interrupt mask</desc>
+ <position>10</position>
+ </field>
+ <field>
+ <name>IFUM1</name>
+ <desc>Input FIFO 1 underrun interrupt mask</desc>
+ <position>9</position>
+ </field>
+ <field>
+ <name>LDDM</name>
+ <desc>LCD disable done interrupt mask</desc>
+ <position>8</position>
+ </field>
+ <field>
+ <name>QDM</name>
+ <desc>LCD quick disable done interrupt mask</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>BEDN</name>
+ <desc>Endian selection</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>PEDN</name>
+ <desc>Endian in byte:0-msb first, 1-lsb first</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>DIS</name>
+ <desc>Disable indicate bit</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>ENA</name>
+ <desc>LCD enable bit</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>BPP</name>
+ <desc>30 bpp</desc>
+ <position>0</position>
+ <width>3</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>18_24</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>CMPS_24</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>30</name>
+ <value>0x7</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>STATE</name>
+ <title>LCD Status Register</title>
+ <instance>
+ <name>STATE</name>
+ <address>0x34</address>
+ </instance>
+ <register>
+ <field>
+ <name>FEND</name>
+ <position>22</position>
+ </field>
+ <field>
+ <name>PWRUP</name>
+ <position>20</position>
+ </field>
+ <field>
+ <name>PWRDN</name>
+ <position>19</position>
+ </field>
+ <field>
+ <name>QD</name>
+ <desc>Quick Disable Done</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>EOF</name>
+ <desc>EOF Flag</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>SOF</name>
+ <desc>SOF Flag</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>OFU</name>
+ <desc>Output FIFO Underrun</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>IFU0</name>
+ <desc>Input FIFO 0 Underrun</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>IFU1</name>
+ <desc>Input FIFO 1 Underrun</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>LDD</name>
+ <desc>LCD Disabled</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>IID</name>
+ <title>Interrupt ID Register</title>
+ <instance>
+ <name>IID</name>
+ <address>0x38</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DA</name>
+ <title>Descriptor Address Register 1</title>
+ <instance>
+ <name>DA</name>
+ <range>
+ <first>0</first>
+ <address>0x40</address>
+ <address>0x50</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>SA</name>
+ <title>Source Address Register 1</title>
+ <instance>
+ <name>SA</name>
+ <range>
+ <first>0</first>
+ <address>0x44</address>
+ <address>0x54</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>FID</name>
+ <title>Frame ID Register 1</title>
+ <instance>
+ <name>FID</name>
+ <range>
+ <first>0</first>
+ <address>0x48</address>
+ <address>0x58</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CMD</name>
+ <title>DMA Command Register 1</title>
+ <instance>
+ <name>CMD</name>
+ <range>
+ <first>0</first>
+ <address>0x4c</address>
+ <address>0x5c</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>SOFINT</name>
+ <position>31</position>
+ </field>
+ <field>
+ <name>EOFINT</name>
+ <position>30</position>
+ </field>
+ <field>
+ <name>CMD</name>
+ <desc>indicate command in slcd mode</desc>
+ <position>29</position>
+ </field>
+ <field>
+ <name>PAL</name>
+ <position>28</position>
+ </field>
+ <field>
+ <name>LEN</name>
+ <position>0</position>
+ <width>24</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OFFS</name>
+ <title>DMA Offsize Register 1</title>
+ <instance>
+ <name>OFFS</name>
+ <range>
+ <first>0</first>
+ <address>0x60</address>
+ <address>0x70</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PW</name>
+ <title>DMA Page Width Register 1</title>
+ <instance>
+ <name>PW</name>
+ <range>
+ <first>0</first>
+ <address>0x64</address>
+ <address>0x74</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CNUM</name>
+ <title>DMA Command Counter Register 1</title>
+ <instance>
+ <name>CNUM</name>
+ <range>
+ <first>0</first>
+ <address>0x68</address>
+ <address>0x78</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DESSIZE</name>
+ <title>Foreground Size in Descriptor 1 Register</title>
+ <instance>
+ <name>DESSIZE</name>
+ <range>
+ <first>0</first>
+ <address>0x6c</address>
+ <address>0x7c</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>HEIGHT</name>
+ <desc>height of foreground 1</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>WIDTH</name>
+ <desc>width of foreground 1</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RGBC</name>
+ <title>RGB Controll Register</title>
+ <instance>
+ <name>RGBC</name>
+ <address>0x90</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>RGBDM</name>
+ <desc>enable RGB Dummy data</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>DMM</name>
+ <desc>RGB Dummy mode</desc>
+ <position>14</position>
+ </field>
+ <field>
+ <name>YCC</name>
+ <desc>RGB to YCC</desc>
+ <position>8</position>
+ </field>
+ <field>
+ <name>ODDRGB</name>
+ <desc>odd line serial RGB data arrangement</desc>
+ <position>4</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>EVENRGB</name>
+ <desc>even line serial RGB data arrangement</desc>
+ <position>0</position>
+ <width>3</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OSDC</name>
+ <title>LCD OSD Configure Register</title>
+ <instance>
+ <name>OSDC</name>
+ <address>0x100</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>SOFM1</name>
+ <desc>Start of frame interrupt mask for foreground 1</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>EOFM1</name>
+ <desc>End of frame interrupt mask for foreground 1</desc>
+ <position>14</position>
+ </field>
+ <field>
+ <name>SOFM0</name>
+ <desc>Start of frame interrupt mask for foreground 0</desc>
+ <position>11</position>
+ </field>
+ <field>
+ <name>EOFM0</name>
+ <desc>End of frame interrupt mask for foreground 0</desc>
+ <position>10</position>
+ </field>
+ <field>
+ <name>ENDM</name>
+ <desc>End of frame interrupt mask for panel.</desc>
+ <position>9</position>
+ </field>
+ <field>
+ <name>F1EN</name>
+ <desc>enable foreground 1</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>F0EN</name>
+ <desc>enable foreground 0</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>ALPHAEN</name>
+ <desc>enable alpha blending</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>ALPHAMD</name>
+ <desc>alpha blending mode</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>OSDEN</name>
+ <desc>OSD mode enable</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OSDCTRL</name>
+ <title>LCD OSD Control Register</title>
+ <instance>
+ <name>OSDCTRL</name>
+ <address>0x104</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>IPU</name>
+ <desc>input data from IPU</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>RGB555</name>
+ <desc>foreground 1, 16bpp, 0-RGB565, 1-RGB555</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>CHANGES</name>
+ <desc>Change size flag</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>OSDBPP</name>
+ <desc>RGB 30 bit</desc>
+ <position>0</position>
+ <width>3</width>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>15_16</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>18_24</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>CMPS_24</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>30</name>
+ <value>0x7</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OSDS</name>
+ <title>LCD OSD Status Register</title>
+ <instance>
+ <name>OSDS</name>
+ <address>0x108</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>SOF1</name>
+ <desc>Start of frame flag for foreground 1</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>EOF1</name>
+ <desc>End of frame flag for foreground 1</desc>
+ <position>14</position>
+ </field>
+ <field>
+ <name>SOF0</name>
+ <desc>Start of frame flag for foreground 0</desc>
+ <position>11</position>
+ </field>
+ <field>
+ <name>EOF0</name>
+ <desc>End of frame flag for foreground 0</desc>
+ <position>10</position>
+ </field>
+ <field>
+ <name>READY</name>
+ <desc>Read for accept the change</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>BGC</name>
+ <title>LCD Background Color Register</title>
+ <instance>
+ <name>BGC</name>
+ <address>0x10c</address>
+ </instance>
+ <register>
+ <field>
+ <name>RED</name>
+ <desc>Red color offset</desc>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>GREEN</name>
+ <desc>Green color offset</desc>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>BLUE</name>
+ <desc>Blue color offset</desc>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>KEY</name>
+ <title>LCD Foreground Color Key Register 1</title>
+ <instance>
+ <name>KEY</name>
+ <range>
+ <first>0</first>
+ <address>0x110</address>
+ <address>0x114</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>KEYEN</name>
+ <desc>enable color key</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>KEYMD</name>
+ <desc>color key mode</desc>
+ <position>30</position>
+ </field>
+ <field>
+ <name>RED</name>
+ <desc>Red color offset</desc>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>GREEN</name>
+ <desc>Green color offset</desc>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>BLUE</name>
+ <desc>Blue color offset</desc>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ALPHA</name>
+ <title>LCD ALPHA Register</title>
+ <instance>
+ <name>ALPHA</name>
+ <address>0x118</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>IPUR</name>
+ <title>LCD IPU Restart Register</title>
+ <instance>
+ <name>IPUR</name>
+ <address>0x11c</address>
+ </instance>
+ <register>
+ <field>
+ <name>IPUREN</name>
+ <desc>IPU restart function enable</desc>
+ <position>31</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>XYP</name>
+ <title>Foreground 1 XY Position Register</title>
+ <instance>
+ <name>XYP</name>
+ <range>
+ <first>0</first>
+ <address>0x120</address>
+ <address>0x124</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>YPOS</name>
+ <desc>Y position bit of foreground 0 or 1</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>XPOS</name>
+ <desc>X position bit of foreground 0 or 1</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SIZE</name>
+ <title>Foreground 1 Size Register</title>
+ <instance>
+ <name>SIZE</name>
+ <range>
+ <first>0</first>
+ <address>0x128</address>
+ <address>0x12c</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DA0_PART2</name>
+ <title>Descriptor Address Register PART2</title>
+ <instance>
+ <name>DA0_PART2</name>
+ <address>0x1c0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>SA0_PART2</name>
+ <title>Source Address Register PART2</title>
+ <instance>
+ <name>SA0_PART2</name>
+ <address>0x1c4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>FID0_PART2</name>
+ <title>Frame ID Register PART2</title>
+ <instance>
+ <name>FID0_PART2</name>
+ <address>0x1c8</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CMD0_PART2</name>
+ <title>DMA Command Register PART2</title>
+ <instance>
+ <name>CMD0_PART2</name>
+ <address>0x1cc</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>OFFS0_PART2</name>
+ <title>DMA Offsize Register PART2</title>
+ <instance>
+ <name>OFFS0_PART2</name>
+ <address>0x1e0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PW0_PART2</name>
+ <title>DMA Command Counter Register PART2</title>
+ <instance>
+ <name>PW0_PART2</name>
+ <address>0x1e4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CNUM0_PART2</name>
+ <title>Foreground Size in Descriptor PART2 Register</title>
+ <instance>
+ <name>CNUM0_PART2</name>
+ <address>0x1e8</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DESSIZE0_PART2</name>
+ <instance>
+ <name>DESSIZE0_PART2</name>
+ <address>0x1ec</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>XYP0_PART2</name>
+ <title>Foreground 0 PART2 XY Position Register</title>
+ <instance>
+ <name>XYP0_PART2</name>
+ <address>0x1f0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>SIZE0_PART2</name>
+ <title>Foreground 0 PART2 Size Register</title>
+ <instance>
+ <name>SIZE0_PART2</name>
+ <address>0x1f4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PCFG</name>
+ <instance>
+ <name>PCFG</name>
+ <address>0x2c0</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>SLCD</name>
+ <title>Smart LCD Controller</title>
+ <instance>
+ <name>SLCD</name>
+ <address>0xb3050000</address>
+ </instance>
+ <node>
+ <name>MCFG</name>
+ <title>SLCD Configure Register</title>
+ <instance>
+ <name>SCFG</name>
+ <address>0xa0</address>
+ </instance>
+ <register>
+ <field>
+ <name>DWIDTH</name>
+ <position>10</position>
+ <width>3</width>
+ <enum>
+ <name>18BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>16BIT</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>8BIT_x3</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>8BIT_x2</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>8BIT_x1</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>24BIT</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>9BIT_x2</name>
+ <value>0x7</value>
+ </enum>
+ </field>
+ <field>
+ <name>CWIDTH</name>
+ <position>8</position>
+ <width>2</width>
+ <enum>
+ <name>16BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8BIT</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>18BIT</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>24BIT</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>CS_ACTIVE_HIGH</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RS_CMD_HIGH</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>CLK_ACTIVE_RISING</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>TYPE_SERIAL</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>MCTRL</name>
+ <title>SLCD Control Register</title>
+ <instance>
+ <name>SCTRL</name>
+ <address>0xa4</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>DMA_MODE</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DMA_START</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DMA_EN</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>MSTATE</name>
+ <title>SLCD Status Register</title>
+ <instance>
+ <name>SSTATE</name>
+ <address>0xa8</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>BUSY</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>MDATA</name>
+ <title>SLCD Data Register</title>
+ <instance>
+ <name>MDATA</name>
+ <address>0xac</address>
+ </instance>
+ <register>
+ <field>
+ <name>RS_COMMAND</name>
+ <position>31</position>
+ </field>
+ </register>
+ </node>
+ </node>
+ <node>
+ <name>TVE</name>
+ <title>TVE (TV Encoder Controller)</title>
+ <instance>
+ <name>TVE</name>
+ <address>0xb3050100</address>
+ </instance>
+ <node>
+ <name>CTRL</name>
+ <title>TV Encoder Control register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0x40</address>
+ </instance>
+ <register>
+ <field>
+ <name>EYCBCR</name>
+ <desc>YCbCr_enable</desc>
+ <position>25</position>
+ </field>
+ <field>
+ <name>ECVBS</name>
+ <desc>1: cvbs_enable 0: s-video</desc>
+ <position>24</position>
+ </field>
+ <field>
+ <name>DAPD3</name>
+ <desc>DAC 3 power down</desc>
+ <position>23</position>
+ </field>
+ <field>
+ <name>DAPD2</name>
+ <desc>DAC 2 power down</desc>
+ <position>22</position>
+ </field>
+ <field>
+ <name>DAPD1</name>
+ <desc>DAC 1 power down</desc>
+ <position>21</position>
+ </field>
+ <field>
+ <name>DAPD</name>
+ <desc>power down all DACs</desc>
+ <position>20</position>
+ </field>
+ <field>
+ <name>YCDLY</name>
+ <position>16</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>CGAIN</name>
+ <desc>gain = 3/4</desc>
+ <position>14</position>
+ <width>2</width>
+ <enum>
+ <name>FULL</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>QUTR</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>HALF</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>THREE_QURT</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>CBW</name>
+ <desc>Ultra wide band</desc>
+ <position>12</position>
+ <width>2</width>
+ <enum>
+ <name>NARROW</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>WIDE</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>EXTRA</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>ULTRA</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>SYNCT</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>PAL</name>
+ <desc>1: PAL, 0: NTSC</desc>
+ <position>8</position>
+ </field>
+ <field>
+ <name>FINV</name>
+ <desc>invert_top:1-invert top and bottom fields.</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>ZBLACK</name>
+ <desc>bypass_yclamp:1-Black of luminance (Y) input is 0.</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>CR1ST</name>
+ <desc>uv_order:0-Cb before Cr,1-Cr before Cb</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>CLBAR</name>
+ <desc>Color bar mode:0-Output input video to TV,1-Output color bar to TV</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>SWRST</name>
+ <desc>Software reset:1-TVE is reset</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>FRCFG</name>
+ <title>Frame configure register</title>
+ <instance>
+ <name>FRCFG</name>
+ <address>0x44</address>
+ </instance>
+ <register>
+ <field>
+ <name>L1ST</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>NLINE</name>
+ <position>0</position>
+ <width>10</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SLCFG1</name>
+ <title>TV signal level configure register 1</title>
+ <instance>
+ <name>SLCFG1</name>
+ <address>0x50</address>
+ </instance>
+ <register>
+ <field>
+ <name>WHITEL</name>
+ <position>16</position>
+ <width>10</width>
+ </field>
+ <field>
+ <name>BLACKL</name>
+ <position>0</position>
+ <width>10</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SLCFG2</name>
+ <title>TV signal level configure register 2</title>
+ <instance>
+ <name>SLCFG2</name>
+ <address>0x54</address>
+ </instance>
+ <register>
+ <field>
+ <name>VBLANKL</name>
+ <position>16</position>
+ <width>10</width>
+ </field>
+ <field>
+ <name>BLANKL</name>
+ <position>0</position>
+ <width>10</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SLCFG3</name>
+ <title>TV signal level configure register 3</title>
+ <instance>
+ <name>SLCFG3</name>
+ <address>0x58</address>
+ </instance>
+ <register>
+ <field>
+ <name>SYNCL</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>LTCFG1</name>
+ <title>Line timing configure register 1</title>
+ <instance>
+ <name>LTCFG1</name>
+ <address>0x60</address>
+ </instance>
+ <register>
+ <field>
+ <name>FRONTP</name>
+ <position>16</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>HSYNCW</name>
+ <position>8</position>
+ <width>7</width>
+ </field>
+ <field>
+ <name>BACKP</name>
+ <position>0</position>
+ <width>7</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>LTCFG2</name>
+ <title>Line timing configure register 2</title>
+ <instance>
+ <name>LTCFG2</name>
+ <address>0x64</address>
+ </instance>
+ <register>
+ <field>
+ <name>ACTLIN</name>
+ <position>16</position>
+ <width>11</width>
+ </field>
+ <field>
+ <name>PREBW</name>
+ <position>8</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>BURSTW</name>
+ <position>0</position>
+ <width>6</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CFREQ</name>
+ <title>Chrominance sub-carrier frequency configure register</title>
+ <instance>
+ <name>CFREQ</name>
+ <address>0x70</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CPHASE</name>
+ <title>Chrominance sub-carrier phase configure register</title>
+ <instance>
+ <name>CPHASE</name>
+ <address>0x74</address>
+ </instance>
+ <register>
+ <field>
+ <name>INITPH</name>
+ <position>24</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>ACTPH</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>CCRSTP</name>
+ <desc>Never</desc>
+ <position>0</position>
+ <width>2</width>
+ <enum>
+ <name>8</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>0</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CBCRCFG</name>
+ <title>Chrominance filter configure register</title>
+ <instance>
+ <name>CBCRCFG</name>
+ <address>0x78</address>
+ </instance>
+ <register>
+ <field>
+ <name>CBBA</name>
+ <position>24</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>CRBA</name>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>CBGAIN</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>CRGAIN</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>WSSCR</name>
+ <title>Wide screen signal control register</title>
+ <instance>
+ <name>WSSCR</name>
+ <address>0x80</address>
+ </instance>
+ <register>
+ <field>
+ <name>NCHFREQ</name>
+ <position>12</position>
+ <width>3</width>
+ </field>
+ <field>
+ <name>WSSEDGE</name>
+ <position>4</position>
+ <width>3</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>WSSCFG1</name>
+ <title>Wide screen signal configure register 1</title>
+ <instance>
+ <name>WSSCFG1</name>
+ <address>0x84</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>WSSCFG2</name>
+ <title>Wide screen signal configure register 2</title>
+ <instance>
+ <name>WSSCFG2</name>
+ <address>0x88</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>WSSCFG3</name>
+ <title>Wide screen signal configure register 3</title>
+ <instance>
+ <name>WSSCFG3</name>
+ <address>0x8c</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>CIM</name>
+ <instance>
+ <name>CIM</name>
+ <address>0xb3060000</address>
+ </instance>
+ <node>
+ <name>CFG</name>
+ <instance>
+ <name>CFG</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>RXF_TRIG</name>
+ <position>24</position>
+ <width>6</width>
+ </field>
+ <field>
+ <name>SEP</name>
+ <position>20</position>
+ </field>
+ <field>
+ <name>ORDER</name>
+ <desc>CrY0CbY1; CrCbY</desc>
+ <position>18</position>
+ <width>2</width>
+ <enum>
+ <name>0</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>DF</name>
+ <desc>ITU656 YCbCr422</desc>
+ <position>16</position>
+ <width>2</width>
+ <enum>
+ <name>YUV444</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>YUV422</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>ITU656</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>INV_DAT</name>
+ <position>15</position>
+ </field>
+ <field>
+ <name>VSP</name>
+ <desc>VSYNC Polarity:0-rising edge active,1-falling edge active</desc>
+ <position>14</position>
+ </field>
+ <field>
+ <name>HSP</name>
+ <desc>HSYNC Polarity:0-rising edge active,1-falling edge active</desc>
+ <position>13</position>
+ </field>
+ <field>
+ <name>PCP</name>
+ <desc>PCLK working edge: 0-rising, 1-falling</desc>
+ <position>12</position>
+ </field>
+ <field>
+ <name>DMA</name>
+ <desc>Suggested High speed AHB</desc>
+ <position>10</position>
+ <width>2</width>
+ <enum>
+ <name>BURST_INCR4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>BURST_INCR8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>BURST_INCR16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>BURST_INCR32</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>DUMMY_ZERO</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>EXT_VSYNC</name>
+ <desc>Only for ITU656 Progressive mode</desc>
+ <position>8</position>
+ </field>
+ <field>
+ <name>PACK</name>
+ <desc>11 44 33 22 0xY0CrY1Cb</desc>
+ <position>4</position>
+ <width>3</width>
+ <enum>
+ <name>0</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>1</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>5</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>6</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>7</name>
+ <value>0x7</value>
+ </enum>
+ </field>
+ <field>
+ <name>BYPASS</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DSM</name>
+ <desc>Gated Clock Mode</desc>
+ <position>0</position>
+ <width>2</width>
+ <enum>
+ <name>CPM</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>CIM</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>GCM</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>CTRL</name>
+ <title>CIM Control Register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <field>
+ <name>EEOF_LINE</name>
+ <position>20</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>FRC</name>
+ <desc>Sample 1/16 frame</desc>
+ <position>16</position>
+ <width>4</width>
+ <enum>
+ <name>1</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>3</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>5</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>6</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>7</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x7</value>
+ </enum>
+ <enum>
+ <name>9</name>
+ <value>0x8</value>
+ </enum>
+ <enum>
+ <name>10</name>
+ <value>0x9</value>
+ </enum>
+ <enum>
+ <name>11</name>
+ <value>0xa</value>
+ </enum>
+ <enum>
+ <name>12</name>
+ <value>0xb</value>
+ </enum>
+ <enum>
+ <name>13</name>
+ <value>0xc</value>
+ </enum>
+ <enum>
+ <name>14</name>
+ <value>0xd</value>
+ </enum>
+ <enum>
+ <name>15</name>
+ <value>0xe</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0xf</value>
+ </enum>
+ </field>
+ <field>
+ <name>DMA_EEOFM</name>
+ <desc>Enable EEOF interrupt</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>WIN_EN</name>
+ <position>14</position>
+ </field>
+ <field>
+ <name>VDDM</name>
+ <desc>VDD interrupt enable</desc>
+ <position>13</position>
+ </field>
+ <field>
+ <name>DMA_SOFM</name>
+ <position>12</position>
+ </field>
+ <field>
+ <name>DMA_EOFM</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>DMA_STOPM</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>RXF_TRIGM</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>RXF_OFM</name>
+ <position>8</position>
+ </field>
+ <field>
+ <name>DMA_SYNC</name>
+ <desc>when change DA, do frame sync</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>RXF_TRIG</name>
+ <desc>trigger value = (n+1)*burst_type</desc>
+ <position>3</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>DMA_EN</name>
+ <desc>Enable DMA</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RXF_RST</name>
+ <desc>RxFIFO reset</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ENA</name>
+ <desc>Enable CIM</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>STATE</name>
+ <title>CIM State Register</title>
+ <instance>
+ <name>STATE</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <field>
+ <name>CR_RF_OF</name>
+ <position>27</position>
+ </field>
+ <field>
+ <name>CR_RF_TRIG</name>
+ <position>26</position>
+ </field>
+ <field>
+ <name>CR_RF_EMPTY</name>
+ <position>25</position>
+ </field>
+ <field>
+ <name>CB_RF_OF</name>
+ <position>19</position>
+ </field>
+ <field>
+ <name>CB_RF_TRIG</name>
+ <position>18</position>
+ </field>
+ <field>
+ <name>CB_RF_EMPTY</name>
+ <position>17</position>
+ </field>
+ <field>
+ <name>Y_RF_OF</name>
+ <position>11</position>
+ </field>
+ <field>
+ <name>Y_RF_TRIG</name>
+ <position>10</position>
+ </field>
+ <field>
+ <name>Y_RF_EMPTY</name>
+ <position>9</position>
+ </field>
+ <field>
+ <name>DMA_EEOF</name>
+ <desc>DMA Line EEOf irq</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>DMA_SOF</name>
+ <desc>DMA start irq</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>DMA_EOF</name>
+ <desc>DMA end irq</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>DMA_STOP</name>
+ <desc>DMA stop irq</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RXF_OF</name>
+ <desc>RXFIFO over flow irq</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>RXF_TRIG</name>
+ <desc>RXFIFO triger meet irq</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RXF_EMPTY</name>
+ <desc>RXFIFO empty irq</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>VDD</name>
+ <desc>CIM disabled irq</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>IID</name>
+ <instance>
+ <name>IID</name>
+ <address>0xc</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>RXFIFO</name>
+ <instance>
+ <name>RXFIFO</name>
+ <address>0x10</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DA</name>
+ <instance>
+ <name>DA</name>
+ <address>0x20</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>FA</name>
+ <instance>
+ <name>FA</name>
+ <address>0x24</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>FID</name>
+ <instance>
+ <name>FID</name>
+ <address>0x28</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CMD</name>
+ <title>CIM DMA Command Register</title>
+ <instance>
+ <name>CMD</name>
+ <address>0x2c</address>
+ </instance>
+ <register>
+ <field>
+ <name>SOFINT</name>
+ <desc>enable DMA start irq</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>EOFINT</name>
+ <desc>enable DMA end irq</desc>
+ <position>30</position>
+ </field>
+ <field>
+ <name>EEOFINT</name>
+ <desc>enable DMA EEOF irq</desc>
+ <position>29</position>
+ </field>
+ <field>
+ <name>STOP</name>
+ <desc>enable DMA stop irq</desc>
+ <position>28</position>
+ </field>
+ <field>
+ <name>OFRCV</name>
+ <desc>enable recovery when TXFiFo overflow</desc>
+ <position>27</position>
+ </field>
+ <field>
+ <name>LEN</name>
+ <position>0</position>
+ <width>24</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SIZE</name>
+ <title>CIM Window-Image Size Register</title>
+ <instance>
+ <name>SIZE</name>
+ <address>0x30</address>
+ </instance>
+ <register>
+ <field>
+ <name>LPF</name>
+ <desc>Lines per freame for csc output image</desc>
+ <position>16</position>
+ <width>13</width>
+ </field>
+ <field>
+ <name>PPL</name>
+ <desc>Pixels per line for csc output image, should be an even number</desc>
+ <position>0</position>
+ <width>13</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OFFSET</name>
+ <title>CIM Image Offset Register</title>
+ <instance>
+ <name>OFFSET</name>
+ <address>0x34</address>
+ </instance>
+ <register>
+ <field>
+ <name>V</name>
+ <desc>Vertical offset</desc>
+ <position>16</position>
+ <width>12</width>
+ </field>
+ <field>
+ <name>H</name>
+ <desc>OFFSET_H should be even number</desc>
+ <position>0</position>
+ <width>12</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>YFA</name>
+ <instance>
+ <name>YFA</name>
+ <address>0x38</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>YCMD</name>
+ <instance>
+ <name>YCMD</name>
+ <address>0x3c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CBFA</name>
+ <instance>
+ <name>CBFA</name>
+ <address>0x40</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CBCMD</name>
+ <instance>
+ <name>CBCMD</name>
+ <address>0x44</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CRFA</name>
+ <instance>
+ <name>CRFA</name>
+ <address>0x48</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CRCMD</name>
+ <instance>
+ <name>CRCMD</name>
+ <address>0x4c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CTRL2</name>
+ <instance>
+ <name>CTRL2</name>
+ <address>0x50</address>
+ </instance>
+ <register>
+ <field>
+ <name>OPG</name>
+ <position>4</position>
+ <width>2</width>
+ </field>
+ <field>
+ <name>OPE</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>EME</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>APM</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>RAM_ADDR</name>
+ <instance>
+ <name>RAM_ADDR</name>
+ <address>0x1000</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>IPU</name>
+ <instance>
+ <name>IPU</name>
+ <address>0xb3080000</address>
+ </instance>
+ </node>
+ <node>
+ <name>IPU_V</name>
+ <instance>
+ <name>IPU_V</name>
+ <address>0xb3080000</address>
+ </instance>
+ </node>
+ <node>
+ <name>HARB1</name>
+ <title>AHB1 BUS Devices Base</title>
+ <instance>
+ <name>HARB1</name>
+ <address>0xb3200000</address>
+ </instance>
+ </node>
+ <node>
+ <name>DMAGP0</name>
+ <instance>
+ <name>DMAGP0</name>
+ <address>0xb3210000</address>
+ </instance>
+ </node>
+ <node>
+ <name>DMAGP1</name>
+ <instance>
+ <name>DMAGP1</name>
+ <address>0xb3220000</address>
+ </instance>
+ </node>
+ <node>
+ <name>DMAGP2</name>
+ <instance>
+ <name>DMAGP2</name>
+ <address>0xb3230000</address>
+ </instance>
+ </node>
+ <node>
+ <name>MC</name>
+ <instance>
+ <name>MC</name>
+ <address>0xb3250000</address>
+ </instance>
+ <node>
+ <name>MCCR</name>
+ <title>MC Control Register</title>
+ <instance>
+ <name>MCCR</name>
+ <address>0x0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCSR</name>
+ <title>MC Status Register</title>
+ <instance>
+ <name>MCSR</name>
+ <address>0x4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCRBAR</name>
+ <instance>
+ <name>MCRBAR</name>
+ <address>0x8</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCT1LFCR</name>
+ <instance>
+ <name>MCT1LFCR</name>
+ <address>0xc</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCT2LFCR</name>
+ <instance>
+ <name>MCT2LFCR</name>
+ <address>0x10</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCCBAR</name>
+ <instance>
+ <name>MCCBAR</name>
+ <address>0x14</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCIIR</name>
+ <instance>
+ <name>MCIIR</name>
+ <address>0x18</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCSIR</name>
+ <instance>
+ <name>MCSIR</name>
+ <address>0x1c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCT1MFCR</name>
+ <instance>
+ <name>MCT1MFCR</name>
+ <address>0x20</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCT2MFCR</name>
+ <instance>
+ <name>MCT2MFCR</name>
+ <address>0x24</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCFGIR</name>
+ <instance>
+ <name>MCFGIR</name>
+ <address>0x28</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCFCIR</name>
+ <instance>
+ <name>MCFCIR</name>
+ <address>0x2c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MCRNDTR</name>
+ <instance>
+ <name>MCRNDTR</name>
+ <address>0x40</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2CR</name>
+ <instance>
+ <name>MC2CR</name>
+ <address>0x8000</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2SR</name>
+ <instance>
+ <name>MC2SR</name>
+ <address>0x8004</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2RBAR</name>
+ <instance>
+ <name>MC2RBAR</name>
+ <address>0x8008</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2CBAR</name>
+ <instance>
+ <name>MC2CBAR</name>
+ <address>0x800c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2IIR</name>
+ <instance>
+ <name>MC2IIR</name>
+ <address>0x8010</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2TFCR</name>
+ <instance>
+ <name>MC2TFCR</name>
+ <address>0x8014</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2SIR</name>
+ <instance>
+ <name>MC2SIR</name>
+ <address>0x8018</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2FCIR</name>
+ <instance>
+ <name>MC2FCIR</name>
+ <address>0x801c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MC2RNDTR</name>
+ <instance>
+ <name>MC2RNDTR</name>
+ <address>0x8040</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>ME</name>
+ <instance>
+ <name>ME</name>
+ <address>0xb3260000</address>
+ </instance>
+ <node>
+ <name>MECR</name>
+ <title>ME control register</title>
+ <instance>
+ <name>MECR</name>
+ <address>0x0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MERBAR</name>
+ <instance>
+ <name>MERBAR</name>
+ <address>0x4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MECBAR</name>
+ <instance>
+ <name>MECBAR</name>
+ <address>0x8</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MEDAR</name>
+ <instance>
+ <name>MEDAR</name>
+ <address>0xc</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MERFSR</name>
+ <instance>
+ <name>MERFSR</name>
+ <address>0x10</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MECFSR</name>
+ <instance>
+ <name>MECFSR</name>
+ <address>0x14</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MEDFSR</name>
+ <instance>
+ <name>MEDFSR</name>
+ <address>0x18</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MESR</name>
+ <title>ME settings register</title>
+ <instance>
+ <name>MESR</name>
+ <address>0x1c</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MEMR</name>
+ <title>ME MVD register</title>
+ <instance>
+ <name>MEMR</name>
+ <address>0x20</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>MEFR</name>
+ <title>ME flag register</title>
+ <instance>
+ <name>MEFR</name>
+ <address>0x24</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>DEBLK</name>
+ <instance>
+ <name>DEBLK</name>
+ <address>0xb3270000</address>
+ </instance>
+ </node>
+ <node>
+ <name>IDCT</name>
+ <instance>
+ <name>IDCT</name>
+ <address>0xb3280000</address>
+ </instance>
+ </node>
+ <node>
+ <name>CABAC</name>
+ <instance>
+ <name>CABAC</name>
+ <address>0xb3290000</address>
+ </instance>
+ </node>
+ <node>
+ <name>TCSM0</name>
+ <instance>
+ <name>TCSM0</name>
+ <address>0xb32b0000</address>
+ </instance>
+ </node>
+ <node>
+ <name>TCSM1</name>
+ <instance>
+ <name>TCSM1</name>
+ <address>0xb32c0000</address>
+ </instance>
+ </node>
+ <node>
+ <name>SRAM</name>
+ <instance>
+ <name>SRAM</name>
+ <address>0xb32d0000</address>
+ </instance>
+ </node>
+ <node>
+ <name>HARB2</name>
+ <title>AHB2 BUS Devices Base</title>
+ <instance>
+ <name>HARB2</name>
+ <address>0xb3400000</address>
+ </instance>
+ </node>
+ <node>
+ <name>NEMC</name>
+ <instance>
+ <name>NEMC</name>
+ <address>0xb3410000</address>
+ </instance>
+ <node>
+ <name>SMC</name>
+ <instance>
+ <name>SMC</name>
+ <range>
+ <first>1</first>
+ <address>0x14</address>
+ <address>0x18</address>
+ <address>0x1c</address>
+ <address>0x20</address>
+ <address>0x24</address>
+ <address>0x28</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>STRV</name>
+ <position>24</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>TAW</name>
+ <position>20</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TBP</name>
+ <position>16</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TAH</name>
+ <position>12</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>TAS</name>
+ <position>8</position>
+ <width>4</width>
+ </field>
+ <field>
+ <name>BW</name>
+ <position>6</position>
+ <width>2</width>
+ <enum>
+ <name>8BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>16BIT</name>
+ <value>0x1</value>
+ </enum>
+ </field>
+ <field>
+ <name>BL</name>
+ <position>1</position>
+ <width>2</width>
+ <enum>
+ <name>4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>SMT</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>SMA</name>
+ <instance>
+ <name>SMA</name>
+ <range>
+ <first>1</first>
+ <address>0x34</address>
+ <address>0x38</address>
+ <address>0x3c</address>
+ <address>0x40</address>
+ <address>0x44</address>
+ <address>0x48</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>BASE</name>
+ <position>8</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>MASK</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>NFC</name>
+ <title>NAND Flash Control/Status Register</title>
+ <instance>
+ <name>NFC</name>
+ <address>0x50</address>
+ </instance>
+ <register>
+ <field>
+ <name>NFCE4</name>
+ <desc>NAND Flash Enable</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>NFE4</name>
+ <desc>NAND Flash FCE# Assertion Enable</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>NFCE3</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>NFE3</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>NFCE2</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>NFE2</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>NFCE1</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>NFE1</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>PNC</name>
+ <instance>
+ <name>PNC</name>
+ <address>0x100</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>PND</name>
+ <instance>
+ <name>PND</name>
+ <address>0x104</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>BITCNT</name>
+ <instance>
+ <name>BITCNT</name>
+ <address>0x108</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>DMAC</name>
+ <title>DMAC (DMA Controller)</title>
+ <instance>
+ <name>DMAC</name>
+ <address>0xb3420000</address>
+ </instance>
+ <node>
+ <name>DSAR</name>
+ <title>DMA source address</title>
+ <instance>
+ <name>DSAR</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">((n)/6*0x100 + 0x00 + ((n)-(n)/6*6) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DTAR</name>
+ <title>DMA target address</title>
+ <instance>
+ <name>DTAR</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">((n)/6*0x100 + 0x04 + ((n)-(n)/6*6) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DTCR</name>
+ <title>DMA transfer count</title>
+ <instance>
+ <name>DTCR</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">((n)/6*0x100 + 0x08 + ((n)-(n)/6*6) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DRSR</name>
+ <title>DMA request source</title>
+ <instance>
+ <name>DRSR</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">((n)/6*0x100 + 0x0c + ((n)-(n)/6*6) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>RS</name>
+ <position>0</position>
+ <width>6</width>
+ <enum>
+ <name>AUTO</name>
+ <value>0x8</value>
+ </enum>
+ <enum>
+ <name>TSSIIN</name>
+ <value>0x9</value>
+ </enum>
+ <enum>
+ <name>EXTERN</name>
+ <value>0xc</value>
+ </enum>
+ <enum>
+ <name>UART3OUT</name>
+ <value>0xe</value>
+ </enum>
+ <enum>
+ <name>UART3IN</name>
+ <value>0xf</value>
+ </enum>
+ <enum>
+ <name>UART2OUT</name>
+ <value>0x10</value>
+ </enum>
+ <enum>
+ <name>UART2IN</name>
+ <value>0x11</value>
+ </enum>
+ <enum>
+ <name>UART1OUT</name>
+ <value>0x12</value>
+ </enum>
+ <enum>
+ <name>UART1IN</name>
+ <value>0x13</value>
+ </enum>
+ <enum>
+ <name>UART0OUT</name>
+ <value>0x14</value>
+ </enum>
+ <enum>
+ <name>UART0IN</name>
+ <value>0x15</value>
+ </enum>
+ <enum>
+ <name>SSI0OUT</name>
+ <value>0x16</value>
+ </enum>
+ <enum>
+ <name>SSI0IN</name>
+ <value>0x17</value>
+ </enum>
+ <enum>
+ <name>AICOUT</name>
+ <value>0x18</value>
+ </enum>
+ <enum>
+ <name>AICIN</name>
+ <value>0x19</value>
+ </enum>
+ <enum>
+ <name>MSC0OUT</name>
+ <value>0x1a</value>
+ </enum>
+ <enum>
+ <name>MSC0IN</name>
+ <value>0x1b</value>
+ </enum>
+ <enum>
+ <name>TCU</name>
+ <value>0x1c</value>
+ </enum>
+ <enum>
+ <name>SADC</name>
+ <value>0x1d</value>
+ </enum>
+ <enum>
+ <name>MSC1OUT</name>
+ <value>0x1e</value>
+ </enum>
+ <enum>
+ <name>MSC1IN</name>
+ <value>0x1f</value>
+ </enum>
+ <enum>
+ <name>SSI1OUT</name>
+ <value>0x20</value>
+ </enum>
+ <enum>
+ <name>SSI1IN</name>
+ <value>0x21</value>
+ </enum>
+ <enum>
+ <name>PMOUT</name>
+ <value>0x22</value>
+ </enum>
+ <enum>
+ <name>PMIN</name>
+ <value>0x23</value>
+ </enum>
+ <enum>
+ <name>MSC2OUT</name>
+ <value>0x24</value>
+ </enum>
+ <enum>
+ <name>MSC2IN</name>
+ <value>0x25</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DCCSR</name>
+ <title>DMA control/status</title>
+ <instance>
+ <name>DCCSR</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">((n)/6*0x100 + 0x10 + ((n)-(n)/6*6) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>NDES</name>
+ <desc>descriptor (0) or not (1) ?</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>DES8</name>
+ <desc>Descriptor 8 Word</desc>
+ <position>30</position>
+ </field>
+ <field>
+ <name>CDOA</name>
+ <desc>copy of DMA offset address</desc>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>AR</name>
+ <desc>address error</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>TT</name>
+ <desc>transfer terminated</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>HLT</name>
+ <desc>DMA halted</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>CT</name>
+ <desc>count terminated</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>EN</name>
+ <desc>channel enable bit</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DCMD</name>
+ <title>DMA command</title>
+ <instance>
+ <name>DCMD</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">((n)/6*0x100 + 0x14 + ((n)-(n)/6*6) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>EACKS_LOW</name>
+ <desc>External DACK Output Level Select, active low</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>EACKM_WRITE</name>
+ <desc>External DACK Output Mode Select, output in write cycle</desc>
+ <position>30</position>
+ </field>
+ <field>
+ <name>ERDM</name>
+ <desc>External DREQ Detection Mode Select</desc>
+ <position>28</position>
+ <width>2</width>
+ <enum>
+ <name>LOW</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>FALL</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>HIGH</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>RISE</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>SAI</name>
+ <desc>source address increment</desc>
+ <position>23</position>
+ </field>
+ <field>
+ <name>DAI</name>
+ <desc>dest address increment</desc>
+ <position>22</position>
+ </field>
+ <field>
+ <name>RDIL</name>
+ <desc>request detection interval length</desc>
+ <position>16</position>
+ <width>4</width>
+ <enum>
+ <name>IGN</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>2</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>12</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x5</value>
+ </enum>
+ <enum>
+ <name>20</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>24</name>
+ <value>0x7</value>
+ </enum>
+ <enum>
+ <name>28</name>
+ <value>0x8</value>
+ </enum>
+ <enum>
+ <name>32</name>
+ <value>0x9</value>
+ </enum>
+ <enum>
+ <name>48</name>
+ <value>0xa</value>
+ </enum>
+ <enum>
+ <name>60</name>
+ <value>0xb</value>
+ </enum>
+ <enum>
+ <name>64</name>
+ <value>0xc</value>
+ </enum>
+ <enum>
+ <name>124</name>
+ <value>0xd</value>
+ </enum>
+ <enum>
+ <name>128</name>
+ <value>0xe</value>
+ </enum>
+ <enum>
+ <name>200</name>
+ <value>0xf</value>
+ </enum>
+ </field>
+ <field>
+ <name>SWDH</name>
+ <desc>source port width</desc>
+ <position>14</position>
+ <width>2</width>
+ <enum>
+ <name>32</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>DWDH</name>
+ <desc>dest port width</desc>
+ <position>12</position>
+ <width>2</width>
+ <enum>
+ <name>32</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>DS</name>
+ <desc>transfer data size of a data unit</desc>
+ <position>8</position>
+ <width>3</width>
+ <enum>
+ <name>32BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8BIT</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16BIT</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>16BYTE</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>32BYTE</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>64BYTE</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>STDE</name>
+ <desc>Stride Disable/Enable</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>TIE</name>
+ <desc>DMA transfer interrupt enable</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>LINK</name>
+ <desc>descriptor link enable</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DDA</name>
+ <title>DMA descriptor address</title>
+ <instance>
+ <name>DDA</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">((n)/6*0x100 + 0x18 + ((n)-(n)/6*6) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>BASE</name>
+ <desc>descriptor base address</desc>
+ <position>12</position>
+ <width>20</width>
+ </field>
+ <field>
+ <name>OFFSET</name>
+ <desc>descriptor offset address</desc>
+ <position>4</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DSD</name>
+ <title>DMA Stride Address</title>
+ <instance>
+ <name>DSD</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">((n)/6*0x100 + 0x1c + ((n)-(n)/6*6) * 0x04)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>TSD</name>
+ <desc>target stride address</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>SSD</name>
+ <desc>source stride address</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DMACR</name>
+ <title>DMA control register</title>
+ <instance>
+ <name>DMACR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="m">0x0300 + 0x100 * (m)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>FMSC</name>
+ <desc>MSC Fast DMA mode</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>FSSI</name>
+ <desc>SSI Fast DMA mode</desc>
+ <position>30</position>
+ </field>
+ <field>
+ <name>FTSSI</name>
+ <desc>TSSI Fast DMA mode</desc>
+ <position>29</position>
+ </field>
+ <field>
+ <name>FUART</name>
+ <desc>UART Fast DMA mode</desc>
+ <position>28</position>
+ </field>
+ <field>
+ <name>FAIC</name>
+ <desc>AIC Fast DMA mode</desc>
+ <position>27</position>
+ </field>
+ <field>
+ <name>PR</name>
+ <desc>channel priority mode</desc>
+ <position>8</position>
+ <width>2</width>
+ <enum>
+ <name>012345</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>120345</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>230145</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>340125</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>HLT</name>
+ <desc>DMA halt flag</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>AR</name>
+ <desc>address error flag</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DMAE</name>
+ <desc>DMA enable bit</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DMAIPR</name>
+ <title>DMA interrupt pending</title>
+ <instance>
+ <name>DMAIPR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="m">0x0304 + 0x100 * (m)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>CIRQ5</name>
+ <desc>irq pending status for channel 5</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>CIRQ4</name>
+ <desc>irq pending status for channel 4</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>CIRQ3</name>
+ <desc>irq pending status for channel 3</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>CIRQ2</name>
+ <desc>irq pending status for channel 2</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>CIRQ1</name>
+ <desc>irq pending status for channel 1</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>CIRQ0</name>
+ <desc>irq pending status for channel 0</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DMADBR</name>
+ <title>DMA doorbell</title>
+ <instance>
+ <name>DMADBR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="m">0x0308 + 0x100 * (m)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>DB5</name>
+ <desc>doorbell for channel 5</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>DB4</name>
+ <desc>doorbell for channel 4</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DB3</name>
+ <desc>doorbell for channel 3</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>DB2</name>
+ <desc>doorbell for channel 2</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DB1</name>
+ <desc>doorbell for channel 1</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DB0</name>
+ <desc>doorbell for channel 0</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DMADBSR</name>
+ <title>DMA doorbell set</title>
+ <instance>
+ <name>DMADBSR</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="m">0x030C + 0x100 * (m)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>DBS5</name>
+ <desc>enable doorbell for channel 5</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>DBS4</name>
+ <desc>enable doorbell for channel 4</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DBS3</name>
+ <desc>enable doorbell for channel 3</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>DBS2</name>
+ <desc>enable doorbell for channel 2</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DBS1</name>
+ <desc>enable doorbell for channel 1</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DBS0</name>
+ <desc>enable doorbell for channel 0</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DMACK</name>
+ <instance>
+ <name>DMACK</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="m">0x0310 + 0x100 * (m)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DMACKS</name>
+ <instance>
+ <name>DMACKS</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="m">0x0314 + 0x100 * (m)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DMACKC</name>
+ <instance>
+ <name>DMACKC</name>
+ <range>
+ <first>0</first>
+ <count>2</count>
+ <formula variable="m">0x0318 + 0x100 * (m)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>UHC</name>
+ <instance>
+ <name>UHC</name>
+ <address>0xb3430000</address>
+ </instance>
+ </node>
+ <node>
+ <name>USB</name>
+ <instance>
+ <name>USB</name>
+ <address>0xb3440000</address>
+ </instance>
+ <node>
+ <name>FADDR</name>
+ <title>Function Address 8-bit</title>
+ <instance>
+ <name>FADDR</name>
+ <address>0x0</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>POWER</name>
+ <title>Power register bit masks</title>
+ <instance>
+ <name>POWER</name>
+ <address>0x1</address>
+ </instance>
+ <register>
+ <field>
+ <name>SOFTCONN</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>HSENAB</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>HSMODE</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>RESUME</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>SUSPENDM</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>INTRIN</name>
+ <title>Interrupt IN 16-bit</title>
+ <instance>
+ <name>INTRIN</name>
+ <address>0x2</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>INTROUT</name>
+ <title>Interrupt OUT 16-bit</title>
+ <instance>
+ <name>INTROUT</name>
+ <address>0x4</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>INTRINE</name>
+ <title>Intr IN enable 16-bit</title>
+ <instance>
+ <name>INTRINE</name>
+ <address>0x6</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>INTROUTE</name>
+ <title>Intr OUT enable 16-bit</title>
+ <instance>
+ <name>INTROUTE</name>
+ <address>0x8</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>INTRUSB</name>
+ <title>Interrupt register bit masks</title>
+ <instance>
+ <name>INTRUSB</name>
+ <address>0xa</address>
+ </instance>
+ <register>
+ <field>
+ <name>RESET</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>RESUME</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>SUSPEND</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>INTRUSBE</name>
+ <title>Interrupt USB Enable 8-bit</title>
+ <instance>
+ <name>INTRUSBE</name>
+ <address>0xb</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>FRAME</name>
+ <title>Frame number 16-bit</title>
+ <instance>
+ <name>FRAME</name>
+ <address>0xc</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>INDEX</name>
+ <title>Index register 8-bit</title>
+ <instance>
+ <name>INDEX</name>
+ <address>0xe</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>TESTMODE</name>
+ <title>Testmode register bits</title>
+ <instance>
+ <name>TESTMODE</name>
+ <address>0xf</address>
+ </instance>
+ <register>
+ <field>
+ <name>PACKET</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>K</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>J</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>SE0NAK</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>INMAXP</name>
+ <title>EP1-2 IN Max Pkt Size 16-bit</title>
+ <instance>
+ <name>INMAXP</name>
+ <address>0x10</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CSR0</name>
+ <title>CSR0 bit masks</title>
+ <instance>
+ <name>CSR0</name>
+ <address>0x12</address>
+ </instance>
+ <register>
+ <field>
+ <name>SVDSETUPEND</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>SVDOUTPKTRDY</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>SENDSTALL</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>SETUPEND</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DATAEND</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>SENTSTALL</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>INPKTRDY</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>OUTPKTRDY</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>INCSR</name>
+ <title>EP1-2 IN CSR LSB 8/16bit</title>
+ <instance>
+ <name>INCSR</name>
+ <address>0x12</address>
+ </instance>
+ <register>
+ <field>
+ <name>CDT</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>SENTSTALL</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>SENDSTALL</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>FF</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>UNDERRUN</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>FFNOTEMPT</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>INPKTRDY</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>INCSRH</name>
+ <title>Endpoint CSR register bits</title>
+ <instance>
+ <name>INCSRH</name>
+ <address>0x13</address>
+ </instance>
+ <register>
+ <field>
+ <name>AUTOSET</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>ISO</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>MODE</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>DMAREQENAB</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DMAREQMODE</name>
+ <position>2</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OUTMAXP</name>
+ <title>EP1 OUT Max Pkt Size 16-bit</title>
+ <instance>
+ <name>OUTMAXP</name>
+ <address>0x14</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>OUTCSR</name>
+ <title>EP1 OUT CSR LSB 8/16bit</title>
+ <instance>
+ <name>OUTCSR</name>
+ <address>0x16</address>
+ </instance>
+ <register>
+ <field>
+ <name>CDT</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>SENTSTALL</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>SENDSTALL</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>FF</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DATAERR</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>OVERRUN</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>FFFULL</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>OUTPKTRDY</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OUTCSRH</name>
+ <title>EP1 OUT CSR MSB 8-bit</title>
+ <instance>
+ <name>OUTCSRH</name>
+ <address>0x17</address>
+ </instance>
+ <register>
+ <field>
+ <name>AUTOCLR</name>
+ <position>7</position>
+ </field>
+ <field>
+ <name>ISO</name>
+ <position>6</position>
+ </field>
+ <field>
+ <name>DMAREQENAB</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>DNYT</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DMAREQMODE</name>
+ <position>3</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>OUTCOUNT</name>
+ <title>bytes in EP0/1 OUT FIFO 16-bit</title>
+ <instance>
+ <name>OUTCOUNT</name>
+ <address>0x18</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>FIFO_EP0</name>
+ <instance>
+ <name>FIFO_EP0</name>
+ <address>0x20</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>FIFO_EP1</name>
+ <instance>
+ <name>FIFO_EP1</name>
+ <address>0x24</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>FIFO_EP2</name>
+ <instance>
+ <name>FIFO_EP2</name>
+ <address>0x28</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>EPINFO</name>
+ <title>Endpoint information</title>
+ <instance>
+ <name>EPINFO</name>
+ <address>0x78</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>RAMINFO</name>
+ <title>RAM information</title>
+ <instance>
+ <name>RAMINFO</name>
+ <address>0x79</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>INTR</name>
+ <title>DMA pending interrupts</title>
+ <instance>
+ <name>INTR</name>
+ <address>0x200</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>CNTL</name>
+ <title>DMA control bits</title>
+ <instance>
+ <name>CNTL</name>
+ <range>
+ <first>1</first>
+ <address>0x204</address>
+ <address>0x214</address>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>BURST</name>
+ <position>9</position>
+ <width>2</width>
+ <enum>
+ <name>0</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>4</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>INTR_EN</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>MODE_1</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DIR_IN</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ENA</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>ADDR</name>
+ <title>DMA channel 2 AHB memory addr</title>
+ <instance>
+ <name>ADDR</name>
+ <range>
+ <first>1</first>
+ <address>0x208</address>
+ <address>0x218</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>COUNT</name>
+ <title>DMA channel 2 byte count</title>
+ <instance>
+ <name>COUNT</name>
+ <range>
+ <first>1</first>
+ <address>0x20c</address>
+ <address>0x21c</address>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>BDMAC</name>
+ <title>BDMAC (BCH &amp; NAND DMA Controller)</title>
+ <instance>
+ <name>BDMAC</name>
+ <address>0xb3450000</address>
+ </instance>
+ <node>
+ <name>DSA</name>
+ <title>DMA source address</title>
+ <instance>
+ <name>DSA</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0x00 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DTA</name>
+ <title>DMA target address</title>
+ <instance>
+ <name>DTA</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0x04 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DTC</name>
+ <title>DMA transfer count</title>
+ <instance>
+ <name>DTC</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0x08 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DRT</name>
+ <title>BDMA request source register</title>
+ <instance>
+ <name>DRT</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0x0c + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>RS</name>
+ <position>0</position>
+ <width>6</width>
+ <enum>
+ <name>BCH_ENC</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>BCH_DEC</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>NAND0</name>
+ <value>0x6</value>
+ </enum>
+ <enum>
+ <name>NAND1</name>
+ <value>0x7</value>
+ </enum>
+ <enum>
+ <name>AUTO</name>
+ <value>0x8</value>
+ </enum>
+ <enum>
+ <name>EXT</name>
+ <value>0xc</value>
+ </enum>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DCS</name>
+ <title>BDMA channel control/status register</title>
+ <instance>
+ <name>DCS</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0x10 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>NDES</name>
+ <desc>descriptor (0) or not (1) ?</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>DES8</name>
+ <desc>Descriptor 8 Word</desc>
+ <position>30</position>
+ </field>
+ <field>
+ <name>LASTMD1</name>
+ <desc>BCH Decoding last mode 1, there's two descriptor for decoding blcok</desc>
+ <position>28</position>
+ </field>
+ <field>
+ <name>CDOA</name>
+ <desc>copy of DMA offset address</desc>
+ <position>16</position>
+ <width>8</width>
+ </field>
+ <field>
+ <name>BERR</name>
+ <desc>BCH error within this transfer, Only for channel 0</desc>
+ <position>7</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>BUERR</name>
+ <desc>BCH uncorrectable error, only for channel 0</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>NSERR</name>
+ <desc>status error, only for channel 1</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>AR</name>
+ <desc>address error</desc>
+ <position>4</position>
+ </field>
+ <field>
+ <name>TT</name>
+ <desc>transfer terminated</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>HLT</name>
+ <desc>DMA halted</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>BAC</name>
+ <desc>BCH auto correction</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>EN</name>
+ <desc>channel enable bit</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DCM</name>
+ <title>BDMA channel command register</title>
+ <instance>
+ <name>DCM</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0x14 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>EACKS_LOW</name>
+ <desc>External DACK Output Level Select, active low</desc>
+ <position>31</position>
+ </field>
+ <field>
+ <name>EACKM_WRITE</name>
+ <desc>External DACK Output Mode Select, output in write cycle</desc>
+ <position>30</position>
+ </field>
+ <field>
+ <name>ERDM</name>
+ <desc>External DREQ Detection Mode Select</desc>
+ <position>28</position>
+ <width>2</width>
+ <enum>
+ <name>LOW</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>FALL</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>HIGH</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>RISE</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>BLAST</name>
+ <desc>BCH last</desc>
+ <position>25</position>
+ </field>
+ <field>
+ <name>SAI</name>
+ <desc>source address increment</desc>
+ <position>23</position>
+ </field>
+ <field>
+ <name>DAI</name>
+ <desc>dest address increment</desc>
+ <position>22</position>
+ </field>
+ <field>
+ <name>SWDH</name>
+ <desc>source port width</desc>
+ <position>14</position>
+ <width>2</width>
+ <enum>
+ <name>32</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>DWDH</name>
+ <desc>dest port width</desc>
+ <position>12</position>
+ <width>2</width>
+ <enum>
+ <name>32</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x2</value>
+ </enum>
+ </field>
+ <field>
+ <name>DS</name>
+ <desc>transfer data size of a data unit</desc>
+ <position>8</position>
+ <width>3</width>
+ <enum>
+ <name>32BIT</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8BIT</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>16BIT</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>16BYTE</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>32BYTE</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>64BYTE</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>NRD</name>
+ <desc>NAND direct read</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>NWR</name>
+ <desc>NAND direct write</desc>
+ <position>6</position>
+ </field>
+ <field>
+ <name>NAC</name>
+ <desc>NAND AL/CL enable</desc>
+ <position>5</position>
+ </field>
+ <field>
+ <name>STDE</name>
+ <desc>Stride Disable/Enable</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>TIE</name>
+ <desc>DMA transfer interrupt enable</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>LINK</name>
+ <desc>descriptor link enable</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DDA</name>
+ <title>BDMA descriptor address register</title>
+ <instance>
+ <name>DDA</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0x18 + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>BASE</name>
+ <desc>descriptor base address</desc>
+ <position>12</position>
+ <width>20</width>
+ </field>
+ <field>
+ <name>OFFSET</name>
+ <desc>descriptor offset address</desc>
+ <position>4</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DSD</name>
+ <title>BDMA stride address register</title>
+ <instance>
+ <name>DSD</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0x1c + (n) * 0x20)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>TSD</name>
+ <desc>target stride address</desc>
+ <position>16</position>
+ <width>16</width>
+ </field>
+ <field>
+ <name>SSD</name>
+ <desc>source stride address</desc>
+ <position>0</position>
+ <width>16</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DNT</name>
+ <title>BDMA NAND Detect timer register</title>
+ <instance>
+ <name>DNT</name>
+ <range>
+ <first>0</first>
+ <count>3</count>
+ <formula variable="n">(0xc0 + (n) * 0x04)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>DTCT</name>
+ <desc>tail counter</desc>
+ <position>16</position>
+ <width>7</width>
+ </field>
+ <field>
+ <name>DNTE</name>
+ <desc>enable detect timer</desc>
+ <position>15</position>
+ </field>
+ <field>
+ <name>DNT</name>
+ <desc>detect counter</desc>
+ <position>0</position>
+ <width>6</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DMAC</name>
+ <title>BDMA control register</title>
+ <instance>
+ <name>DMAC</name>
+ <address>0x300</address>
+ </instance>
+ <register>
+ <field>
+ <name>PR</name>
+ <desc>channel priority mode</desc>
+ <position>8</position>
+ <width>2</width>
+ <enum>
+ <name>01_2</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>12_0</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>20_1</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>012</name>
+ <value>0x3</value>
+ </enum>
+ </field>
+ <field>
+ <name>HLT</name>
+ <desc>DMA halt flag</desc>
+ <position>3</position>
+ </field>
+ <field>
+ <name>AR</name>
+ <desc>address error flag</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DMAE</name>
+ <desc>DMA enable bit</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DIRQP</name>
+ <title>BDMA interrupt pending register</title>
+ <instance>
+ <name>DIRQP</name>
+ <address>0x304</address>
+ </instance>
+ <register>
+ <field>
+ <name>CIRQ2</name>
+ <desc>irq pending status for channel 2</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>CIRQ1</name>
+ <desc>irq pending status for channel 1</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>CIRQ0</name>
+ <desc>irq pending status for channel 0</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DDR</name>
+ <title>BDMA doorbell register</title>
+ <instance>
+ <name>DDR</name>
+ <address>0x308</address>
+ </instance>
+ <register>
+ <field>
+ <name>DB2</name>
+ <desc>doorbell for channel 2</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DB1</name>
+ <desc>doorbell for channel 1</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DB0</name>
+ <desc>doorbell for channel 0</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DDRS</name>
+ <title>BDMA doorbell set register</title>
+ <instance>
+ <name>DDRS</name>
+ <address>0x30c</address>
+ </instance>
+ <register>
+ <field>
+ <name>DBS2</name>
+ <desc>enable doorbell for channel 2</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>DBS1</name>
+ <desc>enable doorbell for channel 1</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>DBS0</name>
+ <desc>enable doorbell for channel 0</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DCKE</name>
+ <title>DMA clock enable</title>
+ <instance>
+ <name>DCKE</name>
+ <address>0x310</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DCKES</name>
+ <instance>
+ <name>DCKES</name>
+ <address>0x314</address>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>DCKEC</name>
+ <instance>
+ <name>DCKEC</name>
+ <address>0x318</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+ <node>
+ <name>GPS</name>
+ <instance>
+ <name>GPS</name>
+ <address>0xb3480000</address>
+ </instance>
+ </node>
+ <node>
+ <name>ETHC</name>
+ <instance>
+ <name>ETHC</name>
+ <address>0xb34b0000</address>
+ </instance>
+ </node>
+ <node>
+ <name>BCH</name>
+ <instance>
+ <name>BCH</name>
+ <address>0xb34d0000</address>
+ </instance>
+ <node>
+ <name>CTRL</name>
+ <title>BCH Control register</title>
+ <instance>
+ <name>CTRL</name>
+ <address>0x0</address>
+ </instance>
+ <register>
+ <field>
+ <name>DMAE</name>
+ <desc>BCH DMA Enable</desc>
+ <position>7</position>
+ </field>
+ <field>
+ <name>BSEL</name>
+ <desc>24 Bit BCH Select</desc>
+ <position>3</position>
+ <width>3</width>
+ <enum>
+ <name>4</name>
+ <value>0x0</value>
+ </enum>
+ <enum>
+ <name>8</name>
+ <value>0x1</value>
+ </enum>
+ <enum>
+ <name>12</name>
+ <value>0x2</value>
+ </enum>
+ <enum>
+ <name>16</name>
+ <value>0x3</value>
+ </enum>
+ <enum>
+ <name>20</name>
+ <value>0x4</value>
+ </enum>
+ <enum>
+ <name>24</name>
+ <value>0x5</value>
+ </enum>
+ </field>
+ <field>
+ <name>ENCE</name>
+ <desc>BCH Encoding Select</desc>
+ <position>2</position>
+ </field>
+ <field>
+ <name>BRST</name>
+ <desc>BCH Reset</desc>
+ <position>1</position>
+ </field>
+ <field>
+ <name>BCHE</name>
+ <desc>BCH Enable</desc>
+ <position>0</position>
+ </field>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </register>
+ </node>
+ <node>
+ <name>COUNT</name>
+ <title>BCH ENC/DEC Count Register</title>
+ <instance>
+ <name>COUNT</name>
+ <address>0xc</address>
+ </instance>
+ <register>
+ <field>
+ <name>DEC</name>
+ <position>16</position>
+ <width>11</width>
+ </field>
+ <field>
+ <name>ENC</name>
+ <position>0</position>
+ <width>11</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>DATA</name>
+ <title>BCH data register</title>
+ <instance>
+ <name>DATA</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>8</width>
+ </register>
+ </node>
+ <node>
+ <name>PARITY</name>
+ <title>BCH Parity register</title>
+ <instance>
+ <name>PARITY</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">0x14 + 4 *(n)</formula>
+ </range>
+ </instance>
+ <register/>
+ </node>
+ <node>
+ <name>ERROR</name>
+ <title>BCH Error Report Register</title>
+ <instance>
+ <name>ERROR</name>
+ <range>
+ <first>0</first>
+ <count>12</count>
+ <formula variable="n">0x3C + 4*(n)</formula>
+ </range>
+ </instance>
+ <register>
+ <field>
+ <name>INDEX_ODD</name>
+ <position>16</position>
+ <width>13</width>
+ </field>
+ <field>
+ <name>INDEX_EVEN</name>
+ <position>0</position>
+ <width>13</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>INTS</name>
+ <title>BCH Interrupt Status Register</title>
+ <instance>
+ <name>INTS</name>
+ <address>0x6c</address>
+ </instance>
+ <register>
+ <field>
+ <name>ERRC</name>
+ <position>27</position>
+ <width>5</width>
+ </field>
+ <field>
+ <name>ALL0</name>
+ <position>5</position>
+ </field>
+ <field>
+ <name>ALLf</name>
+ <position>4</position>
+ </field>
+ <field>
+ <name>DECF</name>
+ <position>3</position>
+ </field>
+ <field>
+ <name>ENCF</name>
+ <position>2</position>
+ </field>
+ <field>
+ <name>UNCOR</name>
+ <position>1</position>
+ </field>
+ <field>
+ <name>ERR</name>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>INTE</name>
+ <title>BCH Interrupt Enable register</title>
+ <instance>
+ <name>INTE</name>
+ <address>0x70</address>
+ </instance>
+ <register/>
+ </node>
+ </node>
+</soc>