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authorCástor Muñoz <cmvidal@gmail.com>2016-05-15 02:32:40 +0200
committerCástor Muñoz <cmvidal@gmail.com>2016-05-15 22:57:12 +0200
commit52a6db3a363e915b1af7eb37778baaee81306c48 (patch)
tree0987c86a4f429f32b0ec236eba23d5b88ac65a3b /utils/regtools
parent201f57171a67530a288f2a29a7a7060293e93bf2 (diff)
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iPod Classic: optimize UDMA timming for ATA drives
This patch optimizes UDMA timings to increase write transfer rate on ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to decrease Tcyctyp (typical write cycle period). This is not overclocking, we meet the ATA standar, the settings used by OF are not well optimized for each UDMA mode, we will never know but probably this was due some documentation issue. ATA_UDMA_TIME register is documented on s3c6400 datasheet, information included in s5l8700 datasheet is wrong or not valid for s5l8702. From ATA specs, (Minimum, Maximum) values in nanoseconds: UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4 tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55) tRP (160, --) (125, --) (100, --) (100, --) (100, --) tSS (50, --) (50, --) (50, --) (50, --) (50, --) tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --) tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --) tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --) Tcyc = tDVS+tDVH WR[bytes/s] = 1/Tcyc[s] * 2[bytes] On Classic (boosted): HClk = 108 MHz. -> T = ~9.26 ns. Old values (used by OF): UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s) 0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4 1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6 2 0x3030a52 27.8 101.8 55.6 37 37 74 27 3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36 4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2 New values: UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s) 0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6 1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24 2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9 3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2 4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54 To verify that the settings are correct, a write-to-cache test was performed using emCORE, the measured transfer rate (WRm) is compared against the theoric transfer rate (WR) at 108 Mhz for the old and the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL): UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s) 4 0x2010a52 46.3 43.2 42.9 59.8 4 0x1010a52 37 54 53.5 59.8 Notes: - The new UDMA4 settings increases ~25% the ATA transfer rate for cached-writes. The real HDD write speed is limited by the internal transfer rate (depends on cilinder, for the MK1634GAL it is 276 to 573 Mbits/s). Sequential write benchmark using diskdump on USB are ~8% faster. - Read transfers are clocked by the device, it depends on UDMA mode selected and are not affected by HClk or ATA_UDMA_TIME settings. Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for UDMA4 are 59.8 MB/s on MK1634GAL. - Minimum HClk is limited by tACKENV specs, using current settings it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0. Change-Id: I61d67060410752518a59e1ff08072b21747ca997
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