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authorAidan MacDonald <amachronic@protonmail.com>2021-09-27 17:18:19 +0100
committerAidan MacDonald <amachronic@protonmail.com>2021-10-16 16:58:19 -0400
commit7a5130a27722b95f0de965e99e1fd7cb322cafcf (patch)
tree34abc836f0862540a71d2622a2b64bc0cdaeabe4 /utils
parentbf54002bc19b6dde4c9e3ad5b5c505facd1af95a (diff)
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x1000: fix broken OST2 timer prescaler
It turns out the prescaler fields in OST_CTRL are 2 bits wide, not 3. The programming manual (as usual) is ambiguous and its diagram shows 2-bit wide fields, but the bit positions in the text give a 3-bit wide field. Ingenic's Linux code and my own testing shows that they are, in fact, 2 bits wide. This caused the OST2 divisor to be 16 instead of 4; the OST1 divisor was correct. This means that all udelay/mdelay calls took 4x longer than they should've. After this change the OST2 prescaler will be 4, as intended, and udelay/mdelay calls will wait for the intended duration. Change-Id: I2ac0a9190f49b59a840c649bf586131f5f9fde82
Diffstat (limited to 'utils')
-rw-r--r--utils/reggen-ng/x1000.reggen4
1 files changed, 2 insertions, 2 deletions
diff --git a/utils/reggen-ng/x1000.reggen b/utils/reggen-ng/x1000.reggen
index d34a0eb7bc..8c6c49e27d 100644
--- a/utils/reggen-ng/x1000.reggen
+++ b/utils/reggen-ng/x1000.reggen
@@ -807,8 +807,8 @@ node OST {
addr 0xb2000000
reg CTRL 0x00 {
- field 5 3 PRESCALE2 { enum BY_1 0; enum BY_4 1; enum BY_16 2; }
- field 2 0 PRESCALE1 { enum BY_1 0; enum BY_4 1; enum BY_16 2; }
+ field 3 2 PRESCALE2 { enum BY_1 0; enum BY_4 1; enum BY_16 2; }
+ field 1 0 PRESCALE1 { enum BY_1 0; enum BY_4 1; enum BY_16 2; }
}
reg ENABLE 0x04 {