summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--bootloader/SOURCES2
-rwxr-xr-xbootloader/ondavx747.c125
-rw-r--r--firmware/SOURCES29
-rwxr-xr-xfirmware/export/config-ondavx747.h170
-rw-r--r--firmware/export/config.h12
-rwxr-xr-xfirmware/export/jz4740.h4902
-rwxr-xr-xfirmware/export/mips-archdefs.h2356
-rwxr-xr-xfirmware/export/mips.h820
-rwxr-xr-xfirmware/export/mipsregs.h985
-rw-r--r--firmware/export/thread.h8
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/ata-jz4740.c40
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/boot.lds107
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/crt0.S246
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/lcd-jz4740.c94
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h28
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c80
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h37
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c123
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h69
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c201
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h36
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h26
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/system-jz4740.c71
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/system-target.h103
-rw-r--r--firmware/thread.c147
-rwxr-xr-xtools/configure34
-rwxr-xr-xtools/rockboxdev.sh2
27 files changed, 10853 insertions, 0 deletions
diff --git a/bootloader/SOURCES b/bootloader/SOURCES
index 19e40e2fc3..9f8cf1c91c 100644
--- a/bootloader/SOURCES
+++ b/bootloader/SOURCES
@@ -31,4 +31,6 @@ mrobe500.c
telechips.c
#elif defined(MEIZU_M6SL)
meizu_m6sl.c
+#elif defined(ONDA_VX747)
+ondavx747.c
#endif
diff --git a/bootloader/ondavx747.c b/bootloader/ondavx747.c
new file mode 100755
index 0000000000..46e81cacad
--- /dev/null
+++ b/bootloader/ondavx747.c
@@ -0,0 +1,125 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <string.h>
+#include "config.h"
+#include "jz4740.h"
+#include "backlight.h"
+#include "font.h"
+#include "lcd.h"
+#include "system.h"
+#include "mips.h"
+#include "button.h"
+
+int _line = 1;
+char _printfbuf[256];
+
+/* This is all rather hacky, but it works... */
+void _printf(const char *format, ...)
+{
+ int len;
+ unsigned char *ptr;
+ va_list ap;
+ va_start(ap, format);
+
+ ptr = _printfbuf;
+ len = vsnprintf(ptr, sizeof(_printfbuf), format, ap);
+ va_end(ap);
+
+ int i;
+ for(i=0; i<1; i++)
+ {
+ lcd_puts(0, _line++, ptr);
+ lcd_update();
+ }
+ if(_line >= LCD_HEIGHT/SYSFONT_HEIGHT)
+ _line = 1;
+}
+
+void audiotest(void)
+{
+ __i2s_internal_codec();
+ __aic_enable();
+ __aic_reset();
+ __aic_select_i2s();
+ __aic_enable_loopback();
+}
+
+static void jz_store_icache(void)
+{
+ unsigned long start;
+ unsigned long end;
+
+ start = KSEG0BASE;
+ end = start + CFG_ICACHE_SIZE;
+ while(start < end)
+ {
+ cache_unroll(start, 8);
+ start += CFG_CACHELINE_SIZE;
+ }
+}
+
+int main(void)
+{
+ cli();
+
+ write_c0_status(0x10000400);
+
+ memcpy((void *)A_K0BASE, (void *)0x80E00080, 0x20);
+ memcpy((void *)(A_K0BASE + 0x180), (void *)0x80E00080, 0x20);
+ memcpy((void *)(A_K0BASE + 0x200), (void *)0x80E00080, 0x20);
+
+ jz_flush_dcache();
+ jz_store_icache();
+
+ sti();
+
+ kernel_init();
+ lcd_init();
+ font_init();
+ lcd_setfont(FONT_SYSFIXED);
+ button_init();
+
+ backlight_init();
+
+ /* To make the Windows say "ding-dong".. */
+ REG8(USB_REG_POWER) &= ~USB_POWER_SOFTCONN;
+
+ int touch;
+ lcd_clear_display();
+ _printf("Rockbox bootloader v0.000001");
+ while(1)
+ {
+ if(button_read_device(&touch) & BUTTON_VOL_DOWN)
+ _printf("BUTTON_VOL_DOWN");
+ if(button_read_device(&touch) & BUTTON_MENU)
+ _printf("BUTTON_MENU");
+ if(button_read_device(&touch) & BUTTON_VOL_UP)
+ _printf("BUTTON_VOL_UP");
+ if(button_read_device(&touch) & BUTTON_POWER)
+ _printf("BUTTON_POWER");
+ _printf("X: %d Y: %d", touch>>16, touch&0xFFFF);
+ }
+
+ return 0;
+}
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 3617f978ef..89f5a26c78 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -325,9 +325,11 @@ target/arm/i2c-telechips.c
#elif CONFIG_I2C == I2C_S3C2440
/* no i2c driver yet */
#endif
+
#if CONFIG_CPU == PNX0101
target/arm/pnx0101/system-pnx0101.c
#endif
+
#if defined(CPU_PP)
#if CONFIG_CPU == PP5002
target/arm/system-pp5002.c
@@ -362,6 +364,21 @@ target/arm/crt0.S
#endif /* defined(CPU_*) */
#endif /* SIMULATOR */
+#elif defined(CPU_MIPS)
+#undef mips
+/*target/mips/memcpy.S
+target/mips/memset.S
+common/memset16.c
+target/mips/strlen.S*/
+common/memcpy.c
+common/memmove.c
+common/memset.c
+common/memset16.c
+common/strlen.c
+#if CONFIG_CPU==JZ4732
+target/mips/ingenic_jz47xx/crt0.S
+#endif /* CONFIG_CPU == JZ4732 */
+
#else
#ifdef HAVE_PRIORITY_SCHEDULING
@@ -1054,3 +1071,15 @@ target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c
#endif /* BOOTLOADER */
#endif /* SIMULATOR */
#endif /* MEIZU_M6SL */
+
+#if CONFIG_CPU==JZ4732
+target/mips/ingenic_jz47xx/ata-jz4740.c
+target/mips/ingenic_jz47xx/lcd-jz4740.c
+target/mips/ingenic_jz47xx/system-jz4740.c
+#endif
+
+#ifdef ONDA_VX747
+target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c
+target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c
+target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
+#endif
diff --git a/firmware/export/config-ondavx747.h b/firmware/export/config-ondavx747.h
new file mode 100755
index 0000000000..b5519b21ee
--- /dev/null
+++ b/firmware/export/config-ondavx747.h
@@ -0,0 +1,170 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/*
+ * This config file is for the Onda VX747
+ */
+#define TARGET_TREE /* this target is using the target tree system */
+
+#define CONFIG_SDRAM_START 0x80E00000 /* HACK! */
+
+#define ONDA_VX747 1
+
+/* For Rolo and boot loader */
+#define MODEL_NUMBER 30
+
+/* define this if you use an ATA controller */
+//#define HAVE_ATA
+
+/* define this if you have a bitmap LCD display */
+#define HAVE_LCD_BITMAP
+
+/* define this if you have a colour LCD */
+#define HAVE_LCD_COLOR
+
+/* define this if you have access to the quickscreen */
+#define HAVE_QUICKSCREEN
+
+/* define this if you have access to the pitchscreen */
+#define HAVE_PITCHSCREEN
+
+/* define this if you would like tagcache to build on this target */
+#define HAVE_TAGCACHE
+
+/* define this if the target has volume keys which can be used in the lists */
+#define HAVE_VOLUME_IN_LIST
+
+/* LCD dimensions */
+#define CONFIG_LCD LCD_ONDAVX747
+
+/* choose the lcd orientation. both work */
+#define CONFIG_ORIENTATION SCREEN_PORTRAIT
+
+#define LCD_WIDTH 400
+#define LCD_HEIGHT 240
+
+#define LCD_DEPTH 16 /* 16bit colours */
+#define LCD_PIXELFORMAT RGB565 /* rgb565 */
+
+/* Define this if your LCD can be enabled/disabled */
+#define HAVE_LCD_ENABLE
+
+#define CONFIG_KEYPAD ONDAVX747_PAD
+#define HAS_BUTTON_HOLD
+//#define HAVE_HEADPHONE_DETECTION
+#define HAVE_TOUCHPAD
+#define HAVE_BUTTON_DATA
+
+/* Define this if you do software codec */
+#define CONFIG_CODEC SWCODEC
+
+/* define this if you have a real-time clock */
+//#define CONFIG_RTC RTC_RX5X348AB
+
+/* Define this for LCD backlight available */
+#define HAVE_BACKLIGHT
+
+#define HAVE_BACKLIGHT_BRIGHTNESS
+
+/* Main LCD backlight brightness range and defaults */
+#define MIN_BRIGHTNESS_SETTING 0 /* TODO */
+#define MAX_BRIGHTNESS_SETTING 127
+#define DEFAULT_BRIGHTNESS_SETTING 85
+#define DEFAULT_DIMNESS_SETTING 22
+
+/* Define this if you have a software controlled poweroff */
+//#define HAVE_SW_POWEROFF
+//TODO: enable this back
+
+/* The number of bytes reserved for loadable codecs */
+#define CODEC_SIZE 0x80000
+
+/* The number of bytes reserved for loadable plugins */
+#define PLUGIN_BUFFER_SIZE 0x100000
+
+/* Define this if you have the */
+//#define HAVE_TLV320
+
+#define CONFIG_I2C I2C_JZ47XX
+
+/* TLV320 has no tone controls, so we use the software ones */
+//#define HAVE_SW_TONE_CONTROLS
+
+/*#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \
+ SAMPR_CAP_11)*/
+
+#define BATTERY_CAPACITY_DEFAULT 1250 /* default battery capacity */
+#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */
+#define BATTERY_CAPACITY_MAX 2500 /* max. capacity selectable */
+#define BATTERY_CAPACITY_INC 100 /* capacity increment */
+#define BATTERY_TYPES_COUNT 1 /* only one type */
+
+/* Hardware controlled charging with monitoring */
+//#define CONFIG_CHARGING CHARGING_MONITOR
+
+#ifndef SIMULATOR
+
+/* Define this if you have a Ingenic JZ4732 */
+#define CONFIG_CPU JZ4732
+
+/* define this if the hardware can be powered off while charging */
+#define HAVE_POWEROFF_WHILE_CHARGING
+
+/* Define this to the CPU frequency */
+#define CPU_FREQ 16934400
+
+/* define this if you have a flash memory storage */
+#define HAVE_FLASH_STORAGE
+
+/* Virtual LED (icon) */
+#define CONFIG_LED LED_VIRTUAL
+
+/* define this if the backlight can be set to a brightness */
+#define __BACKLIGHT_INIT
+
+/* Offset ( in the firmware file's header ) to the file CRC */
+#define FIRMWARE_OFFSET_FILE_CRC 0
+
+/* Offset ( in the firmware file's header ) to the real data */
+#define FIRMWARE_OFFSET_FILE_DATA 8
+
+/* Define this if you have adjustable CPU frequency */
+/* #define HAVE_ADJUSTABLE_CPU_FREQ */
+
+#define BOOTFILE_EXT "vx747"
+#define BOOTFILE "rockbox." BOOTFILE_EXT
+#define BOOTDIR "/.rockbox"
+
+/*#define CONFIG_USBOTG USBOTG_INGENIC
+#define HAVE_USBSTACK
+#define USB_VENDOR_ID 0x041e
+#define USB_PRODUCT_ID 0x4133*/
+
+/*DEBUGGING!*/
+#ifdef BOOTLOADER
+#define THREAD_EXTRA_CHECKS 1
+#define DEBUG 1
+#define debug(msg) printf(msg)
+#endif
+
+#include <stdbool.h> /* HACKY */
+
+#endif
diff --git a/firmware/export/config.h b/firmware/export/config.h
index 265f9c8e0f..d700a15102 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -60,6 +60,7 @@
#define TCC773L 773
#define TCC7801 7801
#define S5L8700 8700
+#define JZ4732 4732
/* CONFIG_KEYPAD */
#define PLAYER_PAD 1
@@ -92,6 +93,7 @@
#define SANSA_C100_PAD 28
#define PHILIPS_HDD1630_PAD 29
#define MEIZU_M6SL_PAD 30
+#define ONDAVX747_PAD 31
/* CONFIG_REMOTE_KEYPAD */
#define H100_REMOTE 1
@@ -134,6 +136,7 @@
#define LCD_S6B33B2 26 /* as used by the Sansa c100 */
#define LCD_HDD1630 27 /* as used by the Philips HDD1630 */
#define LCD_MEIZUM6 28 /* as used by the Meizu M6SP and M6SL (various models) */
+#define LCD_ONDAVX747 29 /* as used by the Onda VX747 */
/* LCD_PIXELFORMAT */
#define HORIZONTAL_PACKING 1
@@ -162,6 +165,7 @@
#define I2C_TCC780X 11
#define I2C_DM320 12 /* DM320 style */
#define I2C_S5L8700 13
+#define I2C_JZ47XX 14 /* Ingenic Jz47XX style */
/* CONFIG_LED */
#define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */
@@ -187,12 +191,14 @@
#define RTC_MC13783 13 /* Freescale MC13783 PMIC */
#define RTC_S5L8700 14
#define RTC_S35390A 15
+#define RTC_JZ47XX 16 /* Ingenic Jz47XX */
/* USB On-the-go */
#define USBOTG_ISP1362 1362 /* iriver H300 */
#define USBOTG_ISP1583 1583 /* Creative Zen Vision:M */
#define USBOTG_M5636 5636 /* iAudio X5 */
#define USBOTG_ARC 5020 /* PortalPlayer 502x */
+#define USBOTG_JZ4740 4740 /* Ingenic Jz4740/Jz4732 */
/* Multiple cores */
#define CPU 0
@@ -283,6 +289,8 @@
#include "config-c100.h"
#elif defined(MEIZU_M6SL)
#include "config-meizu-m6sl.h"
+#elif defined(ONDA_VX747)
+#include "config-ondavx747.h"
#else
/* no known platform */
#endif
@@ -448,6 +456,10 @@
#define ROCKBOX_STRICT_ALIGN 1
#endif
+#if (CONFIG_CPU == JZ4732)
+#define CPU_MIPS 32
+#endif
+
#ifndef CODEC_SIZE
#define CODEC_SIZE 0
#endif
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h
new file mode 100755
index 0000000000..7ad10b76a6
--- /dev/null
+++ b/firmware/export/jz4740.h
@@ -0,0 +1,4902 @@
+/*
+ * Include file for Ingenic Semiconductor's JZ4740 CPU.
+ */
+#ifndef __JZ4740_H__
+#define __JZ4740_H__
+
+#ifndef __ASSEMBLY__
+
+#define cache_unroll(base,op) \
+ __asm__ __volatile__(" \
+ .set noreorder; \
+ .set mips3; \
+ cache %1, (%0); \
+ .set mips0; \
+ .set reorder" \
+ : \
+ : "r" (base), \
+ "i" (op));
+
+#define Index_Invalidate_I 0x00
+#define Index_Writeback_Inv_D 0x01
+
+#define CFG_DCACHE_SIZE 16384
+#define CFG_ICACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+
+#define KSEG0BASE 0x80003FFF /* HACK */
+
+static inline void jz_flush_dcache(void)
+{
+ unsigned long start;
+ unsigned long end;
+
+ start = KSEG0BASE;
+ end = start + CFG_DCACHE_SIZE;
+ while (start < end) {
+ cache_unroll(start,Index_Writeback_Inv_D);
+ start += CFG_CACHELINE_SIZE;
+ }
+}
+
+static inline void jz_flush_icache(void)
+{
+ unsigned long start;
+ unsigned long end;
+
+ start = KSEG0BASE;
+ end = start + CFG_ICACHE_SIZE;
+ while(start < end) {
+ cache_unroll(start,Index_Invalidate_I);
+ start += CFG_CACHELINE_SIZE;
+ }
+}
+
+/* cpu pipeline flush */
+static inline void jz_sync(void)
+{
+ __asm__ volatile ("sync");
+}
+
+#define REG8(addr) (*(volatile unsigned char *)(addr))
+#define REG16(addr) (*(volatile unsigned short *)(addr))
+#define REG32(addr) (*(volatile unsigned int *)(addr))
+
+#endif /* !ASSEMBLY */
+
+//----------------------------------------------------------------------
+// Boot ROM Specification
+//
+
+/* NOR Boot config */
+#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
+#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
+#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
+
+/* NAND Boot config */
+#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
+#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
+#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
+#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
+
+
+//----------------------------------------------------------------------
+// Register Definitions
+//
+#define CPM_BASE 0xB0000000
+#define INTC_BASE 0xB0001000
+#define TCU_BASE 0xB0002000
+#define WDT_BASE 0xB0002000
+#define RTC_BASE 0xB0003000
+#define GPIO_BASE 0xB0010000
+#define AIC_BASE 0xB0020000
+#define ICDC_BASE 0xB0020000
+#define MSC_BASE 0xB0021000
+#define UART0_BASE 0xB0030000
+#define I2C_BASE 0xB0042000
+#define SSI_BASE 0xB0043000
+#define SADC_BASE 0xB0070000
+#define EMC_BASE 0xB3010000
+#define DMAC_BASE 0xB3020000
+#define UHC_BASE 0xB3030000
+#define UDC_BASE 0xB3040000
+#define LCD_BASE 0xB3050000
+#define SLCD_BASE 0xB3050000
+#define CIM_BASE 0xB3060000
+#define ETH_BASE 0xB3100000
+
+
+/*************************************************************************
+ * INTC (Interrupt Controller)
+ *************************************************************************/
+#define INTC_ISR (INTC_BASE + 0x00)
+#define INTC_IMR (INTC_BASE + 0x04)
+#define INTC_IMSR (INTC_BASE + 0x08)
+#define INTC_IMCR (INTC_BASE + 0x0c)
+#define INTC_IPR (INTC_BASE + 0x10)
+
+#define REG_INTC_ISR REG32(INTC_ISR)
+#define REG_INTC_IMR REG32(INTC_IMR)
+#define REG_INTC_IMSR REG32(INTC_IMSR)
+#define REG_INTC_IMCR REG32(INTC_IMCR)
+#define REG_INTC_IPR REG32(INTC_IPR)
+
+// 1st-level interrupts
+#define IRQ_I2C 1
+#define IRQ_EMC 2
+#define IRQ_UHC 3
+#define IRQ_UART0 9
+#define IRQ_SADC 12
+#define IRQ_MSC 14
+#define IRQ_RTC 15
+#define IRQ_SSI 16
+#define IRQ_CIM 17
+#define IRQ_AIC 18
+#define IRQ_ETH 19
+#define IRQ_DMAC 20
+#define IRQ_TCU2 21
+#define IRQ_TCU1 22
+#define IRQ_TCU0 23
+#define IRQ_UDC 24
+#define IRQ_GPIO3 25
+#define IRQ_GPIO2 26
+#define IRQ_GPIO1 27
+#define IRQ_GPIO0 28
+#define IRQ_IPU 29
+#define IRQ_LCD 30
+
+// 2nd-level interrupts
+#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
+#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
+
+
+/*************************************************************************
+ * RTC
+ *************************************************************************/
+#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
+#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
+#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
+#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
+
+#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
+#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
+#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
+#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
+#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
+#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
+
+#define REG_RTC_RCR REG32(RTC_RCR)
+#define REG_RTC_RSR REG32(RTC_RSR)
+#define REG_RTC_RSAR REG32(RTC_RSAR)
+#define REG_RTC_RGR REG32(RTC_RGR)
+#define REG_RTC_HCR REG32(RTC_HCR)
+#define REG_RTC_HWFCR REG32(RTC_HWFCR)
+#define REG_RTC_HRCR REG32(RTC_HRCR)
+#define REG_RTC_HWCR REG32(RTC_HWCR)
+#define REG_RTC_HWRSR REG32(RTC_HWRSR)
+#define REG_RTC_HSPR REG32(RTC_HSPR)
+
+/* RTC Control Register */
+#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
+#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
+#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
+#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
+#define RTC_RCR_AF_BIT 4 /* Alarm Flag */
+#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
+#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
+#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
+
+/* RTC Regulator Register */
+#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
+#define RTC_RGR_ADJC_BIT 16
+#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
+#define RTC_RGR_NC1HZ_BIT 0
+#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
+
+/* Hibernate Control Register */
+#define RTC_HCR_PD (1 << 0) /* Power Down */
+
+/* Hibernate Wakeup Filter Counter Register */
+#define RTC_HWFCR_BIT 5
+#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
+
+/* Hibernate Reset Counter Register */
+#define RTC_HRCR_BIT 5
+#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
+
+/* Hibernate Wakeup Control Register */
+#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
+
+/* Hibernate Wakeup Status Register */
+#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
+#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
+#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
+#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
+
+
+/*************************************************************************
+ * CPM (Clock reset and Power control Management)
+ *************************************************************************/
+#define CPM_CPCCR (CPM_BASE+0x00)
+#define CPM_CPPCR (CPM_BASE+0x10)
+#define CPM_I2SCDR (CPM_BASE+0x60)
+#define CPM_LPCDR (CPM_BASE+0x64)
+#define CPM_MSCCDR (CPM_BASE+0x68)
+#define CPM_UHCCDR (CPM_BASE+0x6C)
+
+#define CPM_LCR (CPM_BASE+0x04)
+#define CPM_CLKGR (CPM_BASE+0x20)
+#define CPM_SCR (CPM_BASE+0x24)
+
+#define CPM_HCR (CPM_BASE+0x30)
+#define CPM_HWFCR (CPM_BASE+0x34)
+#define CPM_HRCR (CPM_BASE+0x38)
+#define CPM_HWCR (CPM_BASE+0x3c)
+#define CPM_HWSR (CPM_BASE+0x40)
+#define CPM_HSPR (CPM_BASE+0x44)
+
+#define CPM_RSR (CPM_BASE+0x08)
+
+
+#define REG_CPM_CPCCR REG32(CPM_CPCCR)
+#define REG_CPM_CPPCR REG32(CPM_CPPCR)
+#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
+#define REG_CPM_LPCDR REG32(CPM_LPCDR)
+#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
+#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
+
+#define REG_CPM_LCR REG32(CPM_LCR)
+#define REG_CPM_CLKGR REG32(CPM_CLKGR)
+#define REG_CPM_SCR REG32(CPM_SCR)
+#define REG_CPM_HCR REG32(CPM_HCR)
+#define REG_CPM_HWFCR REG32(CPM_HWFCR)
+#define REG_CPM_HRCR REG32(CPM_HRCR)
+#define REG_CPM_HWCR REG32(CPM_HWCR)
+#define REG_CPM_HWSR REG32(CPM_HWSR)
+#define REG_CPM_HSPR REG32(CPM_HSPR)
+
+#define REG_CPM_RSR REG32(CPM_RSR)
+
+
+/* Clock Control Register */
+#define CPM_CPCCR_I2CS (1 << 31)
+#define CPM_CPCCR_CLKOEN (1 << 30)
+#define CPM_CPCCR_UCS (1 << 29)
+#define CPM_CPCCR_UDIV_BIT 23
+#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
+#define CPM_CPCCR_CE (1 << 22)
+#define CPM_CPCCR_PCS (1 << 21)
+#define CPM_CPCCR_LDIV_BIT 16
+#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
+#define CPM_CPCCR_MDIV_BIT 12
+#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
+#define CPM_CPCCR_PDIV_BIT 8
+#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
+#define CPM_CPCCR_HDIV_BIT 4
+#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
+#define CPM_CPCCR_CDIV_BIT 0
+#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
+
+/* I2S Clock Divider Register */
+#define CPM_I2SCDR_I2SDIV_BIT 0
+#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
+
+/* LCD Pixel Clock Divider Register */
+#define CPM_LPCDR_PIXDIV_BIT 0
+#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
+
+/* MSC Clock Divider Register */
+#define CPM_MSCCDR_MSCDIV_BIT 0
+#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
+
+/* PLL Control Register */
+#define CPM_CPPCR_PLLM_BIT 23
+#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
+#define CPM_CPPCR_PLLN_BIT 18
+#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
+#define CPM_CPPCR_PLLOD_BIT 16
+#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
+#define CPM_CPPCR_PLLS (1 << 10)
+#define CPM_CPPCR_PLLBP (1 << 9)
+#define CPM_CPPCR_PLLEN (1 << 8)
+#define CPM_CPPCR_PLLST_BIT 0
+#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
+
+/* Low Power Control Register */
+#define CPM_LCR_DOZE_DUTY_BIT 3
+#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
+#define CPM_LCR_DOZE_ON (1 << 2)
+#define CPM_LCR_LPM_BIT 0
+#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
+ #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
+ #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
+
+/* Clock Gate Register */
+#define CPM_CLKGR_UART1 (1 << 15)
+#define CPM_CLKGR_UHC (1 << 14)
+#define CPM_CLKGR_IPU (1 << 13)
+#define CPM_CLKGR_DMAC (1 << 12)
+#define CPM_CLKGR_UDC (1 << 11)
+#define CPM_CLKGR_LCD (1 << 10)
+#define CPM_CLKGR_CIM (1 << 9)
+#define CPM_CLKGR_SADC (1 << 8)
+#define CPM_CLKGR_MSC (1 << 7)
+#define CPM_CLKGR_AIC1 (1 << 6)
+#define CPM_CLKGR_AIC2 (1 << 5)
+#define CPM_CLKGR_SSI (1 << 4)
+#define CPM_CLKGR_I2C (1 << 3)
+#define CPM_CLKGR_RTC (1 << 2)
+#define CPM_CLKGR_TCU (1 << 1)
+#define CPM_CLKGR_UART0 (1 << 0)
+
+/* Sleep Control Register */
+#define CPM_SCR_O1ST_BIT 8
+#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
+#define CPM_SCR_USBPHY_ENABLE (1 << 6)
+#define CPM_SCR_OSC_ENABLE (1 << 4)
+
+/* Hibernate Control Register */
+#define CPM_HCR_PD (1 << 0)
+
+/* Wakeup Filter Counter Register in Hibernate Mode */
+#define CPM_HWFCR_TIME_BIT 0
+#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
+
+/* Reset Counter Register in Hibernate Mode */
+#define CPM_HRCR_TIME_BIT 0
+#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
+
+/* Wakeup Control Register in Hibernate Mode */
+#define CPM_HWCR_WLE_LOW (0 << 2)
+#define CPM_HWCR_WLE_HIGH (1 << 2)
+#define CPM_HWCR_PIN_WAKEUP (1 << 1)
+#define CPM_HWCR_RTC_WAKEUP (1 << 0)
+
+/* Wakeup Status Register in Hibernate Mode */
+#define CPM_HWSR_WSR_PIN (1 << 1)
+#define CPM_HWSR_WSR_RTC (1 << 0)
+
+/* Reset Status Register */
+#define CPM_RSR_HR (1 << 2)
+#define CPM_RSR_WR (1 << 1)
+#define CPM_RSR_PR (1 << 0)
+
+
+/*************************************************************************
+ * TCU (Timer Counter Unit)
+ *************************************************************************/
+#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
+#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
+#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
+#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
+#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
+#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
+#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
+#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
+#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
+#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
+#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
+#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
+#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
+#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
+#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
+#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
+#define TCU_TDFR1 (TCU_BASE + 0x50)
+#define TCU_TDHR1 (TCU_BASE + 0x54)
+#define TCU_TCNT1 (TCU_BASE + 0x58)
+#define TCU_TCSR1 (TCU_BASE + 0x5C)
+#define TCU_TDFR2 (TCU_BASE + 0x60)
+#define TCU_TDHR2 (TCU_BASE + 0x64)
+#define TCU_TCNT2 (TCU_BASE + 0x68)
+#define TCU_TCSR2 (TCU_BASE + 0x6C)
+#define TCU_TDFR3 (TCU_BASE + 0x70)
+#define TCU_TDHR3 (TCU_BASE + 0x74)
+#define TCU_TCNT3 (TCU_BASE + 0x78)
+#define TCU_TCSR3 (TCU_BASE + 0x7C)
+#define TCU_TDFR4 (TCU_BASE + 0x80)
+#define TCU_TDHR4 (TCU_BASE + 0x84)
+#define TCU_TCNT4 (TCU_BASE + 0x88)
+#define TCU_TCSR4 (TCU_BASE + 0x8C)
+#define TCU_TDFR5 (TCU_BASE + 0x90)
+#define TCU_TDHR5 (TCU_BASE + 0x94)
+#define TCU_TCNT5 (TCU_BASE + 0x98)
+#define TCU_TCSR5 (TCU_BASE + 0x9C)
+
+#define REG_TCU_TSR REG32(TCU_TSR)
+#define REG_TCU_TSSR REG32(TCU_TSSR)
+#define REG_TCU_TSCR REG32(TCU_TSCR)
+#define REG_TCU_TER REG8(TCU_TER)
+#define REG_TCU_TESR REG8(TCU_TESR)
+#define REG_TCU_TECR REG8(TCU_TECR)
+#define REG_TCU_TFR REG32(TCU_TFR)
+#define REG_TCU_TFSR REG32(TCU_TFSR)
+#define REG_TCU_TFCR REG32(TCU_TFCR)
+#define REG_TCU_TMR REG32(TCU_TMR)
+#define REG_TCU_TMSR REG32(TCU_TMSR)
+#define REG_TCU_TMCR REG32(TCU_TMCR)
+#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
+#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
+#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
+#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
+#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
+#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
+#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
+#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
+#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
+#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
+#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
+#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
+#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
+#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
+#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
+#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
+#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
+#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
+#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
+#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
+
+// n = 0,1,2,3,4,5
+#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
+#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
+#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
+#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
+
+#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
+#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
+#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
+#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
+
+// Register definitions
+#define TCU_TCSR_PWM_SD (1 << 9)
+#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
+#define TCU_TCSR_PWM_EN (1 << 7)
+#define TCU_TCSR_PRESCALE_BIT 3
+#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_EXT_EN (1 << 2)
+#define TCU_TCSR_RTC_EN (1 << 1)
+#define TCU_TCSR_PCK_EN (1 << 0)
+
+#define TCU_TER_TCEN5 (1 << 5)
+#define TCU_TER_TCEN4 (1 << 4)
+#define TCU_TER_TCEN3 (1 << 3)
+#define TCU_TER_TCEN2 (1 << 2)
+#define TCU_TER_TCEN1 (1 << 1)
+#define TCU_TER_TCEN0 (1 << 0)
+
+#define TCU_TESR_TCST5 (1 << 5)
+#define TCU_TESR_TCST4 (1 << 4)
+#define TCU_TESR_TCST3 (1 << 3)
+#define TCU_TESR_TCST2 (1 << 2)
+#define TCU_TESR_TCST1 (1 << 1)
+#define TCU_TESR_TCST0 (1 << 0)
+
+#define TCU_TECR_TCCL5 (1 << 5)
+#define TCU_TECR_TCCL4 (1 << 4)
+#define TCU_TECR_TCCL3 (1 << 3)
+#define TCU_TECR_TCCL2 (1 << 2)
+#define TCU_TECR_TCCL1 (1 << 1)
+#define TCU_TECR_TCCL0 (1 << 0)
+
+#define TCU_TFR_HFLAG5 (1 << 21)
+#define TCU_TFR_HFLAG4 (1 << 20)
+#define TCU_TFR_HFLAG3 (1 << 19)
+#define TCU_TFR_HFLAG2 (1 << 18)
+#define TCU_TFR_HFLAG1 (1 << 17)
+#define TCU_TFR_HFLAG0 (1 << 16)
+#define TCU_TFR_FFLAG5 (1 << 5)
+#define TCU_TFR_FFLAG4 (1 << 4)
+#define TCU_TFR_FFLAG3 (1 << 3)
+#define TCU_TFR_FFLAG2 (1 << 2)
+#define TCU_TFR_FFLAG1 (1 << 1)
+#define TCU_TFR_FFLAG0 (1 << 0)
+
+#define TCU_TFSR_HFLAG5 (1 << 21)
+#define TCU_TFSR_HFLAG4 (1 << 20)
+#define TCU_TFSR_HFLAG3 (1 << 19)
+#define TCU_TFSR_HFLAG2 (1 << 18)
+#define TCU_TFSR_HFLAG1 (1 << 17)
+#define TCU_TFSR_HFLAG0 (1 << 16)
+#define TCU_TFSR_FFLAG5 (1 << 5)
+#define TCU_TFSR_FFLAG4 (1 << 4)
+#define TCU_TFSR_FFLAG3 (1 << 3)
+#define TCU_TFSR_FFLAG2 (1 << 2)
+#define TCU_TFSR_FFLAG1 (1 << 1)
+#define TCU_TFSR_FFLAG0 (1 << 0)
+
+#define TCU_TFCR_HFLAG5 (1 << 21)
+#define TCU_TFCR_HFLAG4 (1 << 20)
+#define TCU_TFCR_HFLAG3 (1 << 19)
+#define TCU_TFCR_HFLAG2 (1 << 18)
+#define TCU_TFCR_HFLAG1 (1 << 17)
+#define TCU_TFCR_HFLAG0 (1 << 16)
+#define TCU_TFCR_FFLAG5 (1 << 5)
+#define TCU_TFCR_FFLAG4 (1 << 4)
+#define TCU_TFCR_FFLAG3 (1 << 3)
+#define TCU_TFCR_FFLAG2 (1 << 2)
+#define TCU_TFCR_FFLAG1 (1 << 1)
+#define TCU_TFCR_FFLAG0 (1 << 0)
+
+#define TCU_TMR_HMASK5 (1 << 21)
+#define TCU_TMR_HMASK4 (1 << 20)
+#define TCU_TMR_HMASK3 (1 << 19)
+#define TCU_TMR_HMASK2 (1 << 18)
+#define TCU_TMR_HMASK1 (1 << 17)
+#define TCU_TMR_HMASK0 (1 << 16)
+#define TCU_TMR_FMASK5 (1 << 5)
+#define TCU_TMR_FMASK4 (1 << 4)
+#define TCU_TMR_FMASK3 (1 << 3)
+#define TCU_TMR_FMASK2 (1 << 2)
+#define TCU_TMR_FMASK1 (1 << 1)
+#define TCU_TMR_FMASK0 (1 << 0)
+
+#define TCU_TMSR_HMST5 (1 << 21)
+#define TCU_TMSR_HMST4 (1 << 20)
+#define TCU_TMSR_HMST3 (1 << 19)
+#define TCU_TMSR_HMST2 (1 << 18)
+#define TCU_TMSR_HMST1 (1 << 17)
+#define TCU_TMSR_HMST0 (1 << 16)
+#define TCU_TMSR_FMST5 (1 << 5)
+#define TCU_TMSR_FMST4 (1 << 4)
+#define TCU_TMSR_FMST3 (1 << 3)
+#define TCU_TMSR_FMST2 (1 << 2)
+#define TCU_TMSR_FMST1 (1 << 1)
+#define TCU_TMSR_FMST0 (1 << 0)
+
+#define TCU_TMCR_HMCL5 (1 << 21)
+#define TCU_TMCR_HMCL4 (1 << 20)
+#define TCU_TMCR_HMCL3 (1 << 19)
+#define TCU_TMCR_HMCL2 (1 << 18)
+#define TCU_TMCR_HMCL1 (1 << 17)
+#define TCU_TMCR_HMCL0 (1 << 16)
+#define TCU_TMCR_FMCL5 (1 << 5)
+#define TCU_TMCR_FMCL4 (1 << 4)
+#define TCU_TMCR_FMCL3 (1 << 3)
+#define TCU_TMCR_FMCL2 (1 << 2)
+#define TCU_TMCR_FMCL1 (1 << 1)
+#define TCU_TMCR_FMCL0 (1 << 0)
+
+#define TCU_TSR_WDTS (1 << 16)
+#define TCU_TSR_STOP5 (1 << 5)
+#define TCU_TSR_STOP4 (1 << 4)
+#define TCU_TSR_STOP3 (1 << 3)
+#define TCU_TSR_STOP2 (1 << 2)
+#define TCU_TSR_STOP1 (1 << 1)
+#define TCU_TSR_STOP0 (1 << 0)
+
+#define TCU_TSSR_WDTSS (1 << 16)
+#define TCU_TSSR_STPS5 (1 << 5)
+#define TCU_TSSR_STPS4 (1 << 4)
+#define TCU_TSSR_STPS3 (1 << 3)
+#define TCU_TSSR_STPS2 (1 << 2)
+#define TCU_TSSR_STPS1 (1 << 1)
+#define TCU_TSSR_STPS0 (1 << 0)
+
+#define TCU_TSSR_WDTSC (1 << 16)
+#define TCU_TSSR_STPC5 (1 << 5)
+#define TCU_TSSR_STPC4 (1 << 4)
+#define TCU_TSSR_STPC3 (1 << 3)
+#define TCU_TSSR_STPC2 (1 << 2)
+#define TCU_TSSR_STPC1 (1 << 1)
+#define TCU_TSSR_STPC0 (1 << 0)
+
+
+/*************************************************************************
+ * WDT (WatchDog Timer)
+ *************************************************************************/
+#define WDT_TDR (WDT_BASE + 0x00)
+#define WDT_TCER (WDT_BASE + 0x04)
+#define WDT_TCNT (WDT_BASE + 0x08)
+#define WDT_TCSR (WDT_BASE + 0x0C)
+
+#define REG_WDT_TDR REG16(WDT_TDR)
+#define REG_WDT_TCER REG8(WDT_TCER)
+#define REG_WDT_TCNT REG16(WDT_TCNT)
+#define REG_WDT_TCSR REG16(WDT_TCSR)
+
+// Register definition
+#define WDT_TCSR_PRESCALE_BIT 3
+#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
+#define WDT_TCSR_EXT_EN (1 << 2)
+#define WDT_TCSR_RTC_EN (1 << 1)
+#define WDT_TCSR_PCK_EN (1 << 0)
+
+#define WDT_TCER_TCEN (1 << 0)
+
+
+/*************************************************************************
+ * DMAC (DMA Controller)
+ *************************************************************************/
+
+#define MAX_DMA_NUM 6 /* max 6 channels */
+
+#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
+#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
+#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
+#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
+#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
+#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
+#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
+#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
+#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
+#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
+#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
+
+// channel 0
+#define DMAC_DSAR0 DMAC_DSAR(0)
+#define DMAC_DTAR0 DMAC_DTAR(0)
+#define DMAC_DTCR0 DMAC_DTCR(0)
+#define DMAC_DRSR0 DMAC_DRSR(0)
+#define DMAC_DCCSR0 DMAC_DCCSR(0)
+#define DMAC_DCMD0 DMAC_DCMD(0)
+#define DMAC_DDA0 DMAC_DDA(0)
+
+// channel 1
+#define DMAC_DSAR1 DMAC_DSAR(1)
+#define DMAC_DTAR1 DMAC_DTAR(1)
+#define DMAC_DTCR1 DMAC_DTCR(1)
+#define DMAC_DRSR1 DMAC_DRSR(1)
+#define DMAC_DCCSR1 DMAC_DCCSR(1)
+#define DMAC_DCMD1 DMAC_DCMD(1)
+#define DMAC_DDA1 DMAC_DDA(1)
+
+// channel 2
+#define DMAC_DSAR2 DMAC_DSAR(2)
+#define DMAC_DTAR2 DMAC_DTAR(2)
+#define DMAC_DTCR2 DMAC_DTCR(2)
+#define DMAC_DRSR2 DMAC_DRSR(2)
+#define DMAC_DCCSR2 DMAC_DCCSR(2)
+#define DMAC_DCMD2 DMAC_DCMD(2)
+#define DMAC_DDA2 DMAC_DDA(2)
+
+// channel 3
+#define DMAC_DSAR3 DMAC_DSAR(3)
+#define DMAC_DTAR3 DMAC_DTAR(3)
+#define DMAC_DTCR3 DMAC_DTCR(3)
+#define DMAC_DRSR3 DMAC_DRSR(3)
+#define DMAC_DCCSR3 DMAC_DCCSR(3)
+#define DMAC_DCMD3 DMAC_DCMD(3)
+#define DMAC_DDA3 DMAC_DDA(3)
+
+// channel 4
+#define DMAC_DSAR4 DMAC_DSAR(4)
+#define DMAC_DTAR4 DMAC_DTAR(4)
+#define DMAC_DTCR4 DMAC_DTCR(4)
+#define DMAC_DRSR4 DMAC_DRSR(4)
+#define DMAC_DCCSR4 DMAC_DCCSR(4)
+#define DMAC_DCMD4 DMAC_DCMD(4)
+#define DMAC_DDA4 DMAC_DDA(4)
+
+// channel 5
+#define DMAC_DSAR5 DMAC_DSAR(5)
+#define DMAC_DTAR5 DMAC_DTAR(5)
+#define DMAC_DTCR5 DMAC_DTCR(5)
+#define DMAC_DRSR5 DMAC_DRSR(5)
+#define DMAC_DCCSR5 DMAC_DCCSR(5)
+#define DMAC_DCMD5 DMAC_DCMD(5)
+#define DMAC_DDA5 DMAC_DDA(5)
+
+#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
+#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
+#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
+#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
+#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
+#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
+#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
+#define REG_DMAC_DMACR REG32(DMAC_DMACR)
+#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
+#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
+#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
+
+// DMA request source register
+#define DMAC_DRSR_RS_BIT 0
+#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
+ #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
+
+// DMA channel control/status register
+#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
+#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
+#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
+#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
+#define DMAC_DCCSR_AR (1 << 4) /* address error */
+#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
+#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
+#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
+#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
+
+// DMA channel command register
+#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
+#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
+#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
+#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
+ #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
+#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
+#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
+ #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
+ #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
+ #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
+#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
+#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
+ #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
+ #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
+ #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
+#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
+#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
+ #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
+ #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
+ #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
+ #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
+ #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
+#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
+#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
+#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
+#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
+#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
+#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
+
+// DMA descriptor address register
+#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
+#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
+#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
+#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
+
+// DMA control register
+#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
+#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
+ #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
+ #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
+ #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
+ #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
+#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
+#define DMAC_DMACR_AR (1 << 2) /* address error flag */
+#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
+
+// DMA doorbell register
+#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
+#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
+#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
+#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
+#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
+#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
+
+// DMA doorbell set register
+#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
+#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
+#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
+#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
+#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
+#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
+
+// DMA interrupt pending register
+#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
+#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
+#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
+#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
+#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
+#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
+
+
+/*************************************************************************
+ * GPIO (General-Purpose I/O Ports)
+ *************************************************************************/
+#define MAX_GPIO_NUM 128
+
+//n = 0,1,2,3
+#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
+#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
+#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
+#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
+#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
+#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
+#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
+#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
+#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
+#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
+#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
+#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
+#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
+#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
+#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
+#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
+#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
+#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
+#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
+#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
+#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
+#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
+#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
+#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
+
+#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
+#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
+#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
+#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
+#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
+#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
+#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
+#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
+#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
+#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
+#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
+#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
+#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
+#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
+#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
+#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
+#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
+#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
+#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
+#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
+#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
+#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
+#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
+#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
+
+
+/*************************************************************************
+ * UART
+ *************************************************************************/
+
+#define IRDA_BASE UART0_BASE
+#define UART_BASE UART0_BASE
+#define UART_OFF 0x1000
+
+/* Register Offset */
+#define OFF_RDR (0x00) /* R 8b H'xx */
+#define OFF_TDR (0x00) /* W 8b H'xx */
+#define OFF_DLLR (0x00) /* RW 8b H'00 */
+#define OFF_DLHR (0x04) /* RW 8b H'00 */
+#define OFF_IER (0x04) /* RW 8b H'00 */
+#define OFF_ISR (0x08) /* R 8b H'01 */
+#define OFF_FCR (0x08) /* W 8b H'00 */
+#define OFF_LCR (0x0C) /* RW 8b H'00 */
+#define OFF_MCR (0x10) /* RW 8b H'00 */
+#define OFF_LSR (0x14) /* R 8b H'00 */
+#define OFF_MSR (0x18) /* R 8b H'00 */
+#define OFF_SPR (0x1C) /* RW 8b H'00 */
+#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
+#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
+#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
+
+/* Register Address */
+#define UART0_RDR (UART0_BASE + OFF_RDR)
+#define UART0_TDR (UART0_BASE + OFF_TDR)
+#define UART0_DLLR (UART0_BASE + OFF_DLLR)
+#define UART0_DLHR (UART0_BASE + OFF_DLHR)
+#define UART0_IER (UART0_BASE + OFF_IER)
+#define UART0_ISR (UART0_BASE + OFF_ISR)
+#define UART0_FCR (UART0_BASE + OFF_FCR)
+#define UART0_LCR (UART0_BASE + OFF_LCR)
+#define UART0_MCR (UART0_BASE + OFF_MCR)
+#define UART0_LSR (UART0_BASE + OFF_LSR)
+#define UART0_MSR (UART0_BASE + OFF_MSR)
+#define UART0_SPR (UART0_BASE + OFF_SPR)
+#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
+#define UART0_UMR (UART0_BASE + OFF_UMR)
+#define UART0_UACR (UART0_BASE + OFF_UACR)
+
+/*
+ * Define macros for UART_IER
+ * UART Interrupt Enable Register
+ */
+#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
+#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
+#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
+#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
+#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
+
+/*
+ * Define macros for UART_ISR
+ * UART Interrupt Status Register
+ */
+#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
+#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
+#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
+#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
+#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
+#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
+#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
+#define UART_ISR_FFMS_NO_FIFO (0 << 6)
+#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
+
+/*
+ * Define macros for UART_FCR
+ * UART FIFO Control Register
+ */
+#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
+#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
+#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
+#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
+#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
+#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
+#define UART_FCR_RTRG_1 (0 << 6)
+#define UART_FCR_RTRG_4 (1 << 6)
+#define UART_FCR_RTRG_8 (2 << 6)
+#define UART_FCR_RTRG_15 (3 << 6)
+
+/*
+ * Define macros for UART_LCR
+ * UART Line Control Register
+ */
+#define UART_LCR_WLEN (3 << 0) /* word length */
+#define UART_LCR_WLEN_5 (0 << 0)
+#define UART_LCR_WLEN_6 (1 << 0)
+#define UART_LCR_WLEN_7 (2 << 0)
+#define UART_LCR_WLEN_8 (3 << 0)
+#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
+ 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
+#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
+ 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
+#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
+ 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
+
+#define UART_LCR_PE (1 << 3) /* 0: parity disable */
+#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
+#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
+#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
+#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
+
+/*
+ * Define macros for UART_LSR
+ * UART Line Status Register
+ */
+#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
+#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
+#define UART_LSR_PER (1 << 2) /* 0: no parity error */
+#define UART_LSR_FER (1 << 3) /* 0; no framing error */
+#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
+#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
+#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
+#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
+
+/*
+ * Define macros for UART_MCR
+ * UART Modem Control Register
+ */
+#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
+#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
+#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
+#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
+#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
+#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
+
+/*
+ * Define macros for UART_MSR
+ * UART Modem Status Register
+ */
+#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
+#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
+#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
+#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
+#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
+#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
+#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
+#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
+
+/*
+ * Define macros for SIRCR
+ * Slow IrDA Control Register
+ */
+#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
+#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
+#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
+ 1: 0 pulse width is 1.6us for 115.2Kbps */
+#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
+#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
+
+
+/*************************************************************************
+ * AIC (AC97/I2S Controller)
+ *************************************************************************/
+#define AIC_FR (AIC_BASE + 0x000)
+#define AIC_CR (AIC_BASE + 0x004)
+#define AIC_ACCR1 (AIC_BASE + 0x008)
+#define AIC_ACCR2 (AIC_BASE + 0x00C)
+#define AIC_I2SCR (AIC_BASE + 0x010)
+#define AIC_SR (AIC_BASE + 0x014)
+#define AIC_ACSR (AIC_BASE + 0x018)
+#define AIC_I2SSR (AIC_BASE + 0x01C)
+#define AIC_ACCAR (AIC_BASE + 0x020)
+#define AIC_ACCDR (AIC_BASE + 0x024)
+#define AIC_ACSAR (AIC_BASE + 0x028)
+#define AIC_ACSDR (AIC_BASE + 0x02C)
+#define AIC_I2SDIV (AIC_BASE + 0x030)
+#define AIC_DR (AIC_BASE + 0x034)
+
+#define REG_AIC_FR REG32(AIC_FR)
+#define REG_AIC_CR REG32(AIC_CR)
+#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
+#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
+#define REG_AIC_I2SCR REG32(AIC_I2SCR)
+#define REG_AIC_SR REG32(AIC_SR)
+#define REG_AIC_ACSR REG32(AIC_ACSR)
+#define REG_AIC_I2SSR REG32(AIC_I2SSR)
+#define REG_AIC_ACCAR REG32(AIC_ACCAR)
+#define REG_AIC_ACCDR REG32(AIC_ACCDR)
+#define REG_AIC_ACSAR REG32(AIC_ACSAR)
+#define REG_AIC_ACSDR REG32(AIC_ACSDR)
+#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
+#define REG_AIC_DR REG32(AIC_DR)
+
+/* AIC Controller Configuration Register (AIC_FR) */
+
+#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
+#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
+#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
+#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
+#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
+#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
+#define AIC_FR_RST (1 << 3) /* AIC registers reset */
+#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
+#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
+#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
+
+/* AIC Controller Common Control Register (AIC_CR) */
+
+#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
+#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
+ #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
+ #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
+ #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
+ #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
+ #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
+#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
+#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
+ #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
+ #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
+ #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
+ #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
+ #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
+#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
+#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
+#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
+#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
+#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
+#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
+#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
+#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
+#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
+#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
+#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
+#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
+#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
+
+/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
+
+#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
+#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
+ #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
+ #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
+ #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
+ #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
+ #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
+ #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
+ #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
+ #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
+ #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
+ #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
+#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
+#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
+ #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
+ #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
+ #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
+ #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
+ #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
+ #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
+ #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
+ #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
+ #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
+ #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
+
+/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
+
+#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
+#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
+#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
+#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
+#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
+ #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
+ #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
+ #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
+ #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
+#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
+#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
+ #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
+ #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
+ #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
+ #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
+#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
+#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
+#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
+#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
+
+/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
+
+#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
+#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
+#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
+ #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
+ #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
+ #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
+ #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
+ #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
+#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
+
+/* AIC Controller FIFO Status Register (AIC_SR) */
+
+#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
+#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
+#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
+#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
+#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
+#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
+#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
+#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
+
+/* AIC Controller AC-link Status Register (AIC_ACSR) */
+
+#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
+#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
+#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
+#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
+#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
+#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
+
+/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
+
+#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
+
+/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
+
+#define AIC_ACCAR_CAR_BIT 0
+#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
+
+/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
+
+#define AIC_ACCDR_CDR_BIT 0
+#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
+
+/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
+
+#define AIC_ACSAR_SAR_BIT 0
+#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
+
+/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
+
+#define AIC_ACSDR_SDR_BIT 0
+#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
+
+/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
+
+#define AIC_I2SDIV_DIV_BIT 0
+#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
+ #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
+ #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
+ #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
+ #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
+ #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
+ #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
+
+
+/*************************************************************************
+ * ICDC (Internal CODEC)
+ *************************************************************************/
+#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
+#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
+#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
+#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
+#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
+#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
+#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
+
+#define REG_ICDC_CR REG32(ICDC_CR)
+#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
+#define REG_ICDC_APPRE REG32(ICDC_APPRE)
+#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
+#define REG_ICDC_APSR REG32(ICDC_APSR)
+#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
+#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
+
+/* ICDC Control Register */
+#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
+#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
+#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
+#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
+ #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
+#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
+#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
+ #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
+ #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
+ #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
+ #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
+#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
+#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
+ #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
+ #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
+ #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
+ #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
+#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
+#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
+#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
+#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
+#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
+#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
+#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
+#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
+#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
+#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
+#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
+#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
+
+/* Anti-Pop WAIT Stage Timing Control Register */
+#define ICDC_APWAIT_WAITSN_BIT 0
+#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
+
+/* Anti-Pop HPEN-PRE Stage Timing Control Register */
+#define ICDC_APPRE_PRESN_BIT 0
+#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
+
+/* Anti-Pop HPEN Stage Timing Control Register */
+#define ICDC_APHPEN_HPENSN_BIT 0
+#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
+
+/* Anti-Pop Status Register */
+#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
+#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
+#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
+#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
+ #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
+#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
+ #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
+ #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
+ #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
+ #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
+#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
+#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
+
+
+/*************************************************************************
+ * I2C
+ *************************************************************************/
+#define I2C_DR (I2C_BASE + 0x000)
+#define I2C_CR (I2C_BASE + 0x004)
+#define I2C_SR (I2C_BASE + 0x008)
+#define I2C_GR (I2C_BASE + 0x00C)
+
+#define REG_I2C_DR REG8(I2C_DR)
+#define REG_I2C_CR REG8(I2C_CR)
+#define REG_I2C_SR REG8(I2C_SR)
+#define REG_I2C_GR REG16(I2C_GR)
+
+/* I2C Control Register (I2C_CR) */
+
+#define I2C_CR_IEN (1 << 4)
+#define I2C_CR_STA (1 << 3)
+#define I2C_CR_STO (1 << 2)
+#define I2C_CR_AC (1 << 1)
+#define I2C_CR_I2CE (1 << 0)
+
+/* I2C Status Register (I2C_SR) */
+
+#define I2C_SR_STX (1 << 4)
+#define I2C_SR_BUSY (1 << 3)
+#define I2C_SR_TEND (1 << 2)
+#define I2C_SR_DRF (1 << 1)
+#define I2C_SR_ACKF (1 << 0)
+
+
+/*************************************************************************
+ * SSI
+ *************************************************************************/
+#define SSI_DR (SSI_BASE + 0x000)
+#define SSI_CR0 (SSI_BASE + 0x004)
+#define SSI_CR1 (SSI_BASE + 0x008)
+#define SSI_SR (SSI_BASE + 0x00C)
+#define SSI_ITR (SSI_BASE + 0x010)
+#define SSI_ICR (SSI_BASE + 0x014)
+#define SSI_GR (SSI_BASE + 0x018)
+
+#define REG_SSI_DR REG32(SSI_DR)
+#define REG_SSI_CR0 REG16(SSI_CR0)
+#define REG_SSI_CR1 REG32(SSI_CR1)
+#define REG_SSI_SR REG32(SSI_SR)
+#define REG_SSI_ITR REG16(SSI_ITR)
+#define REG_SSI_ICR REG8(SSI_ICR)
+#define REG_SSI_GR REG16(SSI_GR)
+
+/* SSI Data Register (SSI_DR) */
+
+#define SSI_DR_GPC_BIT 0
+#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
+
+/* SSI Control Register 0 (SSI_CR0) */
+
+#define SSI_CR0_SSIE (1 << 15)
+#define SSI_CR0_TIE (1 << 14)
+#define SSI_CR0_RIE (1 << 13)
+#define SSI_CR0_TEIE (1 << 12)
+#define SSI_CR0_REIE (1 << 11)
+#define SSI_CR0_LOOP (1 << 10)
+#define SSI_CR0_RFINE (1 << 9)
+#define SSI_CR0_RFINC (1 << 8)
+#define SSI_CR0_FSEL (1 << 6)
+#define SSI_CR0_TFLUSH (1 << 2)
+#define SSI_CR0_RFLUSH (1 << 1)
+#define SSI_CR0_DISREV (1 << 0)
+
+/* SSI Control Register 1 (SSI_CR1) */
+
+#define SSI_CR1_FRMHL_BIT 30
+#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
+ #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
+ #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
+ #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
+ #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
+#define SSI_CR1_TFVCK_BIT 28
+#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
+ #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
+ #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
+ #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
+ #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
+#define SSI_CR1_TCKFI_BIT 26
+#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
+ #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
+ #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
+ #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
+ #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
+#define SSI_CR1_LFST (1 << 25)
+#define SSI_CR1_ITFRM (1 << 24)
+#define SSI_CR1_UNFIN (1 << 23)
+#define SSI_CR1_MULTS (1 << 22)
+#define SSI_CR1_FMAT_BIT 20
+#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
+ #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
+ #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
+ #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
+ #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
+#define SSI_CR1_TTRG_BIT 16
+#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
+ #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
+#define SSI_CR1_MCOM_BIT 12
+#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
+ #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
+ #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
+ #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
+ #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
+ #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
+ #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
+ #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
+ #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
+ #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
+ #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
+ #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
+ #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
+ #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
+ #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
+ #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
+ #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
+#define SSI_CR1_RTRG_BIT 8
+#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
+ #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
+#define SSI_CR1_FLEN_BIT 4
+#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
+ #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
+#define SSI_CR1_PHA (1 << 1)
+#define SSI_CR1_POL (1 << 0)
+
+/* SSI Status Register (SSI_SR) */
+
+#define SSI_SR_TFIFONUM_BIT 16
+#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
+#define SSI_SR_RFIFONUM_BIT 8
+#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
+#define SSI_SR_END (1 << 7)
+#define SSI_SR_BUSY (1 << 6)
+#define SSI_SR_TFF (1 << 5)
+#define SSI_SR_RFE (1 << 4)
+#define SSI_SR_TFHE (1 << 3)
+#define SSI_SR_RFHF (1 << 2)
+#define SSI_SR_UNDR (1 << 1)
+#define SSI_SR_OVER (1 << 0)
+
+/* SSI Interval Time Control Register (SSI_ITR) */
+
+#define SSI_ITR_CNTCLK (1 << 15)
+#define SSI_ITR_IVLTM_BIT 0
+#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
+
+
+/*************************************************************************
+ * MSC
+ *************************************************************************/
+#define MSC_STRPCL (MSC_BASE + 0x000)
+#define MSC_STAT (MSC_BASE + 0x004)
+#define MSC_CLKRT (MSC_BASE + 0x008)
+#define MSC_CMDAT (MSC_BASE + 0x00C)
+#define MSC_RESTO (MSC_BASE + 0x010)
+#define MSC_RDTO (MSC_BASE + 0x014)
+#define MSC_BLKLEN (MSC_BASE + 0x018)
+#define MSC_NOB (MSC_BASE + 0x01C)
+#define MSC_SNOB (MSC_BASE + 0x020)
+#define MSC_IMASK (MSC_BASE + 0x024)
+#define MSC_IREG (MSC_BASE + 0x028)
+#define MSC_CMD (MSC_BASE + 0x02C)
+#define MSC_ARG (MSC_BASE + 0x030)
+#define MSC_RES (MSC_BASE + 0x034)
+#define MSC_RXFIFO (MSC_BASE + 0x038)
+#define MSC_TXFIFO (MSC_BASE + 0x03C)
+
+#define REG_MSC_STRPCL REG16(MSC_STRPCL)
+#define REG_MSC_STAT REG32(MSC_STAT)
+#define REG_MSC_CLKRT REG16(MSC_CLKRT)
+#define REG_MSC_CMDAT REG32(MSC_CMDAT)
+#define REG_MSC_RESTO REG16(MSC_RESTO)
+#define REG_MSC_RDTO REG16(MSC_RDTO)
+#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
+#define REG_MSC_NOB REG16(MSC_NOB)
+#define REG_MSC_SNOB REG16(MSC_SNOB)
+#define REG_MSC_IMASK REG16(MSC_IMASK)
+#define REG_MSC_IREG REG16(MSC_IREG)
+#define REG_MSC_CMD REG8(MSC_CMD)
+#define REG_MSC_ARG REG32(MSC_ARG)
+#define REG_MSC_RES REG16(MSC_RES)
+#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
+#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+
+#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
+#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
+#define MSC_STRPCL_START_READWAIT (1 << 5)
+#define MSC_STRPCL_STOP_READWAIT (1 << 4)
+#define MSC_STRPCL_RESET (1 << 3)
+#define MSC_STRPCL_START_OP (1 << 2)
+#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
+#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
+ #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
+ #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
+
+/* MSC Status Register (MSC_STAT) */
+
+#define MSC_STAT_IS_RESETTING (1 << 15)
+#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
+#define MSC_STAT_PRG_DONE (1 << 13)
+#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
+#define MSC_STAT_END_CMD_RES (1 << 11)
+#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
+#define MSC_STAT_IS_READWAIT (1 << 9)
+#define MSC_STAT_CLK_EN (1 << 8)
+#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
+#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
+#define MSC_STAT_CRC_RES_ERR (1 << 5)
+#define MSC_STAT_CRC_READ_ERROR (1 << 4)
+#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
+#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
+ #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
+ #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
+ #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
+#define MSC_STAT_TIME_OUT_RES (1 << 1)
+#define MSC_STAT_TIME_OUT_READ (1 << 0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+
+#define MSC_CLKRT_CLK_RATE_BIT 0
+#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
+ #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
+ #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
+ #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
+ #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
+ #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
+ #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
+ #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
+ #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+
+#define MSC_CMDAT_IO_ABORT (1 << 11)
+#define MSC_CMDAT_BUS_WIDTH_BIT 9
+#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
+ #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
+ #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
+ #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
+ #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
+#define MSC_CMDAT_DMA_EN (1 << 8)
+#define MSC_CMDAT_INIT (1 << 7)
+#define MSC_CMDAT_BUSY (1 << 6)
+#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
+#define MSC_CMDAT_WRITE (1 << 4)
+#define MSC_CMDAT_READ (0 << 4)
+#define MSC_CMDAT_DATA_EN (1 << 3)
+#define MSC_CMDAT_RESPONSE_BIT 0
+#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
+ #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
+ #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
+ #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
+ #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
+ #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
+ #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
+ #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
+
+#define CMDAT_DMA_EN (1 << 8)
+#define CMDAT_INIT (1 << 7)
+#define CMDAT_BUSY (1 << 6)
+#define CMDAT_STREAM (1 << 5)
+#define CMDAT_WRITE (1 << 4)
+#define CMDAT_DATA_EN (1 << 3)
+
+/* MSC Interrupts Mask Register (MSC_IMASK) */
+
+#define MSC_IMASK_SDIO (1 << 7)
+#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
+#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
+#define MSC_IMASK_END_CMD_RES (1 << 2)
+#define MSC_IMASK_PRG_DONE (1 << 1)
+#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
+
+
+/* MSC Interrupts Status Register (MSC_IREG) */
+
+#define MSC_IREG_SDIO (1 << 7)
+#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
+#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
+#define MSC_IREG_END_CMD_RES (1 << 2)
+#define MSC_IREG_PRG_DONE (1 << 1)
+#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
+
+
+/*************************************************************************
+ * EMC (External Memory Controller)
+ *************************************************************************/
+#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
+
+#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
+#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
+#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
+#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
+#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
+#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
+#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
+#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
+#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
+#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
+
+#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
+#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
+#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
+#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
+#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
+#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
+#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
+#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
+#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
+#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
+#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
+#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
+
+#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
+#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
+#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
+#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
+#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
+#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
+
+#define REG_EMC_BCR REG32(EMC_BCR)
+
+#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
+#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
+#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
+#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
+#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
+#define REG_EMC_SACR0 REG32(EMC_SACR0)
+#define REG_EMC_SACR1 REG32(EMC_SACR1)
+#define REG_EMC_SACR2 REG32(EMC_SACR2)
+#define REG_EMC_SACR3 REG32(EMC_SACR3)
+#define REG_EMC_SACR4 REG32(EMC_SACR4)
+
+#define REG_EMC_NFCSR REG32(EMC_NFCSR)
+#define REG_EMC_NFECR REG32(EMC_NFECR)
+#define REG_EMC_NFECC REG32(EMC_NFECC)
+#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
+#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
+#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
+#define REG_EMC_NFINTS REG32(EMC_NFINTS)
+#define REG_EMC_NFINTE REG32(EMC_NFINTE)
+#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
+#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
+#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
+#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
+
+#define REG_EMC_DMCR REG32(EMC_DMCR)
+#define REG_EMC_RTCSR REG16(EMC_RTCSR)
+#define REG_EMC_RTCNT REG16(EMC_RTCNT)
+#define REG_EMC_RTCOR REG16(EMC_RTCOR)
+#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
+
+/* Static Memory Control Register */
+#define EMC_SMCR_STRV_BIT 24
+#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
+#define EMC_SMCR_TAW_BIT 20
+#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
+#define EMC_SMCR_TBP_BIT 16
+#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
+#define EMC_SMCR_TAH_BIT 12
+#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
+#define EMC_SMCR_TAS_BIT 8
+#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
+#define EMC_SMCR_BW_BIT 6
+#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
+ #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
+ #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
+ #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
+#define EMC_SMCR_BCM (1 << 3)
+#define EMC_SMCR_BL_BIT 1
+#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
+ #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
+ #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
+ #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
+ #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
+#define EMC_SMCR_SMT (1 << 0)
+
+/* Static Memory Bank Addr Config Reg */
+#define EMC_SACR_BASE_BIT 8
+#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
+#define EMC_SACR_MASK_BIT 0
+#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
+
+/* NAND Flash Control/Status Register */
+#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
+#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
+#define EMC_NFCSR_NFCE3 (1 << 5)
+#define EMC_NFCSR_NFE3 (1 << 4)
+#define EMC_NFCSR_NFCE2 (1 << 3)
+#define EMC_NFCSR_NFE2 (1 << 2)
+#define EMC_NFCSR_NFCE1 (1 << 1)
+#define EMC_NFCSR_NFE1 (1 << 0)
+
+/* NAND Flash ECC Control Register */
+#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
+#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
+#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
+#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
+#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
+#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
+#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
+
+/* NAND Flash ECC Data Register */
+#define EMC_NFECC_ECC2_BIT 16
+#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
+#define EMC_NFECC_ECC1_BIT 8
+#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
+#define EMC_NFECC_ECC0_BIT 0
+#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
+
+/* NAND Flash Interrupt Status Register */
+#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
+#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
+#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
+#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
+#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
+#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
+#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
+
+/* NAND Flash Interrupt Enable Register */
+#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
+#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
+#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
+#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
+#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
+
+/* NAND Flash RS Error Report Register */
+#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
+#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
+#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
+#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
+
+
+/* DRAM Control Register */
+#define EMC_DMCR_BW_BIT 31
+#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
+#define EMC_DMCR_CA_BIT 26
+#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
+ #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
+ #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
+ #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
+ #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
+ #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
+#define EMC_DMCR_RMODE (1 << 25)
+#define EMC_DMCR_RFSH (1 << 24)
+#define EMC_DMCR_MRSET (1 << 23)
+#define EMC_DMCR_RA_BIT 20
+#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
+ #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
+ #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
+ #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
+#define EMC_DMCR_BA_BIT 19
+#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
+#define EMC_DMCR_PDM (1 << 18)
+#define EMC_DMCR_EPIN (1 << 17)
+#define EMC_DMCR_TRAS_BIT 13
+#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
+#define EMC_DMCR_RCD_BIT 11
+#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
+#define EMC_DMCR_TPC_BIT 8
+#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
+#define EMC_DMCR_TRWL_BIT 5
+#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
+#define EMC_DMCR_TRC_BIT 2
+#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
+#define EMC_DMCR_TCL_BIT 0
+#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
+
+/* Refresh Time Control/Status Register */
+#define EMC_RTCSR_CMF (1 << 7)
+#define EMC_RTCSR_CKS_BIT 0
+#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
+ #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
+ #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
+ #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
+ #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
+ #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
+ #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
+ #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
+ #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
+
+/* SDRAM Bank Address Configuration Register */
+#define EMC_DMAR_BASE_BIT 8
+#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
+#define EMC_DMAR_MASK_BIT 0
+#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
+
+/* Mode Register of SDRAM bank 0 */
+#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
+#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
+#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
+ #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
+#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
+#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
+ #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
+ #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
+ #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
+#define EMC_SDMR_BT_BIT 3 /* Burst Type */
+#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
+ #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
+ #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
+#define EMC_SDMR_BL_BIT 0 /* Burst Length */
+#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
+ #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
+ #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
+ #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
+ #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
+
+#define EMC_SDMR_CAS2_16BIT \
+ (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
+#define EMC_SDMR_CAS2_32BIT \
+ (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
+#define EMC_SDMR_CAS3_16BIT \
+ (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
+#define EMC_SDMR_CAS3_32BIT \
+ (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
+
+
+/*************************************************************************
+ * CIM
+ *************************************************************************/
+#define CIM_CFG (CIM_BASE + 0x0000)
+#define CIM_CTRL (CIM_BASE + 0x0004)
+#define CIM_STATE (CIM_BASE + 0x0008)
+#define CIM_IID (CIM_BASE + 0x000C)
+#define CIM_RXFIFO (CIM_BASE + 0x0010)
+#define CIM_DA (CIM_BASE + 0x0020)
+#define CIM_FA (CIM_BASE + 0x0024)
+#define CIM_FID (CIM_BASE + 0x0028)
+#define CIM_CMD (CIM_BASE + 0x002C)
+
+#define REG_CIM_CFG REG32(CIM_CFG)
+#define REG_CIM_CTRL REG32(CIM_CTRL)
+#define REG_CIM_STATE REG32(CIM_STATE)
+#define REG_CIM_IID REG32(CIM_IID)
+#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
+#define REG_CIM_DA REG32(CIM_DA)
+#define REG_CIM_FA REG32(CIM_FA)
+#define REG_CIM_FID REG32(CIM_FID)
+#define REG_CIM_CMD REG32(CIM_CMD)
+
+/* CIM Configuration Register (CIM_CFG) */
+
+#define CIM_CFG_INV_DAT (1 << 15)
+#define CIM_CFG_VSP (1 << 14)
+#define CIM_CFG_HSP (1 << 13)
+#define CIM_CFG_PCP (1 << 12)
+#define CIM_CFG_DUMMY_ZERO (1 << 9)
+#define CIM_CFG_EXT_VSYNC (1 << 8)
+#define CIM_CFG_PACK_BIT 4
+#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
+ #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
+ #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
+ #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
+ #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
+ #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
+ #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
+ #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
+ #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
+#define CIM_CFG_DSM_BIT 0
+#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
+ #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
+ #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
+ #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
+ #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
+
+/* CIM Control Register (CIM_CTRL) */
+
+#define CIM_CTRL_MCLKDIV_BIT 24
+#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
+#define CIM_CTRL_FRC_BIT 16
+#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
+ #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
+ #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
+ #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
+ #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
+ #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
+ #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
+ #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
+ #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
+ #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
+ #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
+ #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
+ #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
+ #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
+ #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
+ #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
+ #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
+#define CIM_CTRL_VDDM (1 << 13)
+#define CIM_CTRL_DMA_SOFM (1 << 12)
+#define CIM_CTRL_DMA_EOFM (1 << 11)
+#define CIM_CTRL_DMA_STOPM (1 << 10)
+#define CIM_CTRL_RXF_TRIGM (1 << 9)
+#define CIM_CTRL_RXF_OFM (1 << 8)
+#define CIM_CTRL_RXF_TRIG_BIT 4
+#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
+ #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
+ #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
+ #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
+ #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
+ #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
+ #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
+ #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
+ #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
+#define CIM_CTRL_DMA_EN (1 << 2)
+#define CIM_CTRL_RXF_RST (1 << 1)
+#define CIM_CTRL_ENA (1 << 0)
+
+/* CIM State Register (CIM_STATE) */
+
+#define CIM_STATE_DMA_SOF (1 << 6)
+#define CIM_STATE_DMA_EOF (1 << 5)
+#define CIM_STATE_DMA_STOP (1 << 4)
+#define CIM_STATE_RXF_OF (1 << 3)
+#define CIM_STATE_RXF_TRIG (1 << 2)
+#define CIM_STATE_RXF_EMPTY (1 << 1)
+#define CIM_STATE_VDD (1 << 0)
+
+/* CIM DMA Command Register (CIM_CMD) */
+
+#define CIM_CMD_SOFINT (1 << 31)
+#define CIM_CMD_EOFINT (1 << 30)
+#define CIM_CMD_STOP (1 << 28)
+#define CIM_CMD_LEN_BIT 0
+#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
+
+
+/*************************************************************************
+ * SADC (Smart A/D Controller)
+ *************************************************************************/
+
+#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
+#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
+#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
+#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
+#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
+#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
+#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
+#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
+#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
+
+#define REG_SADC_ENA REG8(SADC_ENA)
+#define REG_SADC_CFG REG32(SADC_CFG)
+#define REG_SADC_CTRL REG8(SADC_CTRL)
+#define REG_SADC_STATE REG8(SADC_STATE)
+#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
+#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
+#define REG_SADC_TSDAT REG32(SADC_TSDAT)
+#define REG_SADC_BATDAT REG16(SADC_BATDAT)
+#define REG_SADC_SADDAT REG16(SADC_SADDAT)
+
+/* ADC Enable Register */
+#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
+#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
+#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
+#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
+
+/* ADC Configure Register */
+#define SADC_CFG_CLKOUT_NUM_BIT 16
+#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
+#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
+#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
+#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
+ #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
+ #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
+ #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
+#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
+#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
+ #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
+ #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
+ #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
+ #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
+ #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
+ #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
+ #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
+ #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
+#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
+#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
+#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
+#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
+#define SADC_CFG_CMD_BIT 0 /* ADC Command */
+#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
+ #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
+ #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
+ #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
+ #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
+ #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
+ #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
+ #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
+ #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
+ #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
+ #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
+ #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
+ #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
+ #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
+
+/* ADC Control Register */
+#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
+#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
+#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
+#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
+#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
+
+/* ADC Status Register */
+#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
+#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
+#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
+#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
+#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
+#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
+#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
+#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
+
+/* ADC Touch Screen Data Register */
+#define SADC_TSDAT_DATA0_BIT 0
+#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
+#define SADC_TSDAT_TYPE0 (1 << 15)
+#define SADC_TSDAT_DATA1_BIT 16
+#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
+#define SADC_TSDAT_TYPE1 (1 << 31)
+
+
+/*************************************************************************
+ * SLCD (Smart LCD Controller)
+ *************************************************************************/
+
+#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
+#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
+#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
+#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
+#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
+
+#define REG_SLCD_CFG REG32(SLCD_CFG)
+#define REG_SLCD_CTRL REG8(SLCD_CTRL)
+#define REG_SLCD_STATE REG8(SLCD_STATE)
+#define REG_SLCD_DATA REG32(SLCD_DATA)
+#define REG_SLCD_FIFO REG32(SLCD_FIFO)
+
+/* SLCD Configure Register */
+#define SLCD_CFG_BURST_BIT 14
+#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
+ #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
+ #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
+#define SLCD_CFG_DWIDTH_BIT 10
+#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
+ #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
+ #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
+ #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
+ #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
+ #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
+ #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT)
+#define SLCD_CFG_CWIDTH_BIT 8
+#define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT)
+ #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT)
+ #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT)
+ #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT)
+#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
+#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
+#define SLCD_CFG_RS_CMD_LOW (0 << 3)
+#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
+#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
+#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
+#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
+#define SLCD_CFG_TYPE_SERIAL (1 << 0)
+
+/* SLCD Control Register */
+#define SLCD_CTRL_DMA_EN (1 << 0)
+
+/* SLCD Status Register */
+#define SLCD_STATE_BUSY (1 << 0)
+
+/* SLCD Data Register */
+#define SLCD_DATA_RS_DATA (0 << 31)
+#define SLCD_DATA_RS_COMMAND (1 << 31)
+
+/* SLCD FIFO Register */
+#define SLCD_FIFO_RS_DATA (0 << 31)
+#define SLCD_FIFO_RS_COMMAND (1 << 31)
+
+
+/*************************************************************************
+ * LCD (LCD Controller)
+ *************************************************************************/
+#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
+#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
+#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
+#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
+#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
+#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
+#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
+#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
+#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
+#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
+#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
+#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
+#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
+#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
+#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
+#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
+#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
+#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
+#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
+#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
+#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
+
+#define REG_LCD_CFG REG32(LCD_CFG)
+#define REG_LCD_VSYNC REG32(LCD_VSYNC)
+#define REG_LCD_HSYNC REG32(LCD_HSYNC)
+#define REG_LCD_VAT REG32(LCD_VAT)
+#define REG_LCD_DAH REG32(LCD_DAH)
+#define REG_LCD_DAV REG32(LCD_DAV)
+#define REG_LCD_PS REG32(LCD_PS)
+#define REG_LCD_CLS REG32(LCD_CLS)
+#define REG_LCD_SPL REG32(LCD_SPL)
+#define REG_LCD_REV REG32(LCD_REV)
+#define REG_LCD_CTRL REG32(LCD_CTRL)
+#define REG_LCD_STATE REG32(LCD_STATE)
+#define REG_LCD_IID REG32(LCD_IID)
+#define REG_LCD_DA0 REG32(LCD_DA0)
+#define REG_LCD_SA0 REG32(LCD_SA0)
+#define REG_LCD_FID0 REG32(LCD_FID0)
+#define REG_LCD_CMD0 REG32(LCD_CMD0)
+#define REG_LCD_DA1 REG32(LCD_DA1)
+#define REG_LCD_SA1 REG32(LCD_SA1)
+#define REG_LCD_FID1 REG32(LCD_FID1)
+#define REG_LCD_CMD1 REG32(LCD_CMD1)
+
+/* LCD Configure Register */
+#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
+#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
+ #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
+ #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
+#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
+#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
+#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
+#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
+#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
+#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
+#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
+#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
+#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
+#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
+#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
+#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
+#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
+#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
+#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
+#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
+#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
+#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
+#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
+ #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
+ #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
+ #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
+#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
+#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
+ #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT)
+ /* JZ47XX defines */
+ #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
+ #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
+
+
+
+/* Vertical Synchronize Register */
+#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
+#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
+#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
+#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
+
+/* Horizontal Synchronize Register */
+#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
+#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
+#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
+#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
+
+/* Virtual Area Setting Register */
+#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
+#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
+#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
+#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
+
+/* Display Area Horizontal Start/End Point Register */
+#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
+#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
+#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
+#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
+
+/* Display Area Vertical Start/End Point Register */
+#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
+#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
+#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
+#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
+
+/* PS Signal Setting */
+#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
+#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
+#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
+#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
+
+/* CLS Signal Setting */
+#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
+#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
+#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
+#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
+
+/* SPL Signal Setting */
+#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
+#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
+#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
+#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
+
+/* REV Signal Setting */
+#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
+#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
+
+/* LCD Control Register */
+#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
+#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
+ #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
+ #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
+ #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
+#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
+#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
+#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
+#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
+#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
+ #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
+ #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
+ #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
+#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
+#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
+#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
+#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
+#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
+#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
+#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
+#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
+#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
+#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
+#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
+#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
+#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
+#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
+#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
+ #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
+ #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
+ #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
+ #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
+ #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
+ #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
+
+/* LCD Status Register */
+#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
+#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
+#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
+#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
+#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
+#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
+#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
+
+/* DMA Command Register */
+#define LCD_CMD_SOFINT (1 << 31)
+#define LCD_CMD_EOFINT (1 << 30)
+#define LCD_CMD_PAL (1 << 28)
+#define LCD_CMD_LEN_BIT 0
+#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
+
+
+/*************************************************************************
+ * USB Device
+ *************************************************************************/
+#define USB_BASE UDC_BASE
+
+#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
+#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
+#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
+#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
+#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
+#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
+#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
+#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
+#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
+#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
+#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
+
+#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
+#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
+#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
+#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
+#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
+#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
+#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
+#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
+
+#define USB_FIFO_EP0 (USB_BASE + 0x20)
+#define USB_FIFO_EP1 (USB_BASE + 0x24)
+#define USB_FIFO_EP2 (USB_BASE + 0x28)
+
+#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
+#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
+
+#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
+#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
+#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
+#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
+#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
+#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
+#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
+
+
+/* Power register bit masks */
+#define USB_POWER_SUSPENDM 0x01
+#define USB_POWER_RESUME 0x04
+#define USB_POWER_HSMODE 0x10
+#define USB_POWER_HSENAB 0x20
+#define USB_POWER_SOFTCONN 0x40
+
+/* Interrupt register bit masks */
+#define USB_INTR_SUSPEND 0x01
+#define USB_INTR_RESUME 0x02
+#define USB_INTR_RESET 0x04
+
+#define USB_INTR_EP0 0x0001
+#define USB_INTR_INEP1 0x0002
+#define USB_INTR_INEP2 0x0004
+#define USB_INTR_OUTEP1 0x0002
+
+/* CSR0 bit masks */
+#define USB_CSR0_OUTPKTRDY 0x01
+#define USB_CSR0_INPKTRDY 0x02
+#define USB_CSR0_SENTSTALL 0x04
+#define USB_CSR0_DATAEND 0x08
+#define USB_CSR0_SETUPEND 0x10
+#define USB_CSR0_SENDSTALL 0x20
+#define USB_CSR0_SVDOUTPKTRDY 0x40
+#define USB_CSR0_SVDSETUPEND 0x80
+
+/* Endpoint CSR register bits */
+#define USB_INCSRH_AUTOSET 0x80
+#define USB_INCSRH_ISO 0x40
+#define USB_INCSRH_MODE 0x20
+#define USB_INCSRH_DMAREQENAB 0x10
+#define USB_INCSRH_DMAREQMODE 0x04
+#define USB_INCSR_CDT 0x40
+#define USB_INCSR_SENTSTALL 0x20
+#define USB_INCSR_SENDSTALL 0x10
+#define USB_INCSR_FF 0x08
+#define USB_INCSR_UNDERRUN 0x04
+#define USB_INCSR_FFNOTEMPT 0x02
+#define USB_INCSR_INPKTRDY 0x01
+#define USB_OUTCSRH_AUTOCLR 0x80
+#define USB_OUTCSRH_ISO 0x40
+#define USB_OUTCSRH_DMAREQENAB 0x20
+#define USB_OUTCSRH_DNYT 0x10
+#define USB_OUTCSRH_DMAREQMODE 0x08
+#define USB_OUTCSR_CDT 0x80
+#define USB_OUTCSR_SENTSTALL 0x40
+#define USB_OUTCSR_SENDSTALL 0x20
+#define USB_OUTCSR_FF 0x10
+#define USB_OUTCSR_DATAERR 0x08
+#define USB_OUTCSR_OVERRUN 0x04
+#define USB_OUTCSR_FFFULL 0x02
+#define USB_OUTCSR_OUTPKTRDY 0x01
+
+/* Testmode register bits */
+#define USB_TEST_SE0NAK 0x01
+#define USB_TEST_J 0x02
+#define USB_TEST_K 0x04
+#define USB_TEST_PACKET 0x08
+
+/* DMA control bits */
+#define USB_CNTL_ENA 0x01
+#define USB_CNTL_DIR_IN 0x02
+#define USB_CNTL_MODE_1 0x04
+#define USB_CNTL_INTR_EN 0x08
+#define USB_CNTL_EP(n) ((n) << 4)
+#define USB_CNTL_BURST_0 (0 << 9)
+#define USB_CNTL_BURST_4 (1 << 9)
+#define USB_CNTL_BURST_8 (2 << 9)
+#define USB_CNTL_BURST_16 (3 << 9)
+
+
+//----------------------------------------------------------------------
+//
+// Module Operation Definitions
+//
+//----------------------------------------------------------------------
+#ifndef __ASSEMBLY__
+
+/***************************************************************************
+ * GPIO
+ ***************************************************************************/
+
+//------------------------------------------------------
+// GPIO Pins Description
+//
+// PORT 0:
+//
+// PIN/BIT N FUNC0 FUNC1
+// 0 D0 -
+// 1 D1 -
+// 2 D2 -
+// 3 D3 -
+// 4 D4 -
+// 5 D5 -
+// 6 D6 -
+// 7 D7 -
+// 8 D8 -
+// 9 D9 -
+// 10 D10 -
+// 11 D11 -
+// 12 D12 -
+// 13 D13 -
+// 14 D14 -
+// 15 D15 -
+// 16 D16 -
+// 17 D17 -
+// 18 D18 -
+// 19 D19 -
+// 20 D20 -
+// 21 D21 -
+// 22 D22 -
+// 23 D23 -
+// 24 D24 -
+// 25 D25 -
+// 26 D26 -
+// 27 D27 -
+// 28 D28 -
+// 29 D29 -
+// 30 D30 -
+// 31 D31 -
+//
+//------------------------------------------------------
+// PORT 1:
+//
+// PIN/BIT N FUNC0 FUNC1
+// 0 A0 -
+// 1 A1 -
+// 2 A2 -
+// 3 A3 -
+// 4 A4 -
+// 5 A5 -
+// 6 A6 -
+// 7 A7 -
+// 8 A8 -
+// 9 A9 -
+// 10 A10 -
+// 11 A11 -
+// 12 A12 -
+// 13 A13 -
+// 14 A14 -
+// 15 A15/CL -
+// 16 A16/AL -
+// 17 LCD_CLS A21
+// 18 LCD_SPL A22
+// 19 DCS# -
+// 20 RAS# -
+// 21 CAS# -
+// 22 RDWE#/BUFD# -
+// 23 CKE -
+// 24 CKO -
+// 25 CS1# -
+// 26 CS2# -
+// 27 CS3# -
+// 28 CS4# -
+// 29 RD# -
+// 30 WR# -
+// 31 WE0# -
+//
+// Note: PIN15&16 are CL&AL when connecting to NAND flash.
+//------------------------------------------------------
+// PORT 2:
+//
+// PIN/BIT N FUNC0 FUNC1
+// 0 LCD_D0 -
+// 1 LCD_D1 -
+// 2 LCD_D2 -
+// 3 LCD_D3 -
+// 4 LCD_D4 -
+// 5 LCD_D5 -
+// 6 LCD_D6 -
+// 7 LCD_D7 -
+// 8 LCD_D8 -
+// 9 LCD_D9 -
+// 10 LCD_D10 -
+// 11 LCD_D11 -
+// 12 LCD_D12 -
+// 13 LCD_D13 -
+// 14 LCD_D14 -
+// 15 LCD_D15 -
+// 16 LCD_D16 -
+// 17 LCD_D17 -
+// 18 LCD_PCLK -
+// 19 LCD_HSYNC -
+// 20 LCD_VSYNC -
+// 21 LCD_DE -
+// 22 LCD_PS A19
+// 23 LCD_REV A20
+// 24 WE1# -
+// 25 WE2# -
+// 26 WE3# -
+// 27 WAIT# -
+// 28 FRE# -
+// 29 FWE# -
+// 30(NOTE:FRB#) - -
+// 31 - -
+//
+// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
+//------------------------------------------------------
+// PORT 3:
+//
+// PIN/BIT N FUNC0 FUNC1
+// 0 CIM_D0 -
+// 1 CIM_D1 -
+// 2 CIM_D2 -
+// 3 CIM_D3 -
+// 4 CIM_D4 -
+// 5 CIM_D5 -
+// 6 CIM_D6 -
+// 7 CIM_D7 -
+// 8 MSC_CMD -
+// 9 MSC_CLK -
+// 10 MSC_D0 -
+// 11 MSC_D1 -
+// 12 MSC_D2 -
+// 13 MSC_D3 -
+// 14 CIM_MCLK -
+// 15 CIM_PCLK -
+// 16 CIM_VSYNC -
+// 17 CIM_HSYNC -
+// 18 SSI_CLK SCLK_RSTN
+// 19 SSI_CE0# BIT_CLK(AIC)
+// 20 SSI_DT SDATA_OUT(AIC)
+// 21 SSI_DR SDATA_IN(AIC)
+// 22 SSI_CE1#&GPC SYNC(AIC)
+// 23 PWM0 I2C_SDA
+// 24 PWM1 I2C_SCK
+// 25 PWM2 UART0_TxD
+// 26 PWM3 UART0_RxD
+// 27 PWM4 A17
+// 28 PWM5 A18
+// 29 - -
+// 30 PWM6 UART0_CTS/UART1_RxD
+// 31 PWM7 UART0_RTS/UART1_TxD
+//
+//////////////////////////////////////////////////////////
+
+/*
+ * p is the port number (0,1,2,3)
+ * o is the pin offset (0-31) inside the port
+ * n is the absolute number of a pin (0-127), regardless of the port
+ */
+
+//-------------------------------------------
+// Function Pins Mode
+
+#define __gpio_as_func0(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXFUNS(p) = (1 << o); \
+ REG_GPIO_PXSELC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_as_func1(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXFUNS(p) = (1 << o); \
+ REG_GPIO_PXSELS(p) = (1 << o); \
+} while (0)
+
+/*
+ * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
+ * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
+ */
+#define __gpio_as_sdram_32bit() \
+do { \
+ REG_GPIO_PXFUNS(0) = 0xffffffff; \
+ REG_GPIO_PXSELC(0) = 0xffffffff; \
+ REG_GPIO_PXPES(0) = 0xffffffff; \
+ REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
+ REG_GPIO_PXSELC(1) = 0x81f9ffff; \
+ REG_GPIO_PXPES(1) = 0x81f9ffff; \
+ REG_GPIO_PXFUNS(2) = 0x07000000; \
+ REG_GPIO_PXSELC(2) = 0x07000000; \
+ REG_GPIO_PXPES(2) = 0x07000000; \
+} while (0)
+
+//#ifdef JZ4740_PAVO
+#ifdef JZ4740_4740
+/*
+ * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
+ * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
+ */
+#define __gpio_as_sdram_16bit() \
+do { \
+ REG_GPIO_PXFUNS(0) = 0x0000ffff; \
+ REG_GPIO_PXFUNS(0) = 0x0000ffff; \
+ REG_GPIO_PXPES(0) = 0x0000ffff; \
+ REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
+ REG_GPIO_PXSELC(1) = 0x81f9ffff; \
+ REG_GPIO_PXPES(1) = 0x81f9ffff; \
+ REG_GPIO_PXFUNS(2) = 0x07000000; \
+ REG_GPIO_PXSELC(2) = 0x07000000; \
+ REG_GPIO_PXPES(2) = 0x07000000; \
+} while (0)
+
+#endif
+
+//#ifdef JZ4740_VIRGO
+#ifdef JZ4740_4720
+/*
+ * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
+ * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
+ */
+#define __gpio_as_sdram_16bit() \
+do { \
+ REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
+ REG_GPIO_PXSELC(0) = 0x5442bfaa; \
+ REG_GPIO_PXPES(0) = 0x5442bfaa; \
+ REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
+ REG_GPIO_PXSELC(1) = 0x81f9ffff; \
+ REG_GPIO_PXPES(1) = 0x81f9ffff; \
+ REG_GPIO_PXFUNS(2) = 0x01000000; \
+ REG_GPIO_PXSELC(2) = 0x01000000; \
+ REG_GPIO_PXPES(2) = 0x01000000; \
+} while (0)
+#endif
+
+
+#ifdef JZ4740_4725
+/*
+ * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
+ * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
+ */
+#define __jz4725__gpio_as_sdram_16bit() \
+do { \
+ REG_GPIO_PXFUNS(0) = 0x0000ffff; \
+ REG_GPIO_PXSELC(0) = 0x0000ffff; \
+ REG_GPIO_PXPES(0) = 0x0000ffff; \
+ REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
+ REG_GPIO_PXSELC(1) = 0x81f9ffff; \
+ REG_GPIO_PXPES(1) = 0x81f9ffff; \
+ REG_GPIO_PXFUNS(2) = 0x07000000; \
+ REG_GPIO_PXSELC(2) = 0x07000000; \
+ REG_GPIO_PXPES(2) = 0x07000000; \
+} while (0)
+#endif
+/*
+ * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
+ */
+#define __gpio_as_nand() \
+do { \
+ REG_GPIO_PXFUNS(1) = 0x02018000; \
+ REG_GPIO_PXSELC(1) = 0x02018000; \
+ REG_GPIO_PXPES(1) = 0x02018000; \
+ REG_GPIO_PXFUNS(2) = 0x30000000; \
+ REG_GPIO_PXSELC(2) = 0x30000000; \
+ REG_GPIO_PXPES(2) = 0x30000000; \
+ REG_GPIO_PXFUNC(2) = 0x40000000; \
+ REG_GPIO_PXSELC(2) = 0x40000000; \
+ REG_GPIO_PXDIRC(2) = 0x40000000; \
+ REG_GPIO_PXPES(2) = 0x40000000; \
+ REG_GPIO_PXFUNS(1) = 0x00400000; \
+ REG_GPIO_PXSELC(1) = 0x00400000; \
+} while (0)
+
+/*
+ * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
+ */
+#define __gpio_as_nor_8bit() \
+do { \
+ REG_GPIO_PXFUNS(0) = 0x000000ff; \
+ REG_GPIO_PXSELC(0) = 0x000000ff; \
+ REG_GPIO_PXPES(0) = 0x000000ff; \
+ REG_GPIO_PXFUNS(1) = 0x7041ffff; \
+ REG_GPIO_PXSELC(1) = 0x7041ffff; \
+ REG_GPIO_PXPES(1) = 0x7041ffff; \
+ REG_GPIO_PXFUNS(1) = 0x00060000; \
+ REG_GPIO_PXSELS(1) = 0x00060000; \
+ REG_GPIO_PXPES(1) = 0x00060000; \
+ REG_GPIO_PXFUNS(2) = 0x08000000; \
+ REG_GPIO_PXSELC(2) = 0x08000000; \
+ REG_GPIO_PXPES(2) = 0x08000000; \
+ REG_GPIO_PXFUNS(2) = 0x00c00000; \
+ REG_GPIO_PXSELS(2) = 0x00c00000; \
+ REG_GPIO_PXPES(2) = 0x00c00000; \
+ REG_GPIO_PXFUNS(3) = 0x18000000; \
+ REG_GPIO_PXSELS(3) = 0x18000000; \
+ REG_GPIO_PXPES(3) = 0x18000000; \
+} while (0)
+
+/*
+ * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
+ */
+#define __gpio_as_nor_16bit() \
+do { \
+ REG_GPIO_PXFUNS(0) = 0x0000ffff; \
+ REG_GPIO_PXSELC(0) = 0x0000ffff; \
+ REG_GPIO_PXPES(0) = 0x0000ffff; \
+ REG_GPIO_PXFUNS(1) = 0x7041ffff; \
+ REG_GPIO_PXSELC(1) = 0x7041ffff; \
+ REG_GPIO_PXPES(1) = 0x7041ffff; \
+ REG_GPIO_PXFUNS(1) = 0x00060000; \
+ REG_GPIO_PXSELS(1) = 0x00060000; \
+ REG_GPIO_PXPES(1) = 0x00060000; \
+ REG_GPIO_PXFUNS(2) = 0x08000000; \
+ REG_GPIO_PXSELC(2) = 0x08000000; \
+ REG_GPIO_PXPES(2) = 0x08000000; \
+ REG_GPIO_PXFUNS(2) = 0x00c00000; \
+ REG_GPIO_PXSELS(2) = 0x00c00000; \
+ REG_GPIO_PXPES(2) = 0x00c00000; \
+ REG_GPIO_PXFUNS(3) = 0x18000000; \
+ REG_GPIO_PXSELS(3) = 0x18000000; \
+ REG_GPIO_PXPES(3) = 0x18000000; \
+} while (0)
+
+/*
+ * UART0_TxD, UART_RxD0
+ */
+#define __gpio_as_uart0() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x06000000; \
+ REG_GPIO_PXSELS(3) = 0x06000000; \
+ REG_GPIO_PXPES(3) = 0x06000000; \
+} while (0)
+
+/*
+ * UART1_TxD, UART1_RxD1
+ */
+#define __gpio_as_uart1() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0xc0000000; \
+ REG_GPIO_PXSELS(3) = 0xc0000000; \
+ REG_GPIO_PXPES(3) = 0xc0000000; \
+} while (0)
+
+/*
+ * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
+ */
+#define __gpio_as_lcd_16bit() \
+do { \
+ REG_GPIO_PXFUNS(2) = 0x003cffff; \
+ REG_GPIO_PXSELC(2) = 0x003cffff; \
+ REG_GPIO_PXPES(2) = 0x003cffff; \
+} while (0)
+
+/*
+ * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
+ */
+#define __gpio_as_lcd_18bit() \
+do { \
+ REG_GPIO_PXFUNS(2) = 0x003fffff; \
+ REG_GPIO_PXSELC(2) = 0x003fffff; \
+ REG_GPIO_PXPES(2) = 0x003fffff; \
+} while (0)
+
+
+/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
+#define __gpio_as_slcd_8bit() \
+do { \
+ REG_GPIO_PXFUNS(2) = 0x001800ff; \
+ REG_GPIO_PXSELC(2) = 0x001800ff; \
+} while (0)
+
+/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
+#define __gpio_as_slcd_9bit() \
+do { \
+ REG_GPIO_PXFUNS(2) = 0x001801ff; \
+ REG_GPIO_PXSELC(2) = 0x001801ff; \
+} while (0)
+
+/* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */
+#define __gpio_as_slcd_16bit() \
+do { \
+ REG_GPIO_PXFUNS(2) = 0x0018ffff; \
+ REG_GPIO_PXSELC(2) = 0x0018ffff; \
+} while (0)
+
+/* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */
+#define __gpio_as_slcd_18bit() \
+do { \
+ REG_GPIO_PXFUNS(2) = 0x001bffff; \
+ REG_GPIO_PXSELC(2) = 0x001bffff; \
+} while (0)
+
+/*
+ * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
+ */
+#define __gpio_as_cim() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
+ REG_GPIO_PXSELC(3) = 0x0003c0ff; \
+ REG_GPIO_PXPES(3) = 0x0003c0ff; \
+} while (0)
+
+/*
+ * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
+ */
+#define __gpio_as_aic() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x007c0000; \
+ REG_GPIO_PXSELS(3) = 0x007c0000; \
+ REG_GPIO_PXPES(3) = 0x007c0000; \
+} while (0)
+
+/*
+ * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
+ */
+#define __gpio_as_msc() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x00003f00; \
+ REG_GPIO_PXSELC(3) = 0x00003f00; \
+ REG_GPIO_PXPES(3) = 0x00003f00; \
+} while (0)
+
+/*
+ * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
+ */
+#define __gpio_as_ssi() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x003c0000; \
+ REG_GPIO_PXSELC(3) = 0x003c0000; \
+ REG_GPIO_PXPES(3) = 0x003c0000; \
+} while (0)
+
+/*
+ * I2C_SCK, I2C_SDA
+ */
+#define __gpio_as_i2c() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x01800000; \
+ REG_GPIO_PXSELS(3) = 0x01800000; \
+ REG_GPIO_PXPES(3) = 0x01800000; \
+} while (0)
+
+/*
+ * PWM0
+ */
+#define __gpio_as_pwm0() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x00800000; \
+ REG_GPIO_PXSELC(3) = 0x00800000; \
+ REG_GPIO_PXPES(3) = 0x00800000; \
+} while (0)
+
+/*
+ * PWM1
+ */
+#define __gpio_as_pwm1() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x01000000; \
+ REG_GPIO_PXSELC(3) = 0x01000000; \
+ REG_GPIO_PXPES(3) = 0x01000000; \
+} while (0)
+
+/*
+ * PWM2
+ */
+#define __gpio_as_pwm2() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x02000000; \
+ REG_GPIO_PXSELC(3) = 0x02000000; \
+ REG_GPIO_PXPES(3) = 0x02000000; \
+} while (0)
+
+/*
+ * PWM3
+ */
+#define __gpio_as_pwm3() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x04000000; \
+ REG_GPIO_PXSELC(3) = 0x04000000; \
+ REG_GPIO_PXPES(3) = 0x04000000; \
+} while (0)
+
+/*
+ * PWM4
+ */
+#define __gpio_as_pwm4() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x08000000; \
+ REG_GPIO_PXSELC(3) = 0x08000000; \
+ REG_GPIO_PXPES(3) = 0x08000000; \
+} while (0)
+
+/*
+ * PWM5
+ */
+#define __gpio_as_pwm5() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x10000000; \
+ REG_GPIO_PXSELC(3) = 0x10000000; \
+ REG_GPIO_PXPES(3) = 0x10000000; \
+} while (0)
+
+/*
+ * PWM6
+ */
+#define __gpio_as_pwm6() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x40000000; \
+ REG_GPIO_PXSELC(3) = 0x40000000; \
+ REG_GPIO_PXPES(3) = 0x40000000; \
+} while (0)
+
+/*
+ * PWM7
+ */
+#define __gpio_as_pwm7() \
+do { \
+ REG_GPIO_PXFUNS(3) = 0x80000000; \
+ REG_GPIO_PXSELC(3) = 0x80000000; \
+ REG_GPIO_PXPES(3) = 0x80000000; \
+} while (0)
+
+/*
+ * n = 0 ~ 7
+ */
+#define __gpio_as_pwm(n) __gpio_as_pwm##n()
+
+//-------------------------------------------
+// GPIO or Interrupt Mode
+
+#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
+
+#define __gpio_port_as_output(p, o) \
+do { \
+ REG_GPIO_PXFUNC(p) = (1 << (o)); \
+ REG_GPIO_PXSELC(p) = (1 << (o)); \
+ REG_GPIO_PXDIRS(p) = (1 << (o)); \
+} while (0)
+
+#define __gpio_port_as_input(p, o) \
+do { \
+ REG_GPIO_PXFUNC(p) = (1 << (o)); \
+ REG_GPIO_PXSELC(p) = (1 << (o)); \
+ REG_GPIO_PXDIRC(p) = (1 << (o)); \
+} while (0)
+
+#define __gpio_as_output(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ __gpio_port_as_output(p, o); \
+} while (0)
+
+#define __gpio_as_input(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ __gpio_port_as_input(p, o); \
+} while (0)
+
+#define __gpio_set_pin(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXDATS(p) = (1 << o); \
+} while (0)
+
+#define __gpio_clear_pin(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXDATC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_get_pin(n) \
+({ \
+ unsigned int p, o, v; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ if (__gpio_get_port(p) & (1 << o)) \
+ v = 1; \
+ else \
+ v = 0; \
+ v; \
+})
+
+#define __gpio_as_irq_high_level(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXIMS(p) = (1 << o); \
+ REG_GPIO_PXTRGC(p) = (1 << o); \
+ REG_GPIO_PXFUNC(p) = (1 << o); \
+ REG_GPIO_PXSELS(p) = (1 << o); \
+ REG_GPIO_PXDIRS(p) = (1 << o); \
+ REG_GPIO_PXFLGC(p) = (1 << o); \
+ REG_GPIO_PXIMC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_as_irq_low_level(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXIMS(p) = (1 << o); \
+ REG_GPIO_PXTRGC(p) = (1 << o); \
+ REG_GPIO_PXFUNC(p) = (1 << o); \
+ REG_GPIO_PXSELS(p) = (1 << o); \
+ REG_GPIO_PXDIRC(p) = (1 << o); \
+ REG_GPIO_PXFLGC(p) = (1 << o); \
+ REG_GPIO_PXIMC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_as_irq_rise_edge(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXIMS(p) = (1 << o); \
+ REG_GPIO_PXTRGS(p) = (1 << o); \
+ REG_GPIO_PXFUNC(p) = (1 << o); \
+ REG_GPIO_PXSELS(p) = (1 << o); \
+ REG_GPIO_PXDIRS(p) = (1 << o); \
+ REG_GPIO_PXFLGC(p) = (1 << o); \
+ REG_GPIO_PXIMC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_as_irq_fall_edge(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXIMS(p) = (1 << o); \
+ REG_GPIO_PXTRGS(p) = (1 << o); \
+ REG_GPIO_PXFUNC(p) = (1 << o); \
+ REG_GPIO_PXSELS(p) = (1 << o); \
+ REG_GPIO_PXDIRC(p) = (1 << o); \
+ REG_GPIO_PXFLGC(p) = (1 << o); \
+ REG_GPIO_PXIMC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_mask_irq(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXIMS(p) = (1 << o); \
+} while (0)
+
+#define __gpio_unmask_irq(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXIMC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_ack_irq(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXFLGC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_get_irq() \
+({ \
+ unsigned int p, i, tmp, v = 0; \
+ for (p = 3; p >= 0; p--) { \
+ tmp = REG_GPIO_PXFLG(p); \
+ for (i = 0; i < 32; i++) \
+ if (tmp & (1 << i)) \
+ v = (32*p + i); \
+ } \
+ v; \
+})
+
+#define __gpio_group_irq(n) \
+({ \
+ register int tmp, i; \
+ tmp = REG_GPIO_PXFLG((n)); \
+ for (i=31;i>=0;i--) \
+ if (tmp & (1 << i)) \
+ break; \
+ i; \
+})
+
+#define __gpio_enable_pull(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXPEC(p) = (1 << o); \
+} while (0)
+
+#define __gpio_disable_pull(n) \
+do { \
+ unsigned int p, o; \
+ p = (n) / 32; \
+ o = (n) % 32; \
+ REG_GPIO_PXPES(p) = (1 << o); \
+} while (0)
+
+
+/***************************************************************************
+ * CPM
+ ***************************************************************************/
+#define __cpm_get_pllm() \
+ ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
+#define __cpm_get_plln() \
+ ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
+#define __cpm_get_pllod() \
+ ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
+
+#define __cpm_get_cdiv() \
+ ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
+#define __cpm_get_hdiv() \
+ ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
+#define __cpm_get_pdiv() \
+ ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
+#define __cpm_get_mdiv() \
+ ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
+#define __cpm_get_ldiv() \
+ ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
+#define __cpm_get_udiv() \
+ ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
+#define __cpm_get_i2sdiv() \
+ ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
+#define __cpm_get_pixdiv() \
+ ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
+#define __cpm_get_mscdiv() \
+ ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
+
+#define __cpm_set_cdiv(v) \
+ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
+#define __cpm_set_hdiv(v) \
+ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
+#define __cpm_set_pdiv(v) \
+ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
+#define __cpm_set_mdiv(v) \
+ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
+#define __cpm_set_ldiv(v) \
+ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
+#define __cpm_set_udiv(v) \
+ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
+#define __cpm_set_i2sdiv(v) \
+ (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
+#define __cpm_set_pixdiv(v) \
+ (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
+#define __cpm_set_mscdiv(v) \
+ (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
+
+#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
+#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
+#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
+#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
+#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
+#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
+#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
+#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
+
+#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
+#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
+#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
+
+#define __cpm_get_cclk_doze_duty() \
+ ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
+#define __cpm_set_cclk_doze_duty(v) \
+ (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
+
+#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
+#define __cpm_idle_mode() \
+ (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
+#define __cpm_sleep_mode() \
+ (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
+
+#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
+#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
+#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
+#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
+#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
+#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
+#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
+#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
+#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
+#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
+#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
+#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
+#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
+#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
+#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
+#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
+#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
+
+#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
+#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
+#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
+#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
+#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
+#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
+#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
+#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
+#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
+#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
+#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
+#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
+#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
+#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
+#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
+#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
+#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
+
+#define __cpm_get_o1st() \
+ ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
+#define __cpm_set_o1st(v) \
+ (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
+#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
+#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
+
+
+#ifdef CFG_EXTAL
+#define JZ_EXTAL CFG_EXTAL
+#else
+#define JZ_EXTAL 3686400
+#endif
+#define JZ_EXTAL2 32768 /* RTC clock */
+
+/* PLL output frequency */
+static __inline__ unsigned int __cpm_get_pllout(void)
+{
+ unsigned long m, n, no, pllout;
+ unsigned long cppcr = REG_CPM_CPPCR;
+ unsigned long od[4] = {1, 2, 2, 4};
+ if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
+ m = __cpm_get_pllm() + 2;
+ n = __cpm_get_plln() + 2;
+ no = od[__cpm_get_pllod()];
+ pllout = ((JZ_EXTAL) / (n * no)) * m;
+ } else
+ pllout = JZ_EXTAL;
+ return pllout;
+}
+
+/* PLL output frequency for MSC/I2S/LCD/USB */
+static __inline__ unsigned int __cpm_get_pllout2(void)
+{
+ if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
+ return __cpm_get_pllout();
+ else
+ return __cpm_get_pllout()/2;
+}
+
+/* CPU core clock */
+static __inline__ unsigned int __cpm_get_cclk(void)
+{
+ int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+ return __cpm_get_pllout() / div[__cpm_get_cdiv()];
+}
+
+/* AHB system bus clock */
+static __inline__ unsigned int __cpm_get_hclk(void)
+{
+ int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+ return __cpm_get_pllout() / div[__cpm_get_hdiv()];
+}
+
+/* Memory bus clock */
+static __inline__ unsigned int __cpm_get_mclk(void)
+{
+ int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+ return __cpm_get_pllout() / div[__cpm_get_mdiv()];
+}
+
+/* APB peripheral bus clock */
+static __inline__ unsigned int __cpm_get_pclk(void)
+{
+ int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+ return __cpm_get_pllout() / div[__cpm_get_pdiv()];
+}
+
+/* LCDC module clock */
+static __inline__ unsigned int __cpm_get_lcdclk(void)
+{
+ return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
+}
+
+/* LCD pixel clock */
+static __inline__ unsigned int __cpm_get_pixclk(void)
+{
+ return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
+}
+
+/* I2S clock */
+static __inline__ unsigned int __cpm_get_i2sclk(void)
+{
+ if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
+ return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
+ }
+ else {
+ return JZ_EXTAL;
+ }
+}
+
+/* USB clock */
+static __inline__ unsigned int __cpm_get_usbclk(void)
+{
+ if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
+ return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
+ }
+ else {
+ return JZ_EXTAL;
+ }
+}
+
+/* MSC clock */
+static __inline__ unsigned int __cpm_get_mscclk(void)
+{
+ return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
+}
+
+/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
+static __inline__ unsigned int __cpm_get_extalclk(void)
+{
+ return JZ_EXTAL;
+}
+
+/* RTC clock for CPM,INTC,RTC,TCU,WDT */
+static __inline__ unsigned int __cpm_get_rtcclk(void)
+{
+ return JZ_EXTAL2;
+}
+
+/*
+ * Output 24MHz for SD and 16MHz for MMC.
+ */
+static inline void __cpm_select_msc_clk(int sd)
+{
+ unsigned int pllout2 = __cpm_get_pllout2();
+ unsigned int div = 0;
+
+ if (sd) {
+ div = pllout2 / 24000000;
+ }
+ else {
+ div = pllout2 / 16000000;
+ }
+
+ REG_CPM_MSCCDR = div - 1;
+}
+
+/*
+ * Output 48MHz for SD and 16MHz for MMC.
+ */
+static inline void __cpm_select_msc_hs_clk(int sd)
+{
+ unsigned int pllout2 = __cpm_get_pllout2();
+ unsigned int div = 0;
+
+ if (sd) {
+ div = pllout2 / 48000000;
+ }
+ else {
+ div = pllout2 / 16000000;
+ }
+ REG_CPM_MSCCDR = div - 1;
+}
+
+/***************************************************************************
+ * TCU
+ ***************************************************************************/
+// where 'n' is the TCU channel
+#define __tcu_select_extalclk(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
+#define __tcu_select_rtcclk(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
+#define __tcu_select_pclk(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
+
+#define __tcu_select_clk_div1(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
+#define __tcu_select_clk_div4(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
+#define __tcu_select_clk_div16(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
+#define __tcu_select_clk_div64(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
+#define __tcu_select_clk_div256(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
+#define __tcu_select_clk_div1024(n) \
+ (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
+
+#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
+#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
+
+#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
+#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
+
+#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
+#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
+
+#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
+#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
+
+#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
+#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
+#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
+#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
+#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
+#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
+#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
+#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
+#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
+#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
+
+#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
+#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
+
+#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
+#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
+
+#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
+#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
+
+#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
+#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
+#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
+#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
+
+
+/***************************************************************************
+ * WDT
+ ***************************************************************************/
+#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
+#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
+#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
+#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
+
+#define __wdt_select_extalclk() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
+#define __wdt_select_rtcclk() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
+#define __wdt_select_pclk() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
+
+#define __wdt_select_clk_div1() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
+#define __wdt_select_clk_div4() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
+#define __wdt_select_clk_div16() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
+#define __wdt_select_clk_div64() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
+#define __wdt_select_clk_div256() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
+#define __wdt_select_clk_div1024() \
+ (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
+
+
+/***************************************************************************
+ * UART
+ ***************************************************************************/
+
+#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
+#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
+
+#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
+#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
+
+#define __uart_enable_receive_irq() \
+ ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
+#define __uart_disable_receive_irq() \
+ ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
+
+#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
+#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
+
+#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
+
+#define __uart_set_baud(devclk, baud) \
+ do { \
+ REG8(UART0_LCR) |= UARTLCR_DLAB; \
+ REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
+ REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
+ REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
+ } while (0)
+
+#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
+#define __uart_clear_errors() \
+ ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
+
+#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
+#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
+#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
+#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
+#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
+#define __uart_receive_char() REG8(UART0_RDR)
+#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
+#define __uart_enable_irda() \
+ /* Tx high pulse as 0, Rx low pulse as 0 */ \
+ ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
+
+
+/***************************************************************************
+ * DMAC
+ ***************************************************************************/
+
+/* n is the DMA channel (0 - 5) */
+
+#define __dmac_enable_module() \
+ ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
+#define __dmac_disable_module() \
+ ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
+
+/* p=0,1,2,3 */
+#define __dmac_set_priority(p) \
+do { \
+ REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
+ REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
+} while (0)
+
+#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
+#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
+
+#define __dmac_enable_descriptor(n) \
+ ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
+#define __dmac_disable_descriptor(n) \
+ ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
+
+#define __dmac_enable_channel(n) \
+ ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
+#define __dmac_disable_channel(n) \
+ ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
+#define __dmac_channel_enabled(n) \
+ ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
+
+#define __dmac_channel_enable_irq(n) \
+ ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
+#define __dmac_channel_disable_irq(n) \
+ ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
+
+#define __dmac_channel_transmit_halt_detected(n) \
+ ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
+#define __dmac_channel_transmit_end_detected(n) \
+ ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
+#define __dmac_channel_address_error_detected(n) \
+ ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
+#define __dmac_channel_count_terminated_detected(n) \
+ ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
+#define __dmac_channel_descriptor_invalid_detected(n) \
+ ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
+
+#define __dmac_channel_clear_transmit_halt(n) \
+ ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
+#define __dmac_channel_clear_transmit_end(n) \
+ ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
+#define __dmac_channel_clear_address_error(n) \
+ ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
+#define __dmac_channel_clear_count_terminated(n) \
+ ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
+#define __dmac_channel_clear_descriptor_invalid(n) \
+ ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
+
+#define __dmac_channel_set_single_mode(n) \
+ ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
+#define __dmac_channel_set_block_mode(n) \
+ ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
+
+#define __dmac_channel_set_transfer_unit_32bit(n) \
+do { \
+ REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
+ REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
+} while (0)
+
+#define __dmac_channel_set_transfer_unit_16bit(n) \
+do { \
+ REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
+ REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
+} while (0)
+
+#define __dmac_channel_set_transfer_unit_8bit(n) \
+do { \
+ REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
+ REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
+} while (0)
+
+#define __dmac_channel_set_transfer_unit_16byte(n) \
+do { \
+ REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
+ REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
+} while (0)
+
+#define __dmac_channel_set_transfer_unit_32byte(n) \
+do { \
+ REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
+ REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
+} while (0)
+
+/* w=8,16,32 */
+#define __dmac_channel_set_dest_port_width(n,w) \
+do { \
+ REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
+ REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
+} while (0)
+
+/* w=8,16,32 */
+#define __dmac_channel_set_src_port_width(n,w) \
+do { \
+ REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
+ REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
+} while (0)
+
+/* v=0-15 */
+#define __dmac_channel_set_rdil(n,v) \
+do { \
+ REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
+ REG_DMAC_DCMD((n)) |= ((v) << DMAC_DCMD_RDIL_BIT); \
+} while (0)
+
+#define __dmac_channel_dest_addr_fixed(n) \
+ ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
+#define __dmac_channel_dest_addr_increment(n) \
+ ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
+
+#define __dmac_channel_src_addr_fixed(n) \
+ ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
+#define __dmac_channel_src_addr_increment(n) \
+ ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
+
+#define __dmac_channel_set_doorbell(n) \
+ ( REG_DMAC_DMADBSR = (1 << (n)) )
+
+#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
+#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
+
+static __inline__ int __dmac_get_irq(void)
+{
+ int i;
+ for (i = 0; i < MAX_DMA_NUM; i++)
+ if (__dmac_channel_irq_detected(i))
+ return i;
+ return -1;
+}
+
+
+/***************************************************************************
+ * AIC (AC'97 & I2S Controller)
+ ***************************************************************************/
+
+#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
+#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
+
+#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
+#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
+
+#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
+#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
+#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
+
+#define __aic_reset() \
+do { \
+ REG_AIC_FR |= AIC_FR_RST; \
+} while(0)
+
+
+#define __aic_set_transmit_trigger(n) \
+do { \
+ REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
+ REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
+} while(0)
+
+#define __aic_set_receive_trigger(n) \
+do { \
+ REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
+ REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
+} while(0)
+
+#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
+#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
+#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
+#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
+#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
+#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
+
+#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
+#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
+
+#define __aic_enable_transmit_intr() \
+ ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
+#define __aic_disable_transmit_intr() \
+ ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
+#define __aic_enable_receive_intr() \
+ ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
+#define __aic_disable_receive_intr() \
+ ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
+
+#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
+#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
+#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
+#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
+
+#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
+#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
+#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
+#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
+#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
+#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
+
+#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
+#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
+#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
+#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
+#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
+#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
+
+#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
+#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
+#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
+#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
+#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
+#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
+
+#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
+#define __ac97_set_xs_mono() \
+do { \
+ REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
+ REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
+} while(0)
+#define __ac97_set_xs_stereo() \
+do { \
+ REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
+ REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
+} while(0)
+
+/* In fact, only stereo is support now. */
+#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
+#define __ac97_set_rs_mono() \
+do { \
+ REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
+ REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
+} while(0)
+#define __ac97_set_rs_stereo() \
+do { \
+ REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
+ REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
+} while(0)
+
+#define __ac97_warm_reset_codec() \
+ do { \
+ REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
+ REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
+ udelay(2); \
+ REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
+ REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
+ } while (0)
+
+#define __ac97_cold_reset_codec() \
+ do { \
+ REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
+ udelay(2); \
+ REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
+ } while (0)
+
+/* n=8,16,18,20 */
+#define __ac97_set_iass(n) \
+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
+#define __ac97_set_oass(n) \
+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
+
+#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
+#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
+
+/* n=8,16,18,20,24 */
+/*#define __i2s_set_sample_size(n) \
+ ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
+
+#define __i2s_set_oss_sample_size(n) \
+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
+#define __i2s_set_iss_sample_size(n) \
+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
+
+#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
+#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
+
+#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
+#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
+#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
+#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
+
+#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
+
+#define __aic_get_transmit_resident() \
+ ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
+#define __aic_get_receive_count() \
+ ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
+
+#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
+#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
+#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
+#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
+#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
+#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
+#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
+
+#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
+
+#define CODEC_READ_CMD (1 << 19)
+#define CODEC_WRITE_CMD (0 << 19)
+#define CODEC_REG_INDEX_BIT 12
+#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
+#define CODEC_REG_DATA_BIT 4
+#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
+
+#define __ac97_out_rcmd_addr(reg) \
+do { \
+ REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
+} while (0)
+
+#define __ac97_out_wcmd_addr(reg) \
+do { \
+ REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
+} while (0)
+
+#define __ac97_out_data(value) \
+do { \
+ REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
+} while (0)
+
+#define __ac97_in_data() \
+ ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
+
+#define __ac97_in_status_addr() \
+ ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
+
+#define __i2s_set_sample_rate(i2sclk, sync) \
+ ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
+
+#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
+#define __aic_read_rfifo() ( REG_AIC_DR )
+
+#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
+#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
+
+#define AIC_FR_LSMP (1 << 6)
+#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
+//
+// Define next ops for AC97 compatible
+//
+
+#define AC97_ACSR AIC_ACSR
+
+#define __ac97_enable() __aic_enable(); __aic_select_ac97()
+#define __ac97_disable() __aic_disable()
+#define __ac97_reset() __aic_reset()
+
+#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
+#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
+
+#define __ac97_enable_record() __aic_enable_record()
+#define __ac97_disable_record() __aic_disable_record()
+#define __ac97_enable_replay() __aic_enable_replay()
+#define __ac97_disable_replay() __aic_disable_replay()
+#define __ac97_enable_loopback() __aic_enable_loopback()
+#define __ac97_disable_loopback() __aic_disable_loopback()
+
+#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
+#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
+#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
+#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
+
+#define __ac97_transmit_request() __aic_transmit_request()
+#define __ac97_receive_request() __aic_receive_request()
+#define __ac97_transmit_underrun() __aic_transmit_underrun()
+#define __ac97_receive_overrun() __aic_receive_overrun()
+
+#define __ac97_clear_errors() __aic_clear_errors()
+
+#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
+#define __ac97_get_receive_count() __aic_get_receive_count()
+
+#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
+#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
+#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
+#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
+
+#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
+#define __ac97_read_rfifo() __aic_read_rfifo()
+
+//
+// Define next ops for I2S compatible
+//
+
+#define I2S_ACSR AIC_I2SSR
+
+#define __i2s_enable() __aic_enable(); __aic_select_i2s()
+#define __i2s_disable() __aic_disable()
+#define __i2s_reset() __aic_reset()
+
+#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
+#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
+
+#define __i2s_enable_record() __aic_enable_record()
+#define __i2s_disable_record() __aic_disable_record()
+#define __i2s_enable_replay() __aic_enable_replay()
+#define __i2s_disable_replay() __aic_disable_replay()
+#define __i2s_enable_loopback() __aic_enable_loopback()
+#define __i2s_disable_loopback() __aic_disable_loopback()
+
+#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
+#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
+#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
+#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
+
+#define __i2s_transmit_request() __aic_transmit_request()
+#define __i2s_receive_request() __aic_receive_request()
+#define __i2s_transmit_underrun() __aic_transmit_underrun()
+#define __i2s_receive_overrun() __aic_receive_overrun()
+
+#define __i2s_clear_errors() __aic_clear_errors()
+
+#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
+#define __i2s_get_receive_count() __aic_get_receive_count()
+
+#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
+#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
+#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
+#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
+
+#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
+#define __i2s_read_rfifo() __aic_read_rfifo()
+
+#define __i2s_reset_codec() \
+ do { \
+ } while (0)
+
+
+/***************************************************************************
+ * ICDC
+ ***************************************************************************/
+#define __i2s_internal_codec() __aic_internal_codec()
+#define __i2s_external_codec() __aic_external_codec()
+
+/***************************************************************************
+ * INTC
+ ***************************************************************************/
+#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
+#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
+#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
+
+
+/***************************************************************************
+ * I2C
+ ***************************************************************************/
+
+#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
+#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
+
+#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
+#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
+#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
+#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
+
+#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
+#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
+#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
+
+#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
+#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
+#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
+
+#define __i2c_set_clk(dev_clk, i2c_clk) \
+ ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
+
+#define __i2c_read() ( REG_I2C_DR )
+#define __i2c_write(val) ( REG_I2C_DR = (val) )
+
+
+/***************************************************************************
+ * MSC
+ ***************************************************************************/
+
+#define __msc_start_op() \
+ ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
+
+#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
+#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
+#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
+#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
+#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
+#define __msc_get_nob() ( REG_MSC_NOB )
+#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
+#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
+#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
+#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
+
+#define __msc_set_cmdat_bus_width1() \
+do { \
+ REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
+ REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
+} while(0)
+
+#define __msc_set_cmdat_bus_width4() \
+do { \
+ REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
+ REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
+} while(0)
+
+#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
+#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
+#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
+#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
+#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
+#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
+#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
+#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
+
+/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
+#define __msc_set_cmdat_res_format(r) \
+do { \
+ REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
+ REG_MSC_CMDAT |= (r); \
+} while(0)
+
+#define __msc_clear_cmdat() \
+ REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
+ MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
+ MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
+
+#define __msc_get_imask() ( REG_MSC_IMASK )
+#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
+#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
+#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
+#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
+#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
+#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
+#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
+#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
+#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
+#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
+#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
+#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
+
+/* n=0,1,2,3,4,5,6,7 */
+#define __msc_set_clkrt(n) \
+do { \
+ REG_MSC_CLKRT = n; \
+} while(0)
+
+#define __msc_get_ireg() ( REG_MSC_IREG )
+#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
+#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
+#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
+#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
+#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
+#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
+#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
+#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
+
+#define __msc_get_stat() ( REG_MSC_STAT )
+#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
+#define __msc_stat_crc_err() \
+ ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
+#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
+#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
+#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
+#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
+#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
+
+#define __msc_rd_resfifo() ( REG_MSC_RES )
+#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
+#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
+
+#define __msc_reset() \
+do { \
+ REG_MSC_STRPCL = MSC_STRPCL_RESET; \
+ while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
+} while (0)
+
+#define __msc_start_clk() \
+do { \
+ REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
+} while (0)
+
+#define __msc_stop_clk() \
+do { \
+ REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
+} while (0)
+
+#define MMC_CLK 19169200
+#define SD_CLK 24576000
+
+/* msc_clk should little than pclk and little than clk retrieve from card */
+#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
+do { \
+ unsigned int rate, pclk, i; \
+ pclk = dev_clk; \
+ rate = type?SD_CLK:MMC_CLK; \
+ if (msc_clk && msc_clk < pclk) \
+ pclk = msc_clk; \
+ i = 0; \
+ while (pclk < rate) \
+ { \
+ i ++; \
+ rate >>= 1; \
+ } \
+ lv = i; \
+} while(0)
+
+/* divide rate to little than or equal to 400kHz */
+#define __msc_calc_slow_clk_divisor(type, lv) \
+do { \
+ unsigned int rate, i; \
+ rate = (type?SD_CLK:MMC_CLK)/1000/400; \
+ i = 0; \
+ while (rate > 0) \
+ { \
+ rate >>= 1; \
+ i ++; \
+ } \
+ lv = i; \
+} while(0)
+
+
+/***************************************************************************
+ * SSI
+ ***************************************************************************/
+
+#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
+#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
+#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
+
+#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
+
+#define __ssi_select_ce2() \
+do { \
+ REG_SSI_CR0 |= SSI_CR0_FSEL; \
+ REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
+} while (0)
+
+#define __ssi_select_gpc() \
+do { \
+ REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
+ REG_SSI_CR1 |= SSI_CR1_MULTS; \
+} while (0)
+
+#define __ssi_enable_tx_intr() \
+ ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
+
+#define __ssi_disable_tx_intr() \
+ ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
+
+#define __ssi_enable_rx_intr() \
+ ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
+
+#define __ssi_disable_rx_intr() \
+ ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
+
+#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
+#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
+
+#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
+#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
+
+#define __ssi_finish_receive() \
+ ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
+
+#define __ssi_disable_recvfinish() \
+ ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
+
+#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
+#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
+
+#define __ssi_flush_fifo() \
+ ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
+
+#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
+
+#define __ssi_spi_format() \
+do { \
+ REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
+ REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
+ REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
+ REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
+} while (0)
+
+/* TI's SSP format, must clear SSI_CR1.UNFIN */
+#define __ssi_ssp_format() \
+do { \
+ REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
+ REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
+} while (0)
+
+/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
+#define __ssi_microwire_format() \
+do { \
+ REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
+ REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
+ REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
+ REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
+ REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
+} while (0)
+
+/* CE# level (FRMHL), CE# in interval time (ITFRM),
+ clock phase and polarity (PHA POL),
+ interval time (SSIITR), interval characters/frame (SSIICR) */
+
+ /* frmhl,endian,mcom,flen,pha,pol MASK */
+#define SSICR1_MISC_MASK \
+ ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
+ | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
+
+#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
+do { \
+ REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
+ REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
+ (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
+ ((pha) << 1) | (pol); \
+} while(0)
+
+/* Transfer with MSB or LSB first */
+#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
+#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
+
+#define __ssi_set_frame_length(n) \
+ REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
+
+/* n = 1 - 16 */
+#define __ssi_set_microwire_command_length(n) \
+ ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
+
+/* Set the clock phase for SPI */
+#define __ssi_set_spi_clock_phase(n) \
+ ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) )
+
+/* Set the clock polarity for SPI */
+#define __ssi_set_spi_clock_polarity(n) \
+ ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
+
+/* n = ix8 */
+#define __ssi_set_tx_trigger(n) \
+do { \
+ REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
+ REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \
+} while (0)
+
+/* n = ix8 */
+#define __ssi_set_rx_trigger(n) \
+do { \
+ REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
+ REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \
+} while (0)
+
+#define __ssi_get_txfifo_count() \
+ ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
+
+#define __ssi_get_rxfifo_count() \
+ ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
+
+#define __ssi_clear_errors() \
+ ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
+
+#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
+#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
+
+#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
+#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
+#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF )
+
+#define __ssi_set_clk(dev_clk, ssi_clk) \
+ ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
+
+#define __ssi_receive_data() REG_SSI_DR
+#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
+
+
+/***************************************************************************
+ * CIM
+ ***************************************************************************/
+
+#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
+#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
+
+#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
+#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
+
+#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
+#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
+
+#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
+#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
+
+#define __cim_sample_data_at_pclk_falling_edge() \
+ ( REG_CIM_CFG |= CIM_CFG_PCP )
+#define __cim_sample_data_at_pclk_rising_edge() \
+ ( REG_CIM_CFG &= ~CIM_CFG_PCP )
+
+#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
+#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
+
+#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
+#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
+
+/* n=0-7 */
+#define __cim_set_data_packing_mode(n) \
+do { \
+ REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
+ REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
+} while (0)
+
+#define __cim_enable_ccir656_progressive_mode() \
+do { \
+ REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
+ REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
+} while (0)
+
+#define __cim_enable_ccir656_interlace_mode() \
+do { \
+ REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
+ REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
+} while (0)
+
+#define __cim_enable_gated_clock_mode() \
+do { \
+ REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
+ REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
+} while (0)
+
+#define __cim_enable_nongated_clock_mode() \
+do { \
+ REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
+ REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
+} while (0)
+
+/* sclk:system bus clock
+ * mclk: CIM master clock
+ */
+#define __cim_set_master_clk(sclk, mclk) \
+do { \
+ REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
+ REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
+} while (0)
+
+#define __cim_enable_sof_intr() \
+ ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
+#define __cim_disable_sof_intr() \
+ ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
+
+#define __cim_enable_eof_intr() \
+ ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
+#define __cim_disable_eof_intr() \
+ ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
+
+#define __cim_enable_stop_intr() \
+ ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
+#define __cim_disable_stop_intr() \
+ ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
+
+#define __cim_enable_trig_intr() \
+ ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
+#define __cim_disable_trig_intr() \
+ ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
+
+#define __cim_enable_rxfifo_overflow_intr() \
+ ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
+#define __cim_disable_rxfifo_overflow_intr() \
+ ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
+
+/* n=1-16 */
+#define __cim_set_frame_rate(n) \
+do { \
+ REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
+ REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
+} while (0)
+
+#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
+#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
+
+#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
+#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
+
+/* n=4,8,12,16,20,24,28,32 */
+#define __cim_set_rxfifo_trigger(n) \
+do { \
+ REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
+ REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
+} while (0)
+
+#define __cim_clear_state() ( REG_CIM_STATE = 0 )
+
+#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
+#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
+#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
+#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
+#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
+#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
+#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
+#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
+
+#define __cim_get_iid() ( REG_CIM_IID )
+#define __cim_get_image_data() ( REG_CIM_RXFIFO )
+#define __cim_get_dam_cmd() ( REG_CIM_CMD )
+
+#define __cim_set_da(a) ( REG_CIM_DA = (a) )
+
+/***************************************************************************
+ * LCD
+ ***************************************************************************/
+#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
+#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
+
+#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
+#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
+
+#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
+#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
+
+/* n=1,2,4,8,16 */
+#define __lcd_set_bpp(n) \
+ ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
+
+/* n=4,8,16 */
+#define __lcd_set_burst_length(n) \
+do { \
+ REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
+ REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
+} while (0)
+
+#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
+#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
+
+#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
+#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
+
+/* n=2,4,16 */
+#define __lcd_set_stn_frc(n) \
+do { \
+ REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
+ REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
+} while (0)
+
+
+#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
+#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
+
+#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
+#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
+
+#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
+#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
+
+#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
+#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
+
+#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
+#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
+
+#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
+#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
+
+#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
+#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
+
+#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
+#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
+
+#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
+#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
+
+
+/* LCD status register indication */
+
+#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
+#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
+#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
+#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
+#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
+#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
+#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
+
+#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
+#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
+#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
+
+#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
+#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
+
+/* n=1,2,4,8 for single mono-STN
+ * n=4,8 for dual mono-STN
+ */
+#define __lcd_set_panel_datawidth(n) \
+do { \
+ REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
+ REG_LCD_CFG |= LCD_CFG_PDW_n##; \
+} while (0)
+
+/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
+#define __lcd_set_panel_mode(m) \
+do { \
+ REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
+ REG_LCD_CFG |= (m); \
+} while(0)
+
+/* n = 0-255 */
+#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
+#define __lcd_set_ac_bias(n) \
+do { \
+ REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
+ REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
+} while(0)
+
+#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
+#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
+
+#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
+#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
+
+#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
+#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
+
+#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
+#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
+
+#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
+#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
+
+#define __lcd_vsync_get_vps() \
+ ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
+
+#define __lcd_vsync_get_vpe() \
+ ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
+#define __lcd_vsync_set_vpe(n) \
+do { \
+ REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
+ REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
+} while (0)
+
+#define __lcd_hsync_get_hps() \
+ ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
+#define __lcd_hsync_set_hps(n) \
+do { \
+ REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
+ REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
+} while (0)
+
+#define __lcd_hsync_get_hpe() \
+ ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
+#define __lcd_hsync_set_hpe(n) \
+do { \
+ REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
+ REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
+} while (0)
+
+#define __lcd_vat_get_ht() \
+ ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
+#define __lcd_vat_set_ht(n) \
+do { \
+ REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
+ REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
+} while (0)
+
+#define __lcd_vat_get_vt() \
+ ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
+#define __lcd_vat_set_vt(n) \
+do { \
+ REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
+ REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
+} while (0)
+
+#define __lcd_dah_get_hds() \
+ ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
+#define __lcd_dah_set_hds(n) \
+do { \
+ REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
+ REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
+} while (0)
+
+#define __lcd_dah_get_hde() \
+ ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
+#define __lcd_dah_set_hde(n) \
+do { \
+ REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
+ REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
+} while (0)
+
+#define __lcd_dav_get_vds() \
+ ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
+#define __lcd_dav_set_vds(n) \
+do { \
+ REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
+ REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
+} while (0)
+
+#define __lcd_dav_get_vde() \
+ ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
+#define __lcd_dav_set_vde(n) \
+do { \
+ REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
+ REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
+} while (0)
+
+#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
+#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
+#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
+#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
+
+#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
+#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
+#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
+#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
+
+#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
+#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
+
+#define __lcd_cmd0_get_len() \
+ ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
+#define __lcd_cmd1_get_len() \
+ ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
+
+/***************************************************************************
+ * RTC ops
+ ***************************************************************************/
+
+#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY )
+#define __rtc_enabled() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR |= RTC_RCR_RTCE ; \
+}while(0) \
+
+#define __rtc_disabled() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR &= ~RTC_RCR_RTCE; \
+}while(0)
+#define __rtc_enable_alarm() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR |= RTC_RCR_AE; \
+}while(0)
+
+#define __rtc_disable_alarm() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR &= ~RTC_RCR_AE; \
+}while(0)
+
+#define __rtc_enable_alarm_irq() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR |= RTC_RCR_AIE; \
+}while(0)
+
+#define __rtc_disable_alarm_irq() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR &= ~RTC_RCR_AIE; \
+}while(0)
+#define __rtc_enable_Hz_irq() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR |= RTC_RCR_HZIE; \
+}while(0)
+
+#define __rtc_disable_Hz_irq() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR &= ~RTC_RCR_HZIE; \
+}while(0)
+#define __rtc_get_1Hz_flag() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
+}while(0)
+#define __rtc_clear_1Hz_flag() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR &= ~RTC_RCR_HZ; \
+}while(0)
+#define __rtc_get_alarm_flag() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1); \
+while(0)
+
+///( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 )
+
+#define __rtc_clear_alarm_flag() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RCR &= ~RTC_RCR_AF; \
+}while(0)
+//do
+#define __rtc_get_second() \
+({ \
+ while(!__rtc_write_ready());\
+ REG_RTC_RSR; \
+})
+//while(0)
+
+#define __rtc_set_second(v) \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RSR = v; \
+ while(!__rtc_write_ready());\
+}while(0)
+
+#define __rtc_get_alarm_second() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RSAR; \
+}while(0)
+
+
+#define __rtc_set_alarm_second(v) \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RSAR = v; \
+}while(0)
+
+#define __rtc_RGR_is_locked() \
+({ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RGR >> RTC_RGR_LOCK; \
+})
+#define __rtc_lock_RGR() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RGR |= RTC_RGR_LOCK; \
+}while(0)
+
+#define __rtc_unlock_RGR() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RGR &= ~RTC_RGR_LOCK; \
+}while(0)
+
+#define __rtc_get_adjc_val() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
+}while(0)
+#define __rtc_set_adjc_val(v) \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_ADJC_MASK)) |(v << RTC_RGR_ADJC_BIT); \
+}while(0)
+
+#define __rtc_get_nc1Hz_val() \
+ ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
+
+#define __rtc_set_nc1Hz_val(v) \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_NC1HZ_MASK)) | (v << RTC_RGR_NC1HZ_BIT);\
+}while(0)
+#define __rtc_power_down() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_HCR |= RTC_HCR_PD; \
+}while(0)
+
+#define __rtc_get_hwfcr_val() \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_HWFCR & RTC_HWFCR_MASK; \
+}while(0)
+#define __rtc_set_hwfcr_val(v) \
+do{ \
+ while(!__rtc_write_ready()); \
+ REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
+}while(0)
+
+#define __rtc_get_hrcr_val() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
+}while(0)
+#define __rtc_set_hrcr_val(v) \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
+}while(0)
+
+#define __rtc_enable_alarm_wakeup() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
+}while(0)
+
+#define __rtc_disable_alarm_wakeup() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
+}while(0)
+
+#define __rtc_status_hib_reset_occur() \
+({ \
+ (REG_RTC_HWRSR & RTC_HWRSR_HR); \
+})
+#define __rtc_status_ppr_reset_occur() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( (REG_RTC_HWRSR & RTC_HWRSR_PPR) & 0x1 ); \
+}while(0)
+#define __rtc_status_wakeup_pin_waken_up() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
+}while(0)
+#define __rtc_status_alarm_waken_up() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
+}while(0)
+#define __rtc_clear_hib_stat_all() \
+do{ \
+ while(!__rtc_write_ready()); \
+ ( REG_RTC_HWRSR = 0 ); \
+}while(0)
+
+#define __rtc_get_scratch_pattern() \
+({ while(!__rtc_write_ready()); \
+ (REG_RTC_HSPR);})
+#define __rtc_set_scratch_pattern(n) \
+do{ \
+ while(!__rtc_write_ready()); \
+ (REG_RTC_HSPR = n ); \
+}while(0)
+
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __JZ4740_H__ */
diff --git a/firmware/export/mips-archdefs.h b/firmware/export/mips-archdefs.h
new file mode 100755
index 0000000000..37c61b87e5
--- /dev/null
+++ b/firmware/export/mips-archdefs.h
@@ -0,0 +1,2356 @@
+/**************************************************************************
+* *
+* PROJECT : MIPS port for uC/OS-II *
+* *
+* MODULE : ARCHDEFS.h *
+* *
+* AUTHOR : Michael Anburaj *
+* URL : http://geocities.com/michaelanburaj/ *
+* EMAIL: michaelanburaj@hotmail.com *
+* *
+* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board *
+* *
+* TOOL-CHAIN : SDE & Cygnus *
+* *
+* DESCRIPTION : *
+* Architecture definitions. *
+* *
+**************************************************************************/
+
+
+#ifndef __ARCHDEFS_H__
+#define __ARCHDEFS_H__
+
+
+/* ********************************************************************* */
+/* Module configuration */
+
+
+/* ********************************************************************* */
+/* Interface macro & data definition */
+
+/*
+ * Utility defines for cross platform handling of 64bit constants.
+ */
+
+#if !defined(Append)
+ #define Append(c,s) (c##s)
+#endif
+
+#if !defined(__assembler) && !defined(MIPSAVPENV)
+ #if defined(NT)
+ #if !defined(UNS64Const)
+ #define UNS64Const(c) Append(c,ui64)
+ #endif
+
+ #if !defined(INT64Const)
+ #define INT64Const(c) Append(c,i64)
+ #endif
+ #else
+ #if !defined(UNS64Const)
+ #define UNS64Const(c) Append(c,ull)
+ #endif
+
+ #if !defined(INT64Const)
+ #define INT64Const(c) Append(c,ll)
+ #endif
+ #endif
+#else /* Not C or C++ */
+ #if !defined(UNS64Const)
+ #define UNS64Const(c) c
+ #endif
+
+ #if !defined(INT64Const)
+ #define INT64Const(c) c
+ #endif
+#endif /* C or C++ */
+
+
+/*
+ ************************************************************************
+ * I N S T R U C T I O N F O R M A T S *
+ ************************************************************************
+ *
+ * The following definitions describe each field in an instruction. There
+ * is one diagram for each type of instruction, with field definitions
+ * following the diagram for that instruction. Note that if a field of
+ * the same name and position is defined in an earlier diagram, it is
+ * not defined again in the subsequent diagram. Only new fields are
+ * defined for each diagram.
+ *
+ * R-Type (operate)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | | rs | rt | rd | sa | |
+ * | Opcode | | | Tcode | func |
+ * | | Bcode | | sel |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnOpcode 26
+#define M_InstnOpcode (0x3f << S_InstnOpcode)
+#define S_InstnRS 21
+#define M_InstnRS (0x1f << S_InstnRS)
+#define S_InstnRT 16
+#define M_InstnRT (0x1f << S_InstnRT)
+#define S_InstnRD 11
+#define M_InstnRD (0x1f << S_InstnRD)
+#define S_InstnSA 6
+#define M_InstnSA (0x1f << S_InstnSA)
+#define S_InstnTcode 6
+#define M_InstnTcode (0x3ff << S_InstnTcode)
+#define S_InstnBcode 6
+#define M_InstnBcode (0xfffff << S_InstnBcode)
+#define S_InstnFunc 0
+#define M_InstnFunc (0x3f << S_InstnFunc)
+#define S_InstnSel 0
+#define M_InstnSel (0x7 << S_InstnSel)
+
+/*
+ * I-Type (load, store, branch, immediate)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | rs | rt | Offset |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnOffset 0
+#define M_InstnOffset (0xffff << S_InstnOffset)
+
+/*
+ * I-Type (pref)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | rs | hint | Offset |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnHint S_InstnRT
+#define M_InstnHint M_InstnRT
+
+/*
+ * J-Type (jump)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | JIndex |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnJIndex 0
+#define M_InstnJIndex (0x03ffffff << S_InstnJIndex)
+
+/*
+ * FP R-Type (operate)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | fmt | ft | fs | fd | func |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnFmt S_InstnRS
+#define M_InstnFmt M_InstnRS
+#define S_InstnFT S_InstnRT
+#define M_InstnFT M_InstnRT
+#define S_InstnFS S_InstnRD
+#define M_InstnFS M_InstnRD
+#define S_InstnFD S_InstnSA
+#define M_InstnFD M_InstnSA
+
+/*
+ * FP R-Type (cpu <-> cpu data movement))
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | sub | rt | fs | 0 |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnSub S_InstnRS
+#define M_InstnSub M_InstnRS
+
+/*
+ * FP R-Type (compare)
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | | | | | | |C| |
+ * | Opcode | fmt | ft | fs | cc |0|A| func |
+ * | | | | | | |B| |
+ * | | | | | | |S| |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnCCcmp 8
+#define M_InstnCCcmp (0x7 << S_InstnCCcmp)
+#define S_InstnCABS 6
+#define M_InstnCABS (0x1 << S_InstnCABS)
+
+/*
+ * FP R-Type (FPR conditional move on FP cc)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | fmt | cc |n|t| fs | fd | func |
+ * | | | |d|f| | | |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnCC 18
+#define M_InstnCC (0x7 << S_InstnCC)
+#define S_InstnND 17
+#define M_InstnND (0x1 << S_InstnND)
+#define S_InstnTF 16
+#define M_InstnTF (0x1 << S_InstnTF)
+
+/*
+ * FP R-Type (3-operand operate)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | fr | ft | fs | fd | op4 | fmt3|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnFR S_InstnRS
+#define M_InstnFR M_InstnRS
+#define S_InstnOp4 3
+#define M_InstnOp4 (0x7 << S_InstnOp4)
+#define S_InstnFmt3 0
+#define M_InstnFmt3 (0x7 << S_InstnFmt3)
+
+/*
+ * FP R-Type (Indexed load, store)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | rs | rt | 0 | fd | func |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+/*
+ * FP R-Type (prefx)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | rs | rt | hint | 0 | func |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnHintX S_InstnRD
+#define M_InstnHintX M_InstnRD
+
+/*
+ * FP R-Type (GPR conditional move on FP cc)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | rs | cc |n|t| rd | 0 | func |
+ * | | | |d|f| | | |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+/*
+ * FP I-Type (load, store)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | rs | ft | Offset |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+/*
+ * FP I-Type (branch)
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opcode | fmt | cc |n|t| Offset |
+ * | | | |d|f| |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+
+/*
+ *************************************************************************
+ * V I R T U A L A D D R E S S D E F I N I T I O N S *
+ *************************************************************************
+ */
+
+#ifdef MIPSADDR64
+#define A_K0BASE UNS64Const(0xffffffff80000000)
+#define A_K1BASE UNS64Const(0xffffffffa0000000)
+#define A_K2BASE UNS64Const(0xffffffffc0000000)
+#define A_K3BASE UNS64Const(0xffffffffe0000000)
+#define A_REGION UNS64Const(0xc000000000000000)
+#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000)
+#else
+#define A_K0BASE 0x80000000
+#define A_K1BASE 0xa0000000
+#define A_K2BASE 0xc0000000
+#define A_K3BASE 0xe0000000
+#endif
+#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */
+
+
+#ifdef MIPS_Model64
+
+#define S_VMAP64 62
+#define M_VMAP64 UNS64Const(0xc000000000000000)
+
+#define K_VMode11 3
+#define K_VMode10 2
+#define K_VMode01 1
+#define K_VMode00 0
+
+#define S_KSEG3 29
+#define M_KSEG3 (0x7 << S_KSEG3)
+#define K_KSEG3 7
+
+#define S_SSEG 29
+#define M_SSEG (0x7 << S_KSEG3)
+#define K_SSEG 6
+
+#define S_KSSEG 29
+#define M_KSSEG (0x7 << S_KSEG3)
+#define K_KSSEG 6
+
+#define S_KSEG1 29
+#define M_KSEG1 (0x7 << S_KSEG3)
+#define K_KSEG1 5
+
+#define S_KSEG0 29
+#define M_KSEG0 (0x7 << S_KSEG3)
+#define K_KSEG0 4
+
+#define S_XKSEG 29
+#define M_XKSEG (0x7 << S_KSEG3)
+#define K_XKSEG 3
+
+#define S_USEG 31
+#define M_USEG (0x1 << S_USEG)
+#define K_USEG 0
+
+#define S_EjtagProbeMem 20
+#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem)
+#define K_EjtagProbeMem 0
+
+
+
+#else
+
+#define S_KSEG3 29
+#define M_KSEG3 (0x7 << S_KSEG3)
+#define K_KSEG3 7
+
+#define S_KSSEG 29
+#define M_KSSEG (0x7 << S_KSSEG)
+#define K_KSSEG 6
+
+#define S_SSEG 29
+#define M_SSEG (0x7 << S_SSEG)
+#define K_SSEG 6
+
+#define S_KSEG1 29
+#define M_KSEG1 (0x7 << S_KSEG1)
+#define K_KSEG1 5
+
+#define S_KSEG0 29
+#define M_KSEG0 (0x7 << S_KSEG0)
+#define K_KSEG0 4
+
+#define S_KUSEG 31
+#define M_KUSEG (0x1 << S_KUSEG)
+#define K_KUSEG 0
+
+#define S_SUSEG 31
+#define M_SUSEG (0x1 << S_SUSEG)
+#define K_SUSEG 0
+
+#define S_USEG 31
+#define M_USEG (0x1 << S_USEG)
+#define K_USEG 0
+
+#define K_EjtagLower 0xff200000
+#define K_EjtagUpper 0xff3fffff
+
+#define S_EjtagProbeMem 20
+#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem)
+#define K_EjtagProbeMem 0
+
+#endif
+
+
+
+/*
+ *************************************************************************
+ * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S *
+ *************************************************************************
+ */
+
+/*
+ * Cache encodings
+ */
+#define K_CachePriI 0 /* Primary Icache */
+#define K_CachePriD 1 /* Primary Dcache */
+#define K_CachePriU 1 /* Unified primary */
+#define K_CacheTerU 2 /* Unified Tertiary */
+#define K_CacheSecU 3 /* Unified secondary */
+
+
+/*
+ * Function encodings
+ */
+#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */
+#define K_CacheIndexInv 0 /* Index invalidate */
+#define K_CacheIndexWBInv 0 /* Index writeback invalidate */
+#define K_CacheIndexLdTag 1 /* Index load tag */
+#define K_CacheIndexStTag 2 /* Index store tag */
+#define K_CacheHitInv 4 /* Hit Invalidate */
+#define K_CacheFill 5 /* Fill (Icache only) */
+#define K_CacheHitWBInv 5 /* Hit writeback invalidate */
+#define K_CacheHitWB 6 /* Hit writeback */
+#define K_CacheFetchLock 7 /* Fetch and lock */
+
+#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
+#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
+#define DCIndexInv DCIndexWBInv
+#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
+#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
+#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
+#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
+#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
+#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
+#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI)
+#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
+#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
+#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
+#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)
+
+
+/*
+ *************************************************************************
+ * P R E F E T C H I N S T R U C T I O N H I N T S *
+ *************************************************************************
+ */
+
+#define PrefLoad 0
+#define PrefStore 1
+#define PrefLoadStreamed 4
+#define PrefStoreStreamed 5
+#define PrefLoadRetained 6
+#define PrefStoreRetained 7
+#define PrefWBInval 25
+#define PrefNudge 25
+
+
+/*
+ *************************************************************************
+ * C P U R E G I S T E R D E F I N I T I O N S *
+ *************************************************************************
+ */
+
+
+/*
+ *************************************************************************
+ * S O F T W A R E G P R N A M E S *
+ *************************************************************************
+ */
+
+#define zero $0
+#define AT $1
+#define v0 $2
+#define v1 $3
+#define a0 $4
+#define a1 $5
+#define a2 $6
+#define a3 $7
+#define t0 $8
+#define t1 $9
+#define t2 $10
+#define t3 $11
+#define t4 $12
+#define t5 $13
+#define t6 $14
+#define t7 $15
+#define s0 $16
+#define s1 $17
+#define s2 $18
+#define s3 $19
+#define s4 $20
+#define s5 $21
+#define s6 $22
+#define s7 $23
+#define t8 $24
+#define t9 $25
+#define k0 $26
+#define k1 $27
+#define gp $28
+#define sp $29
+#define fp $30
+#define ra $31
+
+/*
+ * The following registers are used by the AVP environment and
+ * are not part of the normal software definitions.
+ */
+
+#ifdef MIPSAVPENV
+#define repc $25 /* Expected exception PC */
+#define tid $30 /* Current test case address */
+#endif
+
+
+/*
+ *************************************************************************
+ * H A R D W A R E G P R N A M E S *
+ *************************************************************************
+ *
+ * In the AVP environment, several of the `r' names are removed from the
+ * name space because they are used by the kernel for special purposes.
+ * Removing them causes assembly rather than runtime errors for tests that
+ * use the `r' names.
+ *
+ * - r25 (repc) is used as the expected PC on an exception
+ * - r26-r27 (k0, k1) are used in the exception handler
+ * - r30 (tid) is used as the current test address
+ */
+
+#define r0 $0
+#define r1 $1
+#define r2 $2
+#define r3 $3
+#define r4 $4
+#define r5 $5
+#define r6 $6
+#define r7 $7
+#define r8 $8
+#define r9 $9
+#define r10 $10
+#define r11 $11
+#define r12 $12
+#define r13 $13
+#define r14 $14
+#define r15 $15
+#define r16 $16
+#define r17 $17
+#define r18 $18
+#define r19 $19
+#define r20 $20
+#define r21 $21
+#define r22 $22
+#define r23 $23
+#define r24 $24
+#ifdef MIPSAVPENV
+#define r25 r25_unknown
+#define r26 r26_unknown
+#define r27 r27_unknown
+#else
+#define r25 $25
+#define r26 $26
+#define r27 $27
+#endif
+#define r28 $28
+#define r29 $29
+#ifdef MIPSAVPENV
+#define r30 r30_unknown
+#else
+#define r30 $30
+#endif
+#define r31 $31
+
+
+/*
+ *************************************************************************
+ * H A R D W A R E G P R I N D I C E S *
+ *************************************************************************
+ *
+ * These definitions provide the index (number) of the GPR, as opposed
+ * to the assembler register name ($n).
+ */
+
+#define R_r0 0
+#define R_r1 1
+#define R_r2 2
+#define R_r3 3
+#define R_r4 4
+#define R_r5 5
+#define R_r6 6
+#define R_r7 7
+#define R_r8 8
+#define R_r9 9
+#define R_r10 10
+#define R_r11 11
+#define R_r12 12
+#define R_r13 13
+#define R_r14 14
+#define R_r15 15
+#define R_r16 16
+#define R_r17 17
+#define R_r18 18
+#define R_r19 19
+#define R_r20 20
+#define R_r21 21
+#define R_r22 22
+#define R_r23 23
+#define R_r24 24
+#define R_r25 25
+#define R_r26 26
+#define R_r27 27
+#define R_r28 28
+#define R_r29 29
+#define R_r30 30
+#define R_r31 31
+#define R_hi 32 /* Hi register */
+#define R_lo 33 /* Lo register */
+
+
+/*
+ *************************************************************************
+ * S O F T W A R E G P R M A S K S *
+ *************************************************************************
+ *
+ * These definitions provide the bit mask corresponding to the GPR number
+ */
+
+#define M_AT (1<<1)
+#define M_v0 (1<<2)
+#define M_v1 (1<<3)
+#define M_a0 (1<<4)
+#define M_a1 (1<<5)
+#define M_a2 (1<<6)
+#define M_a3 (1<<7)
+#define M_t0 (1<<8)
+#define M_t1 (1<<9)
+#define M_t2 (1<<10)
+#define M_t3 (1<<11)
+#define M_t4 (1<<12)
+#define M_t5 (1<<13)
+#define M_t6 (1<<14)
+#define M_t7 (1<<15)
+#define M_s0 (1<<16)
+#define M_s1 (1<<17)
+#define M_s2 (1<<18)
+#define M_s3 (1<<19)
+#define M_s4 (1<<20)
+#define M_s5 (1<<21)
+#define M_s6 (1<<22)
+#define M_s7 (1<<23)
+#define M_t8 (1<<24)
+#define M_t9 (1<<25)
+#define M_k0 (1<<26)
+#define M_k1 (1<<27)
+#define M_gp (1<<28)
+#define M_sp (1<<29)
+#define M_fp (1<<30)
+#define M_ra (1<<31)
+
+
+/*
+ *************************************************************************
+ * C P 0 R E G I S T E R D E F I N I T I O N S *
+ *************************************************************************
+ * Each register has the following definitions:
+ *
+ * C0_rrr The register number (as a $n value)
+ * R_C0_rrr The register index (as an integer corresponding
+ * to the register number)
+ *
+ * Each field in a register has the following definitions:
+ *
+ * S_rrrfff The shift count required to right-justify
+ * the field. This corresponds to the bit
+ * number of the right-most bit in the field.
+ * M_rrrfff The Mask required to isolate the field.
+ *
+ * Register diagrams included below as comments correspond to the
+ * MIPS32 and MIPS64 architecture specifications. Refer to other
+ * sources for register diagrams for older architectures.
+ */
+
+
+/*
+ ************************************************************************
+ * I N D E X R E G I S T E R ( 0 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |P| 0 | Index | Index
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Index $0
+#define R_C0_Index 0
+#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_IndexP 31 /* Probe failure (R)*/
+#define M_IndexP (0x1 << S_IndexP)
+
+#define S_IndexIndex 0 /* TLB index (R/W)*/
+#define M_IndexIndex (0x3f << S_IndexIndex)
+
+#define M_Index0Fields 0x7fffffc0
+#define M_IndexRFields 0x80000000
+
+
+/*
+ ************************************************************************
+ * R A N D O M R E G I S T E R ( 1 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | 0 | Index | Random
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Random $1
+#define R_C0_Random 1
+#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_RandomIndex 0 /* TLB random index (R)*/
+#define M_RandomIndex (0x3f << S_RandomIndex)
+
+#define M_Random0Fields 0xffffffc0
+#define M_RandomRFields 0x0000003f
+
+
+/*
+ ************************************************************************
+ * E N T R Y L O 0 R E G I S T E R ( 2 ) *
+ ************************************************************************
+ *
+ * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_EntryLo0 $2
+#define R_C0_EntryLo0 2
+#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_EntryLoPFN 6 /* PFN (R/W) */
+#define M_EntryLoPFN (0xffffff << S_EntryLoPFN)
+#define S_EntryLoC 3 /* Coherency attribute (R/W) */
+#define M_EntryLoC (0x7 << S_EntryLoC)
+#define S_EntryLoD 2 /* Dirty (R/W) */
+#define M_EntryLoD (0x1 << S_EntryLoD)
+#define S_EntryLoV 1 /* Valid (R/W) */
+#define M_EntryLoV (0x1 << S_EntryLoV)
+#define S_EntryLoG 0 /* Global (R/W) */
+#define M_EntryLoG (0x1 << S_EntryLoG)
+#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */
+#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */
+#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */
+
+#define M_EntryLo0Fields 0x00000000
+#define M_EntryLoRFields 0xc0000000
+#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000)
+#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000)
+
+/*
+ * Cache attribute values in the C field of EntryLo and the
+ * K0 field of Config
+ */
+#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */
+#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */
+#define K_CacheAttrU 2 /* Uncached */
+#define K_CacheAttrC 3 /* Cacheable */
+#define K_CacheAttrCN 3 /* Cacheable, non-coherent */
+#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */
+#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */
+#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */
+#define K_CacheAttrUA 7 /* Uncached accelerated */
+
+
+/*
+ ************************************************************************
+ * E N T R Y L O 1 R E G I S T E R ( 3 ) *
+ ************************************************************************
+ *
+ * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_EntryLo1 $3
+#define R_C0_EntryLo1 3
+#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+/*
+ * Field definitions are as given for EntryLo0 above
+ */
+
+
+/*
+ ************************************************************************
+ * C O N T E X T R E G I S T E R ( 4 ) *
+ ************************************************************************
+ *
+ * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // PTEBase | BadVPN<31:13> | 0 | Context
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Context $4
+#define R_C0_Context 4
+#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_ContextPTEBase 23 /* PTE base (R/W) */
+#define M_ContextPTEBase (0x1ff << S_ContextPTEBase)
+#define S_ContextBadVPN 4 /* BadVPN2 (R) */
+#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN)
+#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */
+#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */
+
+#define M_Context0Fields 0x0000000f
+#define M_ContextRFields 0x007ffff0
+#define M_Context0Fields64 UNS64Const(0x000000000000000f)
+#define M_ContextRFields64 UNS64Const(0x00000000007ffff0)
+
+
+/*
+ ************************************************************************
+ * P A G E M A S K R E G I S T E R ( 5 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | 0 | Mask | 0 | PageMask
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_PageMask $5
+#define R_C0_PageMask 5 /* Mask (R/W) */
+#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_PageMaskMask 13
+#define M_PageMaskMask (0xfff << S_PageMaskMask)
+
+#define M_PageMask0Fields 0xfe001fff
+#define M_PageMaskRFields 0x00000000
+
+/*
+ * Values in the Mask field
+ */
+#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */
+#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */
+#define K_PageMask64K 0x00f
+#define K_PageMask256K 0x03f
+#define K_PageMask1M 0x0ff
+#define K_PageMask4M 0x3ff
+#define K_PageMask16M 0xfff
+
+#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */
+#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */
+#define M_PageMask64K (K_PageMask64K << S_PageMaskMask)
+#define M_PageMask256K (K_PageMask256K << S_PageMaskMask)
+#define M_PageMask1M (K_PageMask1M << S_PageMaskMask)
+#define M_PageMask4M (K_PageMask4M << S_PageMaskMask)
+#define M_PageMask16M (K_PageMask16M << S_PageMaskMask)
+
+
+/*
+ ************************************************************************
+ * W I R E D R E G I S T E R ( 6 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | 0 | Index | Wired
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Wired $6
+#define R_C0_Wired 6
+#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_WiredIndex 0 /* TLB wired boundary (R/W) */
+#define M_WiredIndex (0x3f << S_WiredIndex)
+
+#define M_Wired0Fields 0xffffffc0
+#define M_WiredRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * B A D V A D D R R E G I S T E R ( 8 ) *
+ ************************************************************************
+ *
+ * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // Bad Virtual Address | BadVAddr
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_BadVAddr $8
+#define R_C0_BadVAddr 8
+#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */
+
+#define M_BadVAddr0Fields 0x00000000
+#define M_BadVAddrRFields 0xffffffff
+#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000)
+#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff)
+
+/*
+ ************************************************************************
+ * C O U N T R E G I S T E R ( 9 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Count Value | Count
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Count $9
+#define R_C0_Count 9
+#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_Count0Fields 0x00000000
+#define M_CountRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * E N T R Y H I R E G I S T E R ( 1 0 ) *
+ ************************************************************************
+ *
+ * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | R | Fill // VPN2 | 0 | ASID | EntryHi
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_EntryHi $10
+#define R_C0_EntryHi 10
+#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_EntryHiR64 62 /* Region (R/W) */
+#define M_EntryHiR64 UNS64Const(0xc000000000000000)
+#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */
+#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2)
+#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000)
+#define S_EntryHiASID 0 /* ASID (R/W) */
+#define M_EntryHiASID (0xff << S_EntryHiASID)
+#define S_EntryHiVPN_Shf S_EntryHiVPN2
+
+#define M_EntryHi0Fields 0x00001f00
+#define M_EntryHiRFields 0x00000000
+#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00)
+#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000)
+
+
+/*
+ ************************************************************************
+ * C O M P A R E R E G I S T E R ( 1 1 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Compare Value | Compare
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Compare $11
+#define R_C0_Compare 11
+#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_Compare0Fields 0x00000000
+#define M_CompareRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * S T A T U S R E G I S T E R ( 1 2 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I|
+ * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status
+ * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Status $12
+#define R_C0_Status 12
+#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_StatusCU 28 /* Coprocessor enable (R/W) */
+#define M_StatusCU (0xf << S_StatusCU)
+#define S_StatusCU3 31
+#define M_StatusCU3 (0x1 << S_StatusCU3)
+#define S_StatusCU2 30
+#define M_StatusCU2 (0x1 << S_StatusCU2)
+#define S_StatusCU1 29
+#define M_StatusCU1 (0x1 << S_StatusCU1)
+#define S_StatusCU0 28
+#define M_StatusCU0 (0x1 << S_StatusCU0)
+#define S_StatusRP 27 /* Enable reduced power mode (R/W) */
+#define M_StatusRP (0x1 << S_StatusRP)
+#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */
+#define M_StatusFR (0x1 << S_StatusFR)
+#define S_StatusRE 25 /* Enable reverse endian (R/W) */
+#define M_StatusRE (0x1 << S_StatusRE)
+#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */
+#define M_StatusMX (0x1 << S_StatusMX)
+#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */
+#define M_StatusPX (0x1 << S_StatusPX)
+#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */
+#define M_StatusBEV (0x1 << S_StatusBEV)
+#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */
+#define M_StatusTS (0x1 << S_StatusTS)
+#define S_StatusSR 20 /* Denote soft reset (R/W) */
+#define M_StatusSR (0x1 << S_StatusSR)
+#define S_StatusNMI 19
+#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */
+#define S_StatusIM 8 /* Interrupt mask (R/W) */
+#define M_StatusIM (0xff << S_StatusIM)
+#define S_StatusIM7 15
+#define M_StatusIM7 (0x1 << S_StatusIM7)
+#define S_StatusIM6 14
+#define M_StatusIM6 (0x1 << S_StatusIM6)
+#define S_StatusIM5 13
+#define M_StatusIM5 (0x1 << S_StatusIM5)
+#define S_StatusIM4 12
+#define M_StatusIM4 (0x1 << S_StatusIM4)
+#define S_StatusIM3 11
+#define M_StatusIM3 (0x1 << S_StatusIM3)
+#define S_StatusIM2 10
+#define M_StatusIM2 (0x1 << S_StatusIM2)
+#define S_StatusIM1 9
+#define M_StatusIM1 (0x1 << S_StatusIM1)
+#define S_StatusIM0 8
+#define M_StatusIM0 (0x1 << S_StatusIM0)
+#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */
+#define M_StatusKX (0x1 << S_StatusKX)
+#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */
+#define M_StatusSX (0x1 << S_StatusSX)
+#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */
+#define M_StatusUX (0x1 << S_StatusUX)
+#define S_StatusKSU 3 /* Two-bit current mode (R/W) */
+#define M_StatusKSU (0x3 << S_StatusKSU)
+#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */
+#define M_StatusUM (0x1 << S_StatusUM)
+#define S_StatusSM 3 /* Supervisor mode (R/W) */
+#define M_StatusSM (0x1 << S_StatusSM)
+#define S_StatusERL 2 /* Denotes error level (R/W) */
+#define M_StatusERL (0x1 << S_StatusERL)
+#define S_StatusEXL 1 /* Denotes exception level (R/W) */
+#define M_StatusEXL (0x1 << S_StatusEXL)
+#define S_StatusIE 0 /* Enables interrupts (R/W) */
+#define M_StatusIE (0x1 << S_StatusIE)
+
+#define M_Status0Fields 0x00040000
+#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */
+#define M_Status0Fields64 0x00040000
+#define M_StatusRFields64 0x00000000
+
+/*
+ * Values in the KSU field
+ */
+#define K_StatusKSU_U 2 /* User mode in KSU field */
+#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */
+#define K_StatusKSU_K 0 /* Kernel mode in KSU field */
+
+
+/*
+ ************************************************************************
+ * C A U S E R E G I S T E R ( 1 3 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R |
+ * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause
+ * | | | | | | | |7|6|5|4|3|2|1|0| | | v |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Cause $13
+#define R_C0_Cause 13
+#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_CauseBD 31
+#define M_CauseBD (0x1 << S_CauseBD)
+#define S_CauseCE 28
+#define M_CauseCE (0x3<< S_CauseCE)
+#define S_CauseIV 23
+#define M_CauseIV (0x1 << S_CauseIV)
+#define S_CauseWP 22
+#define M_CauseWP (0x1 << S_CauseWP)
+#define S_CauseIP 8
+#define M_CauseIP (0xff << S_CauseIP)
+#define S_CauseIPEXT 10
+#define M_CauseIPEXT (0x3f << S_CauseIPEXT)
+#define S_CauseIP7 15
+#define M_CauseIP7 (0x1 << S_CauseIP7)
+#define S_CauseIP6 14
+#define M_CauseIP6 (0x1 << S_CauseIP6)
+#define S_CauseIP5 13
+#define M_CauseIP5 (0x1 << S_CauseIP5)
+#define S_CauseIP4 12
+#define M_CauseIP4 (0x1 << S_CauseIP4)
+#define S_CauseIP3 11
+#define M_CauseIP3 (0x1 << S_CauseIP3)
+#define S_CauseIP2 10
+#define M_CauseIP2 (0x1 << S_CauseIP2)
+#define S_CauseIP1 9
+#define M_CauseIP1 (0x1 << S_CauseIP1)
+#define S_CauseIP0 8
+#define M_CauseIP0 (0x1 << S_CauseIP0)
+#define S_CauseExcCode 2
+#define M_CauseExcCode (0x1f << S_CauseExcCode)
+
+#define M_Cause0Fields 0x4f3f0083
+#define M_CauseRFields 0xb000fc7c
+
+/*
+ * Values in the CE field
+ */
+#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */
+#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */
+#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */
+#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */
+
+/*
+ * Values in the ExcCode field
+ */
+#define EX_INT 0 /* Interrupt */
+#define EXC_INT (EX_INT << S_CauseExcCode)
+#define EX_MOD 1 /* TLB modified */
+#define EXC_MOD (EX_MOD << S_CauseExcCode)
+#define EX_TLBL 2 /* TLB exception (load or ifetch) */
+#define EXC_TLBL (EX_TLBL << S_CauseExcCode)
+#define EX_TLBS 3 /* TLB exception (store) */
+#define EXC_TLBS (EX_TLBS << S_CauseExcCode)
+#define EX_ADEL 4 /* Address error (load or ifetch) */
+#define EXC_ADEL (EX_ADEL << S_CauseExcCode)
+#define EX_ADES 5 /* Address error (store) */
+#define EXC_ADES (EX_ADES << S_CauseExcCode)
+#define EX_IBE 6 /* Instruction Bus Error */
+#define EXC_IBE (EX_IBE << S_CauseExcCode)
+#define EX_DBE 7 /* Data Bus Error */
+#define EXC_DBE (EX_DBE << S_CauseExcCode)
+#define EX_SYS 8 /* Syscall */
+#define EXC_SYS (EX_SYS << S_CauseExcCode)
+#define EX_SYSCALL EX_SYS
+#define EXC_SYSCALL EXC_SYS
+#define EX_BP 9 /* Breakpoint */
+#define EXC_BP (EX_BP << S_CauseExcCode)
+#define EX_BREAK EX_BP
+#define EXC_BREAK EXC_BP
+#define EX_RI 10 /* Reserved instruction */
+#define EXC_RI (EX_RI << S_CauseExcCode)
+#define EX_CPU 11 /* CoProcessor Unusable */
+#define EXC_CPU (EX_CPU << S_CauseExcCode)
+#define EX_OV 12 /* OVerflow */
+#define EXC_OV (EX_OV << S_CauseExcCode)
+#define EX_TR 13 /* Trap instruction */
+#define EXC_TR (EX_TR << S_CauseExcCode)
+#define EX_TRAP EX_TR
+#define EXC_TRAP EXC_TR
+#define EX_FPE 15 /* floating point exception */
+#define EXC_FPE (EX_FPE << S_CauseExcCode)
+#define EX_C2E 18 /* COP2 exception */
+#define EXC_C2E (EX_C2E << S_CauseExcCode)
+#define EX_MDMX 22 /* MDMX exception */
+#define EXC_MDMX (EX_MDMX << S_CauseExcCode)
+#define EX_WATCH 23 /* Watch exception */
+#define EXC_WATCH (EX_WATCH << S_CauseExcCode)
+#define EX_MCHECK 24 /* Machine check exception */
+#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode)
+#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */
+#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode)
+
+
+/*
+ ************************************************************************
+ * E P C R E G I S T E R ( 1 4 ) *
+ ************************************************************************
+ *
+ * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // Exception PC | EPC
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_EPC $14
+#define R_C0_EPC 14
+
+#define M_EPC0Fields 0x00000000
+#define M_EPCRFields 0x00000000
+#define M_EPC0Fields64 UNS64Const(0x0000000000000000)
+#define M_EPCRFields64 UNS64Const(0x0000000000000000)
+
+/*
+ ************************************************************************
+ * P R I D R E G I S T E R ( 1 5 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Company Opts | Company ID | Procesor ID | Revision | PRId
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_PRId $15
+#define R_C0_PRId 15
+#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_PRIdCoOpt 24 /* Company options (R) */
+#define M_PRIdCoOpt (0xff << S_PRIdCoOpt)
+#define S_PRIdCoID 16 /* Company ID (R) */
+#define M_PRIdCoID (0xff << S_PRIdCoID)
+#define S_PRIdImp 8 /* Implementation ID (R) */
+#define M_PRIdImp (0xff << S_PRIdImp)
+#define S_PRIdRev 0 /* Revision (R) */
+#define M_PRIdRev (0xff << S_PRIdRev)
+
+#define M_PRId0Fields 0x00000000
+#define M_PRIdRFields 0xffffffff
+/*
+ * Values in the Company ID field
+ */
+#define K_PRIdCoID_MIPS 1
+#define K_PRIdCoID_Broadcom 2
+#define K_PRIdCoID_Alchemy 3
+#define K_PRIdCoID_SiByte 4
+#define K_PRIdCoID_SandCraft 5
+#define K_PRIdCoID_Philips 6
+#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */
+
+
+/*
+ * Values in the implementation number field
+ */
+#define K_PRIdImp_Jade 0x80
+#define K_PRIdImp_Opal 0x81
+#define K_PRIdImp_Ruby 0x82
+#define K_PRIdImp_JadeLite 0x83
+#define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */
+#define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */
+#define K_PRIdImp_4KSc 0x86 /* Coral */
+
+#define K_PRIdImp_R3000 0x01
+#define K_PRIdImp_R4000 0x04
+#define K_PRIdImp_R10000 0x09
+#define K_PRIdImp_R4300 0x0b
+#define K_PRIdImp_R5000 0x23
+#define K_PRIdImp_R5200 0x28
+#define K_PRIdImp_R5400 0x54
+
+/*
+ ************************************************************************
+ * C O N F I G R E G I S T E R ( 1 6 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |M| |B| A | A | | K | Config
+ * | | Reserved for Implementations|E| T | R | Reserved | 0 |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Config $16
+#define R_C0_Config 16
+#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_ConfigMore 31 /* Additional config registers present (R) */
+#define M_ConfigMore (0x1 << S_ConfigMore)
+#define S_ConfigImpl 16 /* Implementation-specific fields */
+#define M_ConfigImpl (0x7fff << S_ConfigImpl)
+#define S_ConfigBE 15 /* Denotes big-endian operation (R) */
+#define M_ConfigBE (0x1 << S_ConfigBE)
+#define S_ConfigAT 13 /* Architecture type (R) */
+#define M_ConfigAT (0x3 << S_ConfigAT)
+#define S_ConfigAR 10 /* Architecture revision (R) */
+#define M_ConfigAR (0x7 << S_ConfigAR)
+#define S_ConfigMT 7 /* MMU Type (R) */
+#define M_ConfigMT (0x7 << S_ConfigMT)
+#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */
+#define M_ConfigK0 (0x7 << S_ConfigK0)
+
+/*
+ * The following definitions are technically part of the "reserved for
+ * implementations" field, but are the semi-standard definition used in
+ * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3
+ * references. For that reason, they are included here, but may be
+ * overridden by true implementation-specific definitions
+ */
+#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */
+#define M_ConfigK23 (0x7 << S_ConfigK23)
+#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */
+#define M_ConfigKU (0x7 << S_ConfigKU)
+
+#define M_Config0Fields 0x00000078
+#define M_ConfigRFields 0x8000ff80
+
+/*
+ * Values in the AT field
+ */
+#define K_ConfigAT_MIPS32 0 /* MIPS32 */
+#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */
+#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */
+
+/*
+ * Values in the MT field
+ */
+#define K_ConfigMT_NoMMU 0 /* No MMU */
+#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */
+#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */
+#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */
+
+
+/*
+ ************************************************************************
+ * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1
+ * | | | | | | | | |2|D|C|R|A|P|P|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Config1 $16,1
+#define R_C0_Config1 16
+
+#define S_Config1More 31 /* Additional Config registers present (R) */
+#define M_Config1More (0x1 << S_Config1More)
+#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */
+#define M_Config1MMUSize (0x3f << S_Config1MMUSize)
+#define S_Config1IS 22 /* Icache sets per way (R) */
+#define M_Config1IS (0x7 << S_Config1IS)
+#define S_Config1IL 19 /* Icache line size (R) */
+#define M_Config1IL (0x7 << S_Config1IL)
+#define S_Config1IA 16 /* Icache associativity - 1 (R) */
+#define M_Config1IA (0x7 << S_Config1IA)
+#define S_Config1DS 13 /* Dcache sets per way (R) */
+#define M_Config1DS (0x7 << S_Config1DS)
+#define S_Config1DL 10 /* Dcache line size (R) */
+#define M_Config1DL (0x7 << S_Config1DL)
+#define S_Config1DA 7 /* Dcache associativity (R) */
+#define M_Config1DA (0x7 << S_Config1DA)
+#define S_Config1C2 6 /* Coprocessor 2 present (R) */
+#define M_Config1C2 (0x1 << S_Config1C2)
+#define S_Config1MD 5 /* Denotes MDMX present (R) */
+#define M_Config1MD (0x1 << S_Config1MD)
+#define S_Config1PC 4 /* Denotes performance counters present (R) */
+#define M_Config1PC (0x1 << S_Config1PC)
+#define S_Config1WR 3 /* Denotes watch registers present (R) */
+#define M_Config1WR (0x1 << S_Config1WR)
+#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */
+#define M_Config1CA (0x1 << S_Config1CA)
+#define S_Config1EP 1 /* Denotes EJTAG present (R) */
+#define M_Config1EP (0x1 << S_Config1EP)
+#define S_Config1FP 0 /* Denotes floating point present (R) */
+#define M_Config1FP (0x1 << S_Config1FP)
+
+#define M_Config10Fields 0x00000060
+#define M_Config1RFields 0x7fffff9f
+
+/*
+ * The following macro generates a table that is indexed
+ * by the Icache or Dcache sets field in Config1 and
+ * contains the decoded value of sets per way
+ */
+#define Config1CacheSets() \
+ HALF(64); \
+ HALF(128); \
+ HALF(256); \
+ HALF(512); \
+ HALF(1024); \
+ HALF(2048); \
+ HALF(4096); \
+ HALF(8192);
+
+/*
+ * The following macro generates a table that is indexed
+ * by the Icache or Dcache line size field in Config1 and
+ * contains the decoded value of the cache line size, in bytes
+ */
+#define Config1CacheLineSize() \
+ HALF(0); \
+ HALF(4); \
+ HALF(8); \
+ HALF(16); \
+ HALF(32); \
+ HALF(64); \
+ HALF(128); \
+ HALF(256);
+
+
+/*
+ ************************************************************************
+ * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |M| | | | | | | | | | | | |S|T| Config1
+ * | | | | | | | | | | | | | |M|L|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Config2 $16,2
+#define R_C0_Config2 16
+
+#define S_Config2More 31 /* Additional Config registers present (R) */
+#define M_Config2More (0x1 << S_Config2More)
+#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */
+#define M_Config2SM (0x1 << S_Config2SM)
+#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */
+#define M_Config2TL (0x1 << S_Config2TL)
+
+#define M_Config20Fields 0xfffffffc
+#define M_Config2RFields 0x00000003
+
+/*
+ ************************************************************************
+ * L L A D D R R E G I S T E R ( 1 7 ) *
+ ************************************************************************
+ *
+ * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // LL Physical Address | LLAddr
+ * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_LLAddr $17
+#define R_C0_LLAddr 17
+#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_LLAddr0Fields 0x00000000
+#define M_LLAddrRFields 0x00000000
+#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000)
+#define M_LLAddrRFields64 UNS64Const(0x0000000000000000)
+
+
+/*
+ ************************************************************************
+ * W A T C H L O R E G I S T E R ( 1 8 ) *
+ ************************************************************************
+ *
+ * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // Watch Virtual Address |I|R|W| WatchLo
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_WatchLo $18
+#define R_C0_WatchLo 18
+#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */
+#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr)
+#define S_WatchLoI 2 /* Enable Istream watch (R/W) */
+#define M_WatchLoI (0x1 << S_WatchLoI)
+#define S_WatchLoR 1 /* Enable data read watch (R/W) */
+#define M_WatchLoR (0x1 << S_WatchLoR)
+#define S_WatchLoW 0 /* Enable data write watch (R/W) */
+#define M_WatchLoW (0x1 << S_WatchLoW)
+
+#define M_WatchLo0Fields 0x00000000
+#define M_WatchLoRFields 0x00000000
+#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000)
+#define M_WatchLoRFields64 UNS64Const(0x0000000000000000)
+
+#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW)
+
+
+/*
+ ************************************************************************
+ * W A T C H H I R E G I S T E R ( 1 9 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_WatchHi $19
+#define R_C0_WatchHi 19
+#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */
+#define M_WatchHiM (0x1 << S_WatchHiM)
+#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */
+#define M_WatchHiG (0x1 << S_WatchHiG)
+#define S_WatchHiASID 16 /* ASID value to match (R/W) */
+#define M_WatchHiASID (0xff << S_WatchHiASID)
+#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */
+#define M_WatchHiMask (0x1ff << S_WatchHiMask)
+
+#define M_WatchHi0Fields 0x3f00f007
+#define M_WatchHiRFields 0x80000000
+
+
+/*
+ ************************************************************************
+ * X C O N T E X T R E G I S T E R ( 2 0 ) *
+ ************************************************************************
+ *
+ * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_XContext $20
+#define R_C0_XContext 20
+#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_XContextBadVPN2 4 /* BadVPN2 (R) */
+#define S_XContextBadVPN S_XContextBadVPN2
+
+#define M_XContext0Fields 0x0000000f
+
+
+/*
+ ************************************************************************
+ * D E B U G R E G I S T E R ( 2 3 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D|
+ * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S|
+ * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S|
+ * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug
+ * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | |
+ * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | |
+ * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | |
+ * | | | | | | | | | | | | |r|r| | | | | | | | | | | |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Debug $23 /* EJTAG */
+#define R_C0_Debug 23
+
+#define S_DebugDBD 31 /* Debug branch delay (R) */
+#define M_DebugDBD (0x1 << S_DebugDBD)
+#define S_DebugDM 30 /* Debug mode (R) */
+#define M_DebugDM (0x1 << S_DebugDM)
+#define S_DebugNoDCR 29 /* No debug control register present (R) */
+#define M_DebugNoDCR (0x1 << S_DebugNoDCR)
+#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */
+#define M_DebugLSNM (0x1 << S_DebugLSNM)
+#define S_DebugDoze 27 /* Doze (R) */
+#define M_DebugDoze (0x1 << S_DebugDoze)
+#define S_DebugHalt 26 /* Halt (R) */
+#define M_DebugHalt (0x1 << S_DebugHalt)
+#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */
+#define M_DebugCountDM (0x1 << S_DebugCountDM)
+#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */
+#define M_DebugIBusEP (0x1 << S_DebugIBusEP)
+#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */
+#define M_DebugMCheckP (0x1 << S_DebugMCheckP)
+#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */
+#define M_DebugCacheEP (0x1 << S_DebugCacheEP)
+#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */
+#define M_DebugDBusEP (0x1 << S_DebugDBusEP)
+#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */
+#define M_DebugIEXI (0x1 << S_DebugIEXI)
+#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */
+#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr)
+#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */
+#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr)
+#define S_DebugEJTAGver 15 /* EJTAG version number (R) */
+#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver)
+#define S_DebugDExcCode 10 /* Debug exception code (R) */
+#define M_DebugDExcCode (0x1f << S_DebugDExcCode)
+#define S_DebugNoSSt 9 /* No single step implemented (R) */
+#define M_DebugNoSSt (0x1 << S_DebugNoSSt)
+#define S_DebugSSt 8 /* Single step enable (R/W) */
+#define M_DebugSSt (0x1 << S_DebugSSt)
+#define S_DebugDINT 5 /* Debug interrupt (R) */
+#define M_DebugDINT (0x1 << S_DebugDINT)
+#define S_DebugDIB 4 /* Debug instruction break (R) */
+#define M_DebugDIB (0x1 << S_DebugDIB)
+#define S_DebugDDBS 3 /* Debug data break store (R) */
+#define M_DebugDDBS (0x1 << S_DebugDDBS)
+#define S_DebugDDBL 2 /* Debug data break load (R) */
+#define M_DebugDDBL (0x1 << S_DebugDDBL)
+#define S_DebugDBp 1 /* Debug breakpoint (R) */
+#define M_DebugDBp (0x1 << S_DebugDBp)
+#define S_DebugDSS 0 /* Debug single step (R) */
+#define M_DebugDSS (0x1 << S_DebugDSS)
+
+#define M_Debug0Fields 0x01f000c0
+#define M_DebugRFields 0xec0ffe3f
+
+
+/*
+ ************************************************************************
+ * D E P C R E G I S T E R ( 2 4 ) *
+ ************************************************************************
+ *
+ * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // EJTAG Debug Exception PC | DEPC
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+
+#define C0_DEPC $24
+#define R_C0_DEPC 24
+
+#define M_DEEPC0Fields 0x00000000
+#define M_DEEPCRFields 0x00000000
+#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000)
+#define M_DEEPCRFields64 UNS64Const(0x0000000000000000)
+
+
+/*
+ ************************************************************************
+ * P E R F C N T R E G I S T E R ( 2 5 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | | | |I| | | |E|
+ * |M| 0 | Event |E|U|S|K|X| PerfCnt
+ * | | | | | | | |L|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Event Count | PerfCnt
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_PerfCnt $25
+#define R_C0_PerfCnt 25
+#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */
+#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_PerfCntM 31 /* More performance counters exist (R) */
+#define M_PerfCntM (1 << S_PerfCntM)
+#define S_PerfCntEvent 5 /* Enabled event (R/W) */
+#define M_PerfCntEvent (0x3f << S_PerfCntEvent)
+#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */
+#define M_PerfCntIE (1 << S_PerfCntIE)
+#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */
+#define M_PerfCntU (1 << S_PerfCntU)
+#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */
+#define M_PerfCntS (1 << S_PerfCntS)
+#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */
+#define M_PerfCntK (1 << S_PerfCntK)
+#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */
+#define M_PerfCntEXL (1 << S_PerfCntEXL)
+
+#define M_PerfCnt0Fields 0x7ffff800
+#define M_PerfCntRFields 0x80000000
+
+
+/*
+ ************************************************************************
+ * E R R C T L R E G I S T E R ( 2 6 ) *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Error Control | ErrCtl
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_ErrCtl $26
+#define R_C0_ErrCtl 26
+#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */
+#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_ErrCtl0Fields 0x00000000
+#define M_ErrCtlRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Cache Error Control | CacheErr
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_CacheErr $27
+#define R_C0_CacheErr 27
+#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_CacheErr0Fields 0x00000000
+#define M_CachErrRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * T A G L O R E G I S T E R ( 2 8 ) * TagLo
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | TagLo | TagLo
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_TagLo $28
+#define R_C0_TagLo 28
+#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+/*
+ * Some implementations use separate TagLo registers for the
+ * instruction and data caches. In those cases, the following
+ * definitions can be used in relevant code
+ */
+
+#define C0_ITagLo $28,0
+#define C0_DTagLo $28,2
+
+#define M_TagLo0Fields 0x00000000
+#define M_TagLoRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | DataLo | DataLo
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_DataLo $28,1
+#define R_C0_DataLo 28
+
+/*
+ * Some implementations use separate DataLo registers for the
+ * instruction and data caches. In those cases, the following
+ * definitions can be used in relevant code
+ */
+
+#define C0_IDataLo $28,1
+#define C0_DDataLo $28,3
+
+#define M_DataLo0Fields 0x00000000
+#define M_DataLoRFields 0xffffffff
+
+
+/*
+ ************************************************************************
+ * T A G H I R E G I S T E R ( 2 9 ) * TagHi
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | TagHi | TagHi
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_TagHi $29
+#define R_C0_TagHi 29
+#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+/*
+ * Some implementations use separate TagHi registers for the
+ * instruction and data caches. In those cases, the following
+ * definitions can be used in relevant code
+ */
+
+#define C0_ITagHi $29,0
+#define C0_DTagHi $29,2
+
+#define M_TagHi0Fields 0x00000000
+#define M_TagHiRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | DataHi | DataHi
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_DataHi $29,1
+#define R_C0_DataHi 29
+
+/*
+ * Some implementations use separate DataHi registers for the
+ * instruction and data caches. In those cases, the following
+ * definitions can be used in relevant code
+ */
+
+#define C0_IDataHi $29,1
+#define C0_DDataHi $29,3
+
+#define M_DataHi0Fields 0x00000000
+#define M_DataHiRFields 0xffffffff
+
+
+/*
+ ************************************************************************
+ * E R R O R E P C R E G I S T E R ( 3 0 ) *
+ ************************************************************************
+ *
+ * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // Error PC | ErrorEPC
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_ErrorEPC $30
+#define R_C0_ErrorEPC 30
+#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_ErrorEPC0Fields 0x00000000
+#define M_ErrorEPCRFields 0x00000000
+#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000)
+#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000)
+
+
+/*
+ ************************************************************************
+ * D E S A V E R E G I S T E R ( 3 1 ) *
+ ************************************************************************
+ *
+ * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | // EJTAG Register Save Value | DESAVE
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_DESAVE $31
+#define R_C0_DESAVE 31
+
+#define M_DESAVE0Fields 0x00000000
+#define M_DESAVERFields 0x00000000
+#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000)
+#define M_DESAVERFields64 UNS64Const(0x0000000000000000)
+
+
+/*
+ *************************************************************************
+ * C P 1 R E G I S T E R D E F I N I T I O N S *
+ *************************************************************************
+ */
+
+
+/*
+ *************************************************************************
+ * H A R D W A R E F P R N A M E S *
+ *************************************************************************
+ */
+
+#define fp0 $f0
+#define fp1 $f1
+#define fp2 $f2
+#define fp3 $f3
+#define fp4 $f4
+#define fp5 $f5
+#define fp6 $f6
+#define fp7 $f7
+#define fp8 $f8
+#define fp9 $f9
+#define fp10 $f10
+#define fp11 $f11
+#define fp12 $f12
+#define fp13 $f13
+#define fp14 $f14
+#define fp15 $f15
+#define fp16 $f16
+#define fp17 $f17
+#define fp18 $f18
+#define fp19 $f19
+#define fp20 $f20
+#define fp21 $f21
+#define fp22 $f22
+#define fp23 $f23
+#define fp24 $f24
+#define fp25 $f25
+#define fp26 $f26
+#define fp27 $f27
+#define fp28 $f28
+#define fp29 $f29
+#define fp30 $f30
+#define fp31 $f31
+
+/*
+ * The following definitions are used to convert an FPR name
+ * into the corresponding even or odd name, respectively.
+ * This is used in macro substitution in the AVPs.
+ */
+
+#define fp1_even $f0
+#define fp3_even $f2
+#define fp5_even $f4
+#define fp7_even $f6
+#define fp9_even $f8
+#define fp11_even $f10
+#define fp13_even $f12
+#define fp15_even $f14
+#define fp17_even $f16
+#define fp19_even $f18
+#define fp21_even $f20
+#define fp23_even $f22
+#define fp25_even $f24
+#define fp27_even $f26
+#define fp29_even $f28
+#define fp31_even $f30
+
+#define fp0_odd $f1
+#define fp2_odd $f3
+#define fp4_odd $f5
+#define fp6_odd $f7
+#define fp8_odd $f9
+#define fp10_odd $f11
+#define fp12_odd $f13
+#define fp14_odd $f15
+#define fp16_odd $f17
+#define fp18_odd $f19
+#define fp20_odd $f21
+#define fp22_odd $f23
+#define fp24_odd $f25
+#define fp26_odd $f27
+#define fp28_odd $f29
+#define fp30_odd $f31
+
+
+/*
+ *************************************************************************
+ * H A R D W A R E F P R I N D I C E S *
+ *************************************************************************
+ *
+ * These definitions provide the index (number) of the FPR, as opposed
+ * to the assembler register name ($n).
+ */
+
+#define R_fp0 0
+#define R_fp1 1
+#define R_fp2 2
+#define R_fp3 3
+#define R_fp4 4
+#define R_fp5 5
+#define R_fp6 6
+#define R_fp7 7
+#define R_fp8 8
+#define R_fp9 9
+#define R_fp10 10
+#define R_fp11 11
+#define R_fp12 12
+#define R_fp13 13
+#define R_fp14 14
+#define R_fp15 15
+#define R_fp16 16
+#define R_fp17 17
+#define R_fp18 18
+#define R_fp19 19
+#define R_fp20 20
+#define R_fp21 21
+#define R_fp22 22
+#define R_fp23 23
+#define R_fp24 24
+#define R_fp25 25
+#define R_fp26 26
+#define R_fp27 27
+#define R_fp28 28
+#define R_fp29 29
+#define R_fp30 30
+#define R_fp31 31
+
+
+/*
+ *************************************************************************
+ * H A R D W A R E F C R N A M E S *
+ *************************************************************************
+ */
+
+#define fc0 $0
+#define fc25 $25
+#define fc26 $26
+#define fc28 $28
+#define fc31 $31
+
+
+/*
+ *************************************************************************
+ * H A R D W A R E F C R I N D I C E S *
+ *************************************************************************
+ *
+ * These definitions provide the index (number) of the FCR, as opposed
+ * to the assembler register name ($n).
+ */
+
+#define R_fc0 0
+#define R_fc25 25
+#define R_fc26 26
+#define R_fc28 28
+#define R_fc31 31
+
+
+/*
+ *************************************************************************
+ * H A R D W A R E F C C N A M E S *
+ *************************************************************************
+ */
+
+#define cc0 $fcc0
+#define cc1 $fcc1
+#define cc2 $fcc2
+#define cc3 $fcc3
+#define cc4 $fcc4
+#define cc5 $fcc5
+#define cc6 $fcc6
+#define cc7 $fcc7
+
+
+/*
+ *************************************************************************
+ * H A R D W A R E F C C I N D I C E S *
+ *************************************************************************
+ *
+ * These definitions provide the index (number) of the CC, as opposed
+ * to the assembler register name ($n).
+ */
+
+#define R_cc0 0
+#define R_cc1 1
+#define R_cc2 2
+#define R_cc3 3
+#define R_cc4 4
+#define R_cc5 5
+#define R_cc6 6
+#define R_cc7 7
+
+
+/*
+ ************************************************************************
+ * I M P L E M E N T A T I O N R E G I S T E R *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR
+ * | Configuration Bits |D|S| | | | |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FIR $0
+#define R_C1_FIR 0
+
+#define S_FIRConfigS 16
+#define M_FIRConfigS (0x1 << S_FIRConfigS)
+#define S_FIRConfigD 17
+#define M_FIRConfigD (0x1 << S_FIRConfigD)
+#define S_FIRConfigPS 18
+#define M_FIRConfigPS (0x1 << S_FIRConfigPS)
+#define S_FIRConfig3D 19
+#define M_FIRConfig3D (0x1 << S_FIRConfig3D)
+#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D)
+
+#define S_FIRImp 8
+#define M_FIRImp (0xff << S_FIRImp)
+
+#define S_FIRRev 0
+#define M_FIRRev (0xff << S_FIRRev)
+
+#define M_FIR0Fields 0xfff00000
+#define M_FIRRFields 0x000fffff
+
+/*
+ ************************************************************************
+ * C O N D I T I O N C O D E S R E G I S T E R *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | 0 | CC | FCCR
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FCCR $25
+#define R_C1_FCCR 25
+
+#define S_FCCRCC 0
+#define M_FCCRCC (0xff << S_FCCRCC)
+#define S_FCCRCC7 7
+#define M_FCCRCC7 (0x1 << S_FCCRCC7)
+#define S_FCCRCC6 6
+#define M_FCCRCC6 (0x1 << S_FCCRCC6)
+#define S_FCCRCC5 5
+#define M_FCCRCC5 (0x1 << S_FCCRCC5)
+#define S_FCCRCC4 4
+#define M_FCCRCC4 (0x1 << S_FCCRCC4)
+#define S_FCCRCC3 3
+#define M_FCCRCC3 (0x1 << S_FCCRCC3)
+#define S_FCCRCC2 2
+#define M_FCCRCC2 (0x1 << S_FCCRCC2)
+#define S_FCCRCC1 1
+#define M_FCCRCC1 (0x1 << S_FCCRCC1)
+#define S_FCCRCC0 0
+#define M_FCCRCC0 (0x1 << S_FCCRCC0)
+
+#define M_FCCR0Fields 0xffffff00
+#define M_FCCRRFields 0x000000ff
+
+
+/*
+ ************************************************************************
+ * E X C E P T I O N S R E G I S T E R *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | 0 | Cause | 0 | Flags | 0 | FEXR
+ * | |E|V|Z|O|U|I| |V|Z|O|U|I| |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FEXR $26
+#define R_C1_FEXR 26
+
+#define S_FEXRExc 12
+#define M_FEXRExc (0x3f << S_FEXRExc)
+#define S_FEXRExcE 17
+#define M_FEXRExcE (0x1 << S_FEXRExcE)
+#define S_FEXRExcV 16
+#define M_FEXRExcV (0x1 << S_FEXRExcV)
+#define S_FEXRExcZ 15
+#define M_FEXRExcZ (0x1 << S_FEXRExcZ)
+#define S_FEXRExcO 14
+#define M_FEXRExcO (0x1 << S_FEXRExcO)
+#define S_FEXRExcU 13
+#define M_FEXRExcU (0x1 << S_FEXRExcU)
+#define S_FEXRExcI 12
+#define M_FEXRExcI (0x1 << S_FEXRExcI)
+
+#define S_FEXRFlg 2
+#define M_FEXRFlg (0x1f << S_FEXRFlg)
+#define S_FEXRFlgV 6
+#define M_FEXRFlgV (0x1 << S_FEXRFlgV)
+#define S_FEXRFlgZ 5
+#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ)
+#define S_FEXRFlgO 4
+#define M_FEXRFlgO (0x1 << S_FEXRFlgO)
+#define S_FEXRFlgU 3
+#define M_FEXRFlgU (0x1 << S_FEXRFlgU)
+#define S_FEXRFlgI 2
+#define M_FEXRFlgI (0x1 << S_FEXRFlgI)
+
+#define M_FEXR0Fields 0xfffc0f83
+#define M_FEXRRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * E N A B L E S R E G I S T E R *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | 0 | Enables | 0 |F|RM | FENR
+ * | |V|Z|O|U|I| |S| |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FENR $28
+#define R_C1_FENR 28
+
+#define S_FENREna 7
+#define M_FENREna (0x1f << S_FENREna)
+#define S_FENREnaV 11
+#define M_FENREnaV (0x1 << S_FENREnaV)
+#define S_FENREnaZ 10
+#define M_FENREnaZ (0x1 << S_FENREnaZ)
+#define S_FENREnaO 9
+#define M_FENREnaO (0x1 << S_FENREnaO)
+#define S_FENREnaU 8
+#define M_FENREnaU (0x1 << S_FENREnaU)
+#define S_FENREnaI 7
+#define M_FENREnaI (0x1 << S_FENREnaI)
+
+#define S_FENRFS 2
+#define M_FENRFS (0x1 << S_FENRFS)
+
+#define S_FENRRM 0
+#define M_FENRRM (0x3 << S_FENRRM)
+
+#define M_FENR0Fields 0xfffff078
+#define M_FENRRFields 0x00000000
+
+
+/*
+ ************************************************************************
+ * C O N T R O L / S T A T U S R E G I S T E R *
+ ************************************************************************
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR
+ * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FCSR $31
+#define R_C1_FCSR 31
+
+#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */
+#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1)
+#define S_FCSRCC7 31
+#define M_FCSRCC7 (0x1 << S_FCSRCC7)
+#define S_FCSRCC6 30
+#define M_FCSRCC6 (0x1 << S_FCSRCC6)
+#define S_FCSRCC5 29
+#define M_FCSRCC5 (0x1 << S_FCSRCC5)
+#define S_FCSRCC4 28
+#define M_FCSRCC4 (0x1 << S_FCSRCC4)
+#define S_FCSRCC3 27
+#define M_FCSRCC3 (0x1 << S_FCSRCC3)
+#define S_FCSRCC2 26
+#define M_FCSRCC2 (0x1 << S_FCSRCC2)
+#define S_FCSRCC1 25
+#define M_FCSRCC1 (0x1 << S_FCSRCC1)
+
+#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */
+#define M_FCSRFS (0x1 << S_FCSRFS)
+
+#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */
+#define M_FCSRCC0 (0x1 << S_FCSRCC0)
+#define S_FCSRCC S_FCSRCC0
+#define M_FCSRCC M_FCSRCC0
+
+#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */
+#define M_FCSRImpl (0x3 << S_FCSRImpl)
+
+#define S_FCSRExc 12 /* Exception cause (R/W) */
+#define M_FCSRExc (0x3f << S_FCSRExc)
+#define S_FCSRExcE 17
+#define M_FCSRExcE (0x1 << S_FCSRExcE)
+#define S_FCSRExcV 16
+#define M_FCSRExcV (0x1 << S_FCSRExcV)
+#define S_FCSRExcZ 15
+#define M_FCSRExcZ (0x1 << S_FCSRExcZ)
+#define S_FCSRExcO 14
+#define M_FCSRExcO (0x1 << S_FCSRExcO)
+#define S_FCSRExcU 13
+#define M_FCSRExcU (0x1 << S_FCSRExcU)
+#define S_FCSRExcI 12
+#define M_FCSRExcI (0x1 << S_FCSRExcI)
+
+#define S_FCSREna 7 /* Exception enable (R/W) */
+#define M_FCSREna (0x1f << S_FCSREna)
+#define S_FCSREnaV 11
+#define M_FCSREnaV (0x1 << S_FCSREnaV)
+#define S_FCSREnaZ 10
+#define M_FCSREnaZ (0x1 << S_FCSREnaZ)
+#define S_FCSREnaO 9
+#define M_FCSREnaO (0x1 << S_FCSREnaO)
+#define S_FCSREnaU 8
+#define M_FCSREnaU (0x1 << S_FCSREnaU)
+#define S_FCSREnaI 7
+#define M_FCSREnaI (0x1 << S_FCSREnaI)
+
+#define S_FCSRFlg 2 /* Exception flags (R/W) */
+#define M_FCSRFlg (0x1f << S_FCSRFlg)
+#define S_FCSRFlgV 6
+#define M_FCSRFlgV (0x1 << S_FCSRFlgV)
+#define S_FCSRFlgZ 5
+#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ)
+#define S_FCSRFlgO 4
+#define M_FCSRFlgO (0x1 << S_FCSRFlgO)
+#define S_FCSRFlgU 3
+#define M_FCSRFlgU (0x1 << S_FCSRFlgU)
+#define S_FCSRFlgI 2
+#define M_FCSRFlgI (0x1 << S_FCSRFlgI)
+
+#define S_FCSRRM 0 /* Rounding mode (R/W) */
+#define M_FCSRRM (0x3 << S_FCSRRM)
+
+#define M_FCSR0Fields 0x001c0000
+#define M_FCSRRFields 0x00000000
+
+/*
+ * Values in the rounding mode field (of both FCSR and FCCR)
+ */
+#define K_FCSRRM_RN 0
+#define K_FCSRRM_RZ 1
+#define K_FCSRRM_RP 2
+#define K_FCSRRM_RM 3
+
+
+/* ********************************************************************* */
+/* Interface function definition */
+
+
+/* ********************************************************************* */
+
+#endif /* __ARCHDEFS_H__ */
diff --git a/firmware/export/mips.h b/firmware/export/mips.h
new file mode 100755
index 0000000000..6f73d150b2
--- /dev/null
+++ b/firmware/export/mips.h
@@ -0,0 +1,820 @@
+/**************************************************************************
+* *
+* PROJECT : MIPS port for uC/OS-II *
+* *
+* MODULE : MIPS.h *
+* *
+* AUTHOR : Michael Anburaj *
+* URL : http://geocities.com/michaelanburaj/ *
+* EMAIL: michaelanburaj@hotmail.com *
+* *
+* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board *
+* *
+* TOOL-CHAIN : SDE & Cygnus *
+* *
+* DESCRIPTION : *
+* MIPS processor definitions. *
+* The basic CPU definitions are found in the file archdefs.h, which *
+* is included by mips.h. *
+* *
+* mips.h implements aliases for some of the definitions in archdefs.h *
+* and adds various definitions. *
+* *
+**************************************************************************/
+
+
+#ifndef __MIPS_H__
+#define __MIPS_H__
+
+#include "mips-archdefs.h"
+
+
+/* ********************************************************************* */
+/* Module configuration */
+
+
+/* ********************************************************************* */
+/* Interface macro & data definition */
+
+#ifndef MSK
+#define MSK(n) ((1 << (n)) - 1)
+#endif
+
+/* CPU registers */
+#define SYS_CPUREG_ZERO 0
+#define SYS_CPUREG_AT 1
+#define SYS_CPUREG_V0 2
+#define SYS_CPUREG_V1 3
+#define SYS_CPUREG_A0 4
+#define SYS_CPUREG_A1 5
+#define SYS_CPUREG_A2 6
+#define SYS_CPUREG_A3 7
+#define SYS_CPUREG_T0 8
+#define SYS_CPUREG_T1 9
+#define SYS_CPUREG_T2 10
+#define SYS_CPUREG_T3 11
+#define SYS_CPUREG_T4 12
+#define SYS_CPUREG_T5 13
+#define SYS_CPUREG_T6 14
+#define SYS_CPUREG_T7 15
+#define SYS_CPUREG_S0 16
+#define SYS_CPUREG_S1 17
+#define SYS_CPUREG_S2 18
+#define SYS_CPUREG_S3 19
+#define SYS_CPUREG_S4 20
+#define SYS_CPUREG_S5 21
+#define SYS_CPUREG_S6 22
+#define SYS_CPUREG_S7 23
+#define SYS_CPUREG_T8 24
+#define SYS_CPUREG_T9 25
+#define SYS_CPUREG_K0 26
+#define SYS_CPUREG_K1 27
+#define SYS_CPUREG_GP 28
+#define SYS_CPUREG_SP 29
+#define SYS_CPUREG_S8 30
+#define SYS_CPUREG_FP SYS_CPUREG_S8
+#define SYS_CPUREG_RA 31
+
+
+/* CPU register fp ($30) has an alias s8 */
+#define s8 fp
+
+
+/* Aliases for System Control Coprocessor (CP0) registers */
+#define C0_INDEX C0_Index
+#define C0_RANDOM C0_Random
+#define C0_ENTRYLO0 C0_EntryLo0
+#define C0_ENTRYLO1 C0_EntryLo1
+#define C0_CONTEXT C0_Context
+#define C0_PAGEMASK C0_PageMask
+#define C0_WIRED C0_Wired
+#define C0_BADVADDR C0_BadVAddr
+#define C0_COUNT C0_Count
+#define C0_ENTRYHI C0_EntryHi
+#define C0_COMPARE C0_Compare
+#define C0_STATUS C0_Status
+#define C0_CAUSE C0_Cause
+
+#ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */
+#undef C0_PRID
+#endif
+#define C0_PRID C0_PRId
+
+#define C0_CONFIG C0_Config
+#define C0_CONFIG1 C0_Config1
+#define C0_LLADDR C0_LLAddr
+#define C0_WATCHLO C0_WatchLo
+#define C0_WATCHHI C0_WatchHi
+#define C0_DEBUG C0_Debug
+#define C0_PERFCNT C0_PerfCnt
+#define C0_ERRCTL C0_ErrCtl
+#define C0_CACHEERR C0_CacheErr
+#define C0_TAGLO C0_TagLo
+#define C0_DATALO C0_DataLo
+#define C0_TAGHI C0_TagHi
+#define C0_DATAHI C0_DataHi
+#define C0_ERROREPC C0_ErrorEPC
+#if 0
+#define C0_DESAVE C0_DESAVE
+#define C0_EPC C0_EPC
+#define C0_DEPC C0_DEPC
+#endif
+
+/* System Control Coprocessor (CP0) registers select fields */
+#define C0_INDEX_SEL 0 /* TLB Index */
+#define C0_RANDOM_SEL 0 /* TLB Random */
+#define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */
+#define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */
+#define C0_CONTEXT_SEL 0 /* Context */
+#define C0_PAGEMASK_SEL 0 /* TLB PageMask */
+#define C0_WIRED_SEL 0 /* TLB Wired */
+#define C0_BADVADDR_SEL 0 /* Bad Virtual Address */
+#define C0_COUNT_SEL 0 /* Count */
+#define C0_ENTRYHI_SEL 0 /* TLB EntryHi */
+#define C0_COMPARE_SEL 0 /* Compare */
+#define C0_STATUS_SEL 0 /* Processor Status */
+#define C0_CAUSE_SEL 0 /* Exception Cause */
+#define C0_EPC_SEL 0 /* Exception PC */
+#define C0_PRID_SEL 0 /* Processor Revision Indentifier */
+#define C0_CONFIG_SEL 0 /* Config */
+#define C0_CONFIG1_SEL 1 /* Config1 */
+#define C0_LLADDR_SEL 0 /* LLAddr */
+#define C0_WATCHLO_SEL 0 /* WatchpointLo */
+#define C0_WATCHHI_SEL 0 /* WatchpointHi */
+#define C0_DEBUG_SEL 0 /* EJTAG Debug Register */
+#define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */
+#define C0_PERFCNT_SEL 0 /* Performance counter interface */
+#define C0_ERRCTL_SEL 0 /* ERRCTL */
+#define C0_CACHEERR_SEL 0 /* CacheErr */
+#define C0_TAGLO_SEL 0 /* TagLo */
+#define C0_DATALO_SEL 1 /* DataLo */
+#define C0_DTAGLO_SEL 2 /* DTagLo */
+#define C0_TAGHI_SEL 0 /* TagHi */
+#define C0_DATAHI_SEL 1 /* DataHi */
+#define C0_DTAGHI_SEL 2 /* DTagHi */
+#define C0_ERROREPC_SEL 0 /* ErrorEPC */
+#define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */
+
+
+/* C0_CONFIG register encoding */
+
+#define C0_CONFIG_M_SHF S_ConfigMore
+#define C0_CONFIG_M_MSK M_ConfigMore
+#define C0_CONFIG_M_BIT C0_CONFIG_M_MSK
+
+#define C0_CONFIG_BE_SHF S_ConfigBE
+#define C0_CONFIG_BE_MSK M_ConfigBE
+#define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK
+
+#define C0_CONFIG_AT_SHF S_ConfigAT
+#define C0_CONFIG_AT_MSK M_ConfigAT
+#define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32
+#define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S
+#define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64
+
+#define C0_CONFIG_AR_SHF S_ConfigAR
+#define C0_CONFIG_AR_MSK M_ConfigAR
+
+#define C0_CONFIG_MT_SHF S_ConfigMT
+#define C0_CONFIG_MT_MSK M_ConfigMT
+#define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU
+#define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU
+#define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU
+#define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU
+
+#define C0_CONFIG_K0_SHF S_ConfigK0
+#define C0_CONFIG_K0_MSK M_ConfigK0
+#define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA
+#define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA
+#define C0_CONFIG_K0_UNCACHED K_CacheAttrU
+#define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN
+#define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE
+#define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS
+#define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU
+#define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA
+
+
+/* WC field.
+ *
+ * This feature is present specifically to support configuration
+ * testing of the core in a lead vehicle, and is not supported
+ * in any other environment. Attempting to use this feature
+ * outside of the scope of a lead vehicle is a violation of the
+ * MIPS Architecture, and may cause unpredictable operation of
+ * the processor.
+ */
+#define C0_CONFIG_WC_SHF 19
+#define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF)
+#define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK
+
+
+/* C0_CONFIG1 register encoding */
+
+#define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize
+#define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize
+
+#define C0_CONFIG1_IS_SHF S_Config1IS
+#define C0_CONFIG1_IS_MSK M_Config1IS
+
+#define C0_CONFIG1_IL_SHF S_Config1IL
+#define C0_CONFIG1_IL_MSK M_Config1IL
+
+#define C0_CONFIG1_IA_SHF S_Config1IA
+#define C0_CONFIG1_IA_MSK M_Config1IA
+
+#define C0_CONFIG1_DS_SHF S_Config1DS
+#define C0_CONFIG1_DS_MSK M_Config1DS
+
+#define C0_CONFIG1_DL_SHF S_Config1DL
+#define C0_CONFIG1_DL_MSK M_Config1DL
+
+#define C0_CONFIG1_DA_SHF S_Config1DA
+#define C0_CONFIG1_DA_MSK M_Config1DA
+
+#define C0_CONFIG1_WR_SHF S_Config1WR
+#define C0_CONFIG1_WR_MSK M_Config1WR
+#define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK
+
+#define C0_CONFIG1_CA_SHF S_Config1CA
+#define C0_CONFIG1_CA_MSK M_Config1CA
+#define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK
+
+#define C0_CONFIG1_EP_SHF S_Config1EP
+#define C0_CONFIG1_EP_MSK M_Config1EP
+#define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK
+
+#define C0_CONFIG1_FP_SHF S_Config1FP
+#define C0_CONFIG1_FP_MSK M_Config1FP
+#define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK
+
+
+/* C0_STATUS register encoding */
+
+#define C0_STATUS_CU3_SHF S_StatusCU3
+#define C0_STATUS_CU3_MSK M_StatusCU3
+#define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK
+
+#define C0_STATUS_CU2_SHF S_StatusCU2
+#define C0_STATUS_CU2_MSK M_StatusCU2
+#define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK
+
+#define C0_STATUS_CU1_SHF S_StatusCU1
+#define C0_STATUS_CU1_MSK M_StatusCU1
+#define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK
+
+#define C0_STATUS_CU0_SHF S_StatusCU1
+#define C0_STATUS_CU0_MSK M_StatusCU1
+#define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK
+
+#define C0_STATUS_RP_SHF S_StatusRP
+#define C0_STATUS_RP_MSK M_StatusRP
+#define C0_STATUS_RP_BIT C0_STATUS_RP_MSK
+
+#define C0_STATUS_FR_SHF S_StatusFR
+#define C0_STATUS_FR_MSK M_StatusFR
+#define C0_STATUS_FR_BIT C0_STATUS_FR_MSK
+
+#define C0_STATUS_RE_SHF S_StatusRE
+#define C0_STATUS_RE_MSK M_StatusRE
+#define C0_STATUS_RE_BIT C0_STATUS_RE_MSK
+
+#define C0_STATUS_BEV_SHF S_StatusBEV
+#define C0_STATUS_BEV_MSK M_StatusBEV
+#define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK
+
+#define C0_STATUS_TS_SHF S_StatusTS
+#define C0_STATUS_TS_MSK M_StatusTS
+#define C0_STATUS_TS_BIT C0_STATUS_TS_MSK
+
+#define C0_STATUS_SR_SHF S_StatusSR
+#define C0_STATUS_SR_MSK M_StatusSR
+#define C0_STATUS_SR_BIT C0_STATUS_SR_MSK
+
+#define C0_STATUS_NMI_SHF S_StatusNMI
+#define C0_STATUS_NMI_MSK M_StatusNMI
+#define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK
+
+#define C0_STATUS_IM_SHF S_StatusIM
+#define C0_STATUS_IM_MSK M_StatusIM
+/* Note that the the definitions below indicate the interrupt number
+ * rather than the mask.
+ * (0..1 for SW interrupts and 2...7 for HW interrupts)
+ */
+#define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM)
+#define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM)
+#define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM)
+#define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM)
+#define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM)
+#define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM)
+#define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM)
+#define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM)
+
+/* Max interrupt code */
+#define C0_STATUS_IM_MAX C0_STATUS_IM_HW5
+
+#define C0_STATUS_KSU_SHF S_StatusKSU
+#define C0_STATUS_KSU_MSK M_StatusKSU
+
+#define C0_STATUS_UM_SHF S_StatusUM
+#define C0_STATUS_UM_MSK M_StatusUM
+#define C0_STATUS_UM_BIT C0_STATUS_UM_MSK
+
+#define C0_STATUS_ERL_SHF S_StatusERL
+#define C0_STATUS_ERL_MSK M_StatusERL
+#define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK
+
+#define C0_STATUS_EXL_SHF S_StatusEXL
+#define C0_STATUS_EXL_MSK M_StatusEXL
+#define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK
+
+#define C0_STATUS_IE_SHF S_StatusIE
+#define C0_STATUS_IE_MSK M_StatusIE
+#define C0_STATUS_IE_BIT C0_STATUS_IE_MSK
+
+
+/* C0_PRID register encoding */
+
+#define C0_PRID_OPT_SHF S_PRIdCoOpt
+#define C0_PRID_OPT_MSK M_PRIdCoOpt
+
+#define C0_PRID_COMP_SHF S_PRIdCoID
+#define C0_PRID_COMP_MSK M_PRIdCoID
+#define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS
+#define C0_PRID_COMP_NOT_MIPS32_64 0
+
+#define C0_PRID_PRID_SHF S_PRIdImp
+#define C0_PRID_PRID_MSK M_PRIdImp
+
+/* Jade */
+#define C0_PRID_PRID_4Kc K_PRIdImp_Jade
+#define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */
+/* Emerald */
+#define C0_PRID_PRID_4KEc K_PRIdImp_4KEc
+#define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp
+/* Coral */
+#define C0_PRID_PRID_4KSc K_PRIdImp_4KSc
+/* Opal */
+#define C0_PRID_PRID_5K K_PRIdImp_Opal
+/* Ruby */
+#define C0_PRID_PRID_20Kc K_PRIdImp_Ruby
+/* Other CPUs */
+#define C0_PRID_PRID_R4000 K_PRIdImp_R4000
+#define C0_PRID_PRID_RM52XX K_PRIdImp_R5200
+#define C0_PRID_PRID_RM70XX 0x27
+
+#define C0_PRID_REV_SHF S_PRIdRev
+#define C0_PRID_REV_MSK M_PRIdRev
+
+
+#define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_4Kc << \
+ C0_PRID_PRID_SHF) \
+ )
+
+#define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_4Kmp << \
+ C0_PRID_PRID_SHF) \
+ )
+
+#define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_4KEc << \
+ C0_PRID_PRID_SHF) \
+ )
+
+#define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_4KEmp << \
+ C0_PRID_PRID_SHF) \
+ )
+
+#define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_4KSc << \
+ C0_PRID_PRID_SHF) \
+ )
+
+#define MIPS_5K ( (C0_PRID_COMP_MIPS << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_5K << \
+ C0_PRID_PRID_SHF) \
+ )
+
+#define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_20Kc << \
+ C0_PRID_PRID_SHF) \
+ )
+
+#define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_RM52XX << \
+ C0_PRID_PRID_SHF) \
+ )
+
+#define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
+ C0_PRID_COMP_SHF) | \
+ (C0_PRID_PRID_RM70XX << \
+ C0_PRID_PRID_SHF) \
+ )
+
+/* C0_ENTRYHI register encoding */
+
+#define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2
+#define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2
+
+#define C0_ENTRYHI_ASID_SHF S_EntryHiASID
+#define C0_ENTRYHI_ASID_MSK M_EntryHiASID
+
+
+/* C0_CAUSE register encoding */
+
+#define C0_CAUSE_BD_SHF S_CauseBD
+#define C0_CAUSE_BD_MSK M_CauseBD
+#define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK
+
+#define C0_CAUSE_CE_SHF S_CauseCE
+#define C0_CAUSE_CE_MSK M_CauseCE
+
+#define C0_CAUSE_IV_SHF S_CauseIV
+#define C0_CAUSE_IV_MSK M_CauseIV
+#define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK
+
+#define C0_CAUSE_WP_SHF S_CauseWP
+#define C0_CAUSE_WP_MSK M_CauseWP
+#define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK
+
+#define C0_CAUSE_IP_SHF S_CauseIP
+#define C0_CAUSE_IP_MSK M_CauseIP
+
+#define C0_CAUSE_CODE_SHF S_CauseExcCode
+#define C0_CAUSE_CODE_MSK M_CauseExcCode
+
+#define C0_CAUSE_CODE_INT EX_INT
+#define C0_CAUSE_CODE_MOD EX_MOD
+#define C0_CAUSE_CODE_TLBL EX_TLBL
+#define C0_CAUSE_CODE_TLBS EX_TLBS
+#define C0_CAUSE_CODE_ADEL EX_ADEL
+#define C0_CAUSE_CODE_ADES EX_ADES
+#define C0_CAUSE_CODE_IBE EX_IBE
+#define C0_CAUSE_CODE_DBE EX_DBE
+#define C0_CAUSE_CODE_SYS EX_SYS
+#define C0_CAUSE_CODE_BP EX_BP
+#define C0_CAUSE_CODE_RI EX_RI
+#define C0_CAUSE_CODE_CPU EX_CPU
+#define C0_CAUSE_CODE_OV EX_OV
+#define C0_CAUSE_CODE_TR EV_TR
+#define C0_CAUSE_CODE_FPE EX_FPE
+#define C0_CAUSE_CODE_WATCH EX_WATCH
+#define C0_CAUSE_CODE_MCHECK EX_MCHECK
+
+/* Max cause code */
+#define C0_CAUSE_CODE_MAX EX_MCHECK
+
+
+/* C0_PAGEMASK register encoding */
+#define C0_PAGEMASK_MASK_SHF S_PageMaskMask
+#define C0_PAGEMASK_MASK_MSK M_PageMaskMask
+#define C0_PAGEMASK_MASK_4K K_PageMask4K
+#define C0_PAGEMASK_MASK_16K K_PageMask16K
+#define C0_PAGEMASK_MASK_64K K_PageMask64K
+#define C0_PAGEMASK_MASK_256K K_PageMask256K
+#define C0_PAGEMASK_MASK_1M K_PageMask1M
+#define C0_PAGEMASK_MASK_4M K_PageMask4M
+#define C0_PAGEMASK_MASK_16M K_PageMask16M
+
+
+/* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */
+#define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN
+#define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN
+
+#define C0_ENTRYLO0_C_SHF S_EntryLoC
+#define C0_ENTRYLO0_C_MSK M_EntryLoC
+
+#define C0_ENTRYLO0_D_SHF S_EntryLoD
+#define C0_ENTRYLO0_D_MSK M_EntryLoD
+
+#define C0_ENTRYLO0_V_SHF S_EntryLoV
+#define C0_ENTRYLO0_V_MSK M_EntryLoV
+
+#define C0_ENTRYLO0_G_SHF S_EntryLoG
+#define C0_ENTRYLO0_G_MSK M_EntryLoG
+
+
+/* FPU (CP1) FIR register encoding */
+#define C1_FIR_3D_SHF S_FIRConfig3D
+#define C1_FIR_3D_MSK M_FIRConfig3D
+
+#define C1_FIR_PS_SHF S_FIRConfigPS
+#define C1_FIR_PS_MSK M_FIRConfigPS
+
+#define C1_FIR_D_SHF S_FIRConfigD
+#define C1_FIR_D_MSK M_FIRConfigD
+
+#define C1_FIR_S_SHF S_FIRConfigS
+#define C1_FIR_S_MSK M_FIRConfigS
+
+#define C1_FIR_PRID_SHF S_FIRImp
+#define C1_FIR_PRID_MSK M_FIRImp
+
+#define C1_FIR_REV_SHF S_FIRRev
+#define C1_FIR_REV_MSK M_FIRRev
+
+
+/* FPU (CP1) FCSR control/status register */
+#define C1_FCSR_FCC_SHF S_FCSRFCC7_1
+#define C1_FCSR_FCC_MSK M_FCSRFCC7_1
+
+#define C1_FCSR_FS_SHF S_FCSRFS
+#define C1_FCSR_FS_MSK M_FCSRFS
+#define C1_FCSR_FS_BIT C1_FCSR_FS_MSK
+
+#define C1_FCSR_CC_SHF S_FCSRCC
+#define C1_FCSR_CC_MSK M_FCSRCC
+
+#define C1_FCSR_IMPL_SHF S_FCSRImpl
+#define C1_FCSR_IMPL_MSK M_FCSRImpl
+
+#define C1_FCSR_EXC_SHF S_FCSRExc
+#define C1_FCSR_EXC_MSK M_FCSRExc
+
+#define C1_FCSR_ENA_SHF S_FCSREna
+#define C1_FCSR_ENA_MSK M_FCSREna
+
+#define C1_FCSR_FLG_SHF S_FCSRFlg
+#define C1_FCSR_FLG_MSK M_FCSRFlg
+
+#define C1_FCSR_RM_SHF S_FCSRRM
+#define C1_FCSR_RM_MSK M_FCSRRM
+#define C1_FCSR_RM_RN K_FCSRRM_RN
+#define C1_FCSR_RM_RZ K_FCSRRM_RZ
+#define C1_FCSR_RM_RP K_FCSRRM_RP
+#define C1_FCSR_RM_RM K_FCSRRM_RM
+
+
+
+/* cache operations */
+
+#define CACHE_OP( code, type ) ( ((code) << 2) | (type) )
+
+#define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0)
+#define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0)
+#define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0)
+#define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1)
+#define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1)
+#define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1)
+#define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3)
+
+#define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0)
+#define ICACHE_ADDR_FILL CACHE_OP(0x5, 0)
+#define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0)
+#define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1)
+#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1)
+#define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1)
+#define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1)
+
+#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3)
+
+/* Workaround for bug in early revisions of MIPS 4K family of
+ * processors. Only relevant in early engineering samples of test
+ * chips (RTL revision <= 3.0).
+ *
+ * The bug is described in :
+ *
+ * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
+ * MIPS Document No: MD00003
+ *
+ * The bug is identified as : C16
+ */
+#ifndef SET_MIPS0
+#define SET_MIPS0()
+#define SET_PUSH()
+#define SET_POP()
+#endif
+#define ICACHE_INVALIDATE_WORKAROUND(reg) \
+SET_PUSH(); \
+SET_MIPS0(); \
+ la reg, 999f; \
+SET_POP(); \
+ cache ICACHE_ADDR_FILL, 0(reg); \
+ sync; \
+ nop; nop; nop; nop; \
+999:
+
+/* EMPTY_PIPELINE is used for the below cache invalidation operations.
+ * When $I is invalidated, there will still be operations in the
+ * pipeline. We make sure these are 'nop' operations.
+ */
+#define EMPTY_PIPELINE nop; nop; nop; nop
+
+#define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \
+ ICACHE_INVALIDATE_WORKAROUND(scratch); \
+ cache ICACHE_INDEX_INVALIDATE, 0(index); \
+ EMPTY_PIPELINE
+
+#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \
+ ICACHE_INVALIDATE_WORKAROUND(scratch); \
+ cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \
+ EMPTY_PIPELINE
+
+/* The sync used in the below macro is there in case we are installing
+ * a new instruction (flush $D, sync, invalidate $I sequence).
+ */
+#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \
+ cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \
+ sync; \
+ EMPTY_PIPELINE
+
+/* Config1 cache field decoding */
+#define CACHE_CALC_SPW(s) ( 64 << (s) )
+#define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 )
+#define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) )
+#define CACHE_CALC_ASSOC(a) ( (a) + 1 )
+
+
+/**** Move from/to Coprocessor operations ****/
+
+/* We use ssnop instead of nop operations in order to handle
+ * superscalar CPUs.
+ * The "sll zero,zero,1" notation is compiler backwards compatible.
+ */
+#define SSNOP sll zero,zero,1
+#define NOPS SSNOP; SSNOP; SSNOP; SSNOP
+
+#define MFLO(dst) \
+ mflo dst;\
+ NOPS
+
+/* Workaround for bug in early revisions of MIPS 4K family of
+ * processors.
+ *
+ * This concerns the nop instruction before mtc0 in the
+ * MTC0 macro below.
+ *
+ * The bug is described in :
+ *
+ * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
+ * MIPS Document No: MD00003
+ *
+ * The bug is identified as : C27
+ */
+
+#define MTC0(src, dst) \
+ nop; \
+ mtc0 src,dst;\
+ NOPS
+
+#define DMTC0(src, dst) \
+ nop; \
+ dmtc0 src,dst;\
+ NOPS
+
+#define MFC0(dst, src) \
+ mfc0 dst,src;\
+ NOPS
+
+#define DMFC0(dst, src) \
+ dmfc0 dst,src;\
+ NOPS
+
+#define MFC0_SEL_OPCODE(dst, src, sel)\
+ .##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\
+ NOPS
+
+#define MTC0_SEL_OPCODE(dst, src, sel)\
+ .##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\
+ NOPS
+
+#define LDC1(dst, src, offs)\
+ .##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs))
+
+#define SDC1(src, dst, offs)\
+ .##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs))
+
+
+/* Instruction opcode fields */
+#define OPC_SPECIAL 0x0
+#define OPC_REGIM 0x1
+#define OPC_J 0x2
+#define OPC_JAL 0x3
+#define OPC_BEQ 0x4
+#define OPC_BNE 0x5
+#define OPC_BLEZ 0x6
+#define OPC_BGTZ 0x7
+#define OPC_COP1 0x11
+#define OPC_JALX 0x1D
+#define OPC_BEQL 0x14
+#define OPC_BNEL 0x15
+#define OPC_BLEZL 0x16
+#define OPC_BGTZL 0x17
+
+/* Instruction function fields */
+#define FUNC_JR 0x8
+#define FUNC_JALR 0x9
+
+/* Instruction rt fields */
+#define RT_BLTZ 0x0
+#define RT_BGEZ 0x1
+#define RT_BLTZL 0x2
+#define RT_BGEZL 0x3
+#define RT_BLTZAL 0x10
+#define RT_BGEZAL 0x11
+#define RT_BLTZALL 0x12
+#define RT_BGEZALL 0x13
+
+/* Instruction rs fields */
+#define RS_BC1 0x08
+
+/* Access macros for instruction fields */
+#define MIPS_OPCODE( instr) ((instr) >> 26)
+#define MIPS_FUNCTION(instr) ((instr) & MSK(6))
+#define MIPS_RT(instr) (((instr) >> 16) & MSK(5))
+#define MIPS_RS(instr) (((instr) >> 21) & MSK(5))
+#define MIPS_OFFSET(instr) ((instr) & 0xFFFF)
+#define MIPS_TARGET(instr) ((instr) & MSK(26))
+
+/* Instructions */
+#define OPCODE_DERET 0x4200001f
+#define OPCODE_BREAK 0x0005000d
+#define OPCODE_NOP 0
+#define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) )
+
+#define DERET .##word OPCODE_DERET
+
+/* MIPS16e opcodes and instruction field access macros */
+
+#define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f)
+#define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7)
+#define MIPS16E_X(inst) (((inst) >> 26) & 0x1)
+#define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f)
+#define MIPS16E_RY(inst) (((inst) >> 5) & 0x3)
+#define MIPS16E_OPC_EXTEND 0x1e
+#define MIPS16E_OPC_JAL_X 0x03
+#define MIPS16E_OPC_B 0x02
+#define MIPS16E_OPC_BEQZ 0x04
+#define MIPS16E_OPC_BNEZ 0x05
+#define MIPS16E_OPC_I8 0x0c
+#define MIPS16E_I8_FUNC_BTEQZ 0x00
+#define MIPS16E_I8_FUNC_BTNEZ 0x01
+#define MIPS16E_X_JALX 0x01
+#define MIPS16E_OPC_RR 0x1d
+#define MIPS16E_RR_FUNC_JALRC 0x00
+#define MIPS16E_RR_RY_JRRX 0x00
+#define MIPS16E_RR_RY_JRRA 0x01
+#define MIPS16E_RR_RY_JALR 0x02
+#define MIPS16E_RR_RY_JRCRX 0x04
+#define MIPS16E_RR_RY_JRCRA 0x05
+#define MIPS16E_RR_RY_JALRC 0x06
+
+#define MIPS16E_OPCODE_BREAK 0xE805
+#define MIPS16E_OPCODE_NOP 0x6500
+
+/* MIPS reset vector */
+#define MIPS_RESET_VECTOR 0x1fc00000
+
+/* Clock periods per count register increment */
+#define MIPS4K_COUNT_CLK_PER_CYCLE 2
+#define MIPS5K_COUNT_CLK_PER_CYCLE 2
+#define MIPS20Kc_COUNT_CLK_PER_CYCLE 1
+
+
+/**** MIPS 4K/5K families specific fields of CONFIG register ****/
+
+#define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23
+#define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF)
+
+#define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU
+#define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF)
+
+
+/**** MIPS 20Kc specific fields of CONFIG register ****/
+
+#define C0_CONFIG_MIPS20KC_EC_SHF 28
+#define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF)
+
+#define C0_CONFIG_MIPS20KC_DD_SHF 27
+#define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF)
+#define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK
+
+#define C0_CONFIG_MIPS20KC_LP_SHF 26
+#define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF)
+#define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK
+
+#define C0_CONFIG_MIPS20KC_SP_SHF 25
+#define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF)
+#define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK
+
+#define C0_CONFIG_MIPS20KC_TI_SHF 24
+#define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF)
+#define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK
+
+
+/* ********************************************************************* */
+/* Interface function definition */
+
+
+/* ********************************************************************* */
+
+#endif /* #ifndef __MIPS_H__ */
diff --git a/firmware/export/mipsregs.h b/firmware/export/mipsregs.h
new file mode 100755
index 0000000000..e2935e3024
--- /dev/null
+++ b/firmware/export/mipsregs.h
@@ -0,0 +1,985 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Modified for further R[236]000 support by Paul M. Antoine, 1996.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ * Copyright (C) 2003 Maciej W. Rozycki
+ */
+#ifndef _ASM_MIPSREGS_H
+#define _ASM_MIPSREGS_H
+
+//#include <linux/config.h>
+//#include <linux/linkage.h>
+
+/*
+ * The following macros are especially useful for __asm__
+ * inline assembler.
+ */
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+/*
+ * Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ULCAST_
+#else
+#define _ULCAST_ (unsigned long)
+#endif
+
+/*
+ * Coprocessor 0 register names
+ */
+#define CP0_INDEX $0
+#define CP0_RANDOM $1
+#define CP0_ENTRYLO0 $2
+#define CP0_ENTRYLO1 $3
+#define CP0_CONF $3
+#define CP0_CONTEXT $4
+#define CP0_PAGEMASK $5
+#define CP0_WIRED $6
+#define CP0_INFO $7
+#define CP0_BADVADDR $8
+#define CP0_COUNT $9
+#define CP0_ENTRYHI $10
+#define CP0_COMPARE $11
+#define CP0_STATUS $12
+#define CP0_CAUSE $13
+#define CP0_EPC $14
+#define CP0_PRID $15
+#define CP0_CONFIG $16
+#define CP0_LLADDR $17
+#define CP0_WATCHLO $18
+#define CP0_WATCHHI $19
+#define CP0_XCONTEXT $20
+#define CP0_FRAMEMASK $21
+#define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
+#define CP0_PERFORMANCE $25
+#define CP0_ECC $26
+#define CP0_CACHEERR $27
+#define CP0_TAGLO $28
+#define CP0_TAGHI $29
+#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
+
+/*
+ * R4640/R4650 cp0 register names. These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux. A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE $0
+#define CP0_IBOUND $1
+#define CP0_DBASE $2
+#define CP0_DBOUND $3
+#define CP0_CALG $17
+#define CP0_IWATCH $18
+#define CP0_DWATCH $19
+
+/*
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0 $26
+#define CP0_S1_DERRADDR1 $27
+#define CP0_S1_INTCONTROL $20
+
+/*
+ * TX39 Series
+ */
+#define CP0_TX39_CACHE $7
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION $0
+#define CP1_STATUS $31
+
+/*
+ * FPU Status Register Values
+ */
+/*
+ * Status Register Values
+ */
+
+#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
+#define FPU_CSR_COND 0x00800000 /* $fcc0 */
+#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
+#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
+#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
+#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
+#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
+#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
+#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
+#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X 0x0003f000
+#define FPU_CSR_UNI_X 0x00020000
+#define FPU_CSR_INV_X 0x00010000
+#define FPU_CSR_DIV_X 0x00008000
+#define FPU_CSR_OVF_X 0x00004000
+#define FPU_CSR_UDF_X 0x00002000
+#define FPU_CSR_INE_X 0x00001000
+
+#define FPU_CSR_ALL_E 0x00000f80
+#define FPU_CSR_INV_E 0x00000800
+#define FPU_CSR_DIV_E 0x00000400
+#define FPU_CSR_OVF_E 0x00000200
+#define FPU_CSR_UDF_E 0x00000100
+#define FPU_CSR_INE_E 0x00000080
+
+#define FPU_CSR_ALL_S 0x0000007c
+#define FPU_CSR_INV_S 0x00000040
+#define FPU_CSR_DIV_S 0x00000020
+#define FPU_CSR_OVF_S 0x00000010
+#define FPU_CSR_UDF_S 0x00000008
+#define FPU_CSR_INE_S 0x00000004
+
+/* rounding mode */
+#define FPU_CSR_RN 0x0 /* nearest */
+#define FPU_CSR_RZ 0x1 /* towards zero */
+#define FPU_CSR_RU 0x2 /* towards +Infinity */
+#define FPU_CSR_RD 0x3 /* towards -Infinity */
+
+
+/*
+ * Values for PageMask register
+ */
+#ifdef CONFIG_CPU_VR41XX
+
+/* Why doesn't stupidity hurt ... */
+
+#define PM_1K 0x00000000
+#define PM_4K 0x00001800
+#define PM_16K 0x00007800
+#define PM_64K 0x0001f800
+#define PM_256K 0x0007f800
+
+#else
+
+#define PM_4K 0x00000000
+#define PM_16K 0x00006000
+#define PM_64K 0x0001e000
+#define PM_256K 0x0007e000
+#define PM_1M 0x001fe000
+#define PM_4M 0x007fe000
+#define PM_16M 0x01ffe000
+#define PM_64M 0x07ffe000
+#define PM_256M 0x1fffe000
+
+#endif
+
+/*
+ * Values used for computation of new tlb entries
+ */
+#define PL_4K 12
+#define PL_16K 14
+#define PL_64K 16
+#define PL_256K 18
+#define PL_1M 20
+#define PL_4M 22
+#define PL_16M 24
+#define PL_64M 26
+#define PL_256M 28
+
+/*
+ * R4x00 interrupt enable / cause bits
+ */
+#define IE_SW0 (_ULCAST_(1) << 8)
+#define IE_SW1 (_ULCAST_(1) << 9)
+#define IE_IRQ0 (_ULCAST_(1) << 10)
+#define IE_IRQ1 (_ULCAST_(1) << 11)
+#define IE_IRQ2 (_ULCAST_(1) << 12)
+#define IE_IRQ3 (_ULCAST_(1) << 13)
+#define IE_IRQ4 (_ULCAST_(1) << 14)
+#define IE_IRQ5 (_ULCAST_(1) << 15)
+
+/*
+ * R4x00 interrupt cause bits
+ */
+#define C_SW0 (_ULCAST_(1) << 8)
+#define C_SW1 (_ULCAST_(1) << 9)
+#define C_IRQ0 (_ULCAST_(1) << 10)
+#define C_IRQ1 (_ULCAST_(1) << 11)
+#define C_IRQ2 (_ULCAST_(1) << 12)
+#define C_IRQ3 (_ULCAST_(1) << 13)
+#define C_IRQ4 (_ULCAST_(1) << 14)
+#define C_IRQ5 (_ULCAST_(1) << 15)
+
+/*
+ * Bitfields in the R4xx0 cp0 status register
+ */
+#define ST0_IE 0x00000001
+#define ST0_EXL 0x00000002
+#define ST0_ERL 0x00000004
+#define ST0_KSU 0x00000018
+# define KSU_USER 0x00000010
+# define KSU_SUPERVISOR 0x00000008
+# define KSU_KERNEL 0x00000000
+#define ST0_UX 0x00000020
+#define ST0_SX 0x00000040
+#define ST0_KX 0x00000080
+#define ST0_DE 0x00010000
+#define ST0_CE 0x00020000
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_IEC 0x00000001
+#define ST0_KUC 0x00000002
+#define ST0_IEP 0x00000004
+#define ST0_KUP 0x00000008
+#define ST0_IEO 0x00000010
+#define ST0_KUO 0x00000020
+/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC 0x00010000
+#define ST0_SWC 0x00020000
+#define ST0_CM 0x00080000
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM (_ULCAST_(1) << 4)
+#define ST0_IL (_ULCAST_(1) << 23)
+#define ST0_DL (_ULCAST_(1) << 24)
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT 19
+#define TX39_CONF_ICS_MASK 0x00380000
+#define TX39_CONF_ICS_1KB 0x00000000
+#define TX39_CONF_ICS_2KB 0x00080000
+#define TX39_CONF_ICS_4KB 0x00100000
+#define TX39_CONF_ICS_8KB 0x00180000
+#define TX39_CONF_ICS_16KB 0x00200000
+
+#define TX39_CONF_DCS_SHIFT 16
+#define TX39_CONF_DCS_MASK 0x00070000
+#define TX39_CONF_DCS_1KB 0x00000000
+#define TX39_CONF_DCS_2KB 0x00010000
+#define TX39_CONF_DCS_4KB 0x00020000
+#define TX39_CONF_DCS_8KB 0x00030000
+#define TX39_CONF_DCS_16KB 0x00040000
+
+#define TX39_CONF_CWFON 0x00004000
+#define TX39_CONF_WBON 0x00002000
+#define TX39_CONF_RF_SHIFT 10
+#define TX39_CONF_RF_MASK 0x00000c00
+#define TX39_CONF_DOZE 0x00000200
+#define TX39_CONF_HALT 0x00000100
+#define TX39_CONF_LOCK 0x00000080
+#define TX39_CONF_ICE 0x00000020
+#define TX39_CONF_DCE 0x00000010
+#define TX39_CONF_IRSIZE_SHIFT 2
+#define TX39_CONF_IRSIZE_MASK 0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT 0
+#define TX39_CONF_DRSIZE_MASK 0x00000003
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define ST0_IM 0x0000ff00
+#define STATUSB_IP0 8
+#define STATUSF_IP0 (_ULCAST_(1) << 8)
+#define STATUSB_IP1 9
+#define STATUSF_IP1 (_ULCAST_(1) << 9)
+#define STATUSB_IP2 10
+#define STATUSF_IP2 (_ULCAST_(1) << 10)
+#define STATUSB_IP3 11
+#define STATUSF_IP3 (_ULCAST_(1) << 11)
+#define STATUSB_IP4 12
+#define STATUSF_IP4 (_ULCAST_(1) << 12)
+#define STATUSB_IP5 13
+#define STATUSF_IP5 (_ULCAST_(1) << 13)
+#define STATUSB_IP6 14
+#define STATUSF_IP6 (_ULCAST_(1) << 14)
+#define STATUSB_IP7 15
+#define STATUSF_IP7 (_ULCAST_(1) << 15)
+#define STATUSB_IP8 0
+#define STATUSF_IP8 (_ULCAST_(1) << 0)
+#define STATUSB_IP9 1
+#define STATUSF_IP9 (_ULCAST_(1) << 1)
+#define STATUSB_IP10 2
+#define STATUSF_IP10 (_ULCAST_(1) << 2)
+#define STATUSB_IP11 3
+#define STATUSF_IP11 (_ULCAST_(1) << 3)
+#define STATUSB_IP12 4
+#define STATUSF_IP12 (_ULCAST_(1) << 4)
+#define STATUSB_IP13 5
+#define STATUSF_IP13 (_ULCAST_(1) << 5)
+#define STATUSB_IP14 6
+#define STATUSF_IP14 (_ULCAST_(1) << 6)
+#define STATUSB_IP15 7
+#define STATUSF_IP15 (_ULCAST_(1) << 7)
+#define ST0_CH 0x00040000
+#define ST0_SR 0x00100000
+#define ST0_TS 0x00200000
+#define ST0_BEV 0x00400000
+#define ST0_RE 0x02000000
+#define ST0_FR 0x04000000
+#define ST0_CU 0xf0000000
+#define ST0_CU0 0x10000000
+#define ST0_CU1 0x20000000
+#define ST0_CU2 0x40000000
+#define ST0_CU3 0x80000000
+#define ST0_XX 0x80000000 /* MIPS IV naming */
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 cause register.
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define CAUSEB_EXCCODE 2
+#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
+#define CAUSEB_IP 8
+#define CAUSEF_IP (_ULCAST_(255) << 8)
+#define CAUSEB_IP0 8
+#define CAUSEF_IP0 (_ULCAST_(1) << 8)
+#define CAUSEB_IP1 9
+#define CAUSEF_IP1 (_ULCAST_(1) << 9)
+#define CAUSEB_IP2 10
+#define CAUSEF_IP2 (_ULCAST_(1) << 10)
+#define CAUSEB_IP3 11
+#define CAUSEF_IP3 (_ULCAST_(1) << 11)
+#define CAUSEB_IP4 12
+#define CAUSEF_IP4 (_ULCAST_(1) << 12)
+#define CAUSEB_IP5 13
+#define CAUSEF_IP5 (_ULCAST_(1) << 13)
+#define CAUSEB_IP6 14
+#define CAUSEF_IP6 (_ULCAST_(1) << 14)
+#define CAUSEB_IP7 15
+#define CAUSEF_IP7 (_ULCAST_(1) << 15)
+#define CAUSEB_IV 23
+#define CAUSEF_IV (_ULCAST_(1) << 23)
+#define CAUSEB_CE 28
+#define CAUSEF_CE (_ULCAST_(3) << 28)
+#define CAUSEB_BD 31
+#define CAUSEF_BD (_ULCAST_(1) << 31)
+
+/*
+ * Bits in the coprocessor 0 config register.
+ */
+/* Generic bits. */
+#define CONF_CM_CACHABLE_NO_WA 0
+#define CONF_CM_CACHABLE_WA 1
+#define CONF_CM_UNCACHED 2
+#define CONF_CM_CACHABLE_NONCOHERENT 3
+#define CONF_CM_CACHABLE_CE 4
+#define CONF_CM_CACHABLE_COW 5
+#define CONF_CM_CACHABLE_CUW 6
+#define CONF_CM_CACHABLE_ACCELERATED 7
+#define CONF_CM_CMASK 7
+#define CONF_BE (_ULCAST_(1) << 15)
+
+/* Bits common to various processors. */
+#define CONF_CU (_ULCAST_(1) << 3)
+#define CONF_DB (_ULCAST_(1) << 4)
+#define CONF_IB (_ULCAST_(1) << 5)
+#define CONF_DC (_ULCAST_(7) << 6)
+#define CONF_IC (_ULCAST_(7) << 9)
+#define CONF_EB (_ULCAST_(1) << 13)
+#define CONF_EM (_ULCAST_(1) << 14)
+#define CONF_SM (_ULCAST_(1) << 16)
+#define CONF_SC (_ULCAST_(1) << 17)
+#define CONF_EW (_ULCAST_(3) << 18)
+#define CONF_EP (_ULCAST_(15)<< 24)
+#define CONF_EC (_ULCAST_(7) << 28)
+#define CONF_CM (_ULCAST_(1) << 31)
+
+/* Bits specific to the R4xx0. */
+#define R4K_CONF_SW (_ULCAST_(1) << 20)
+#define R4K_CONF_SS (_ULCAST_(1) << 21)
+#define R4K_CONF_SB (_ULCAST_(3) << 22)
+
+/* Bits specific to the R5000. */
+#define R5K_CONF_SE (_ULCAST_(1) << 12)
+#define R5K_CONF_SS (_ULCAST_(3) << 20)
+
+/* Bits specific to the R10000. */
+#define R10K_CONF_DN (_ULCAST_(3) << 3)
+#define R10K_CONF_CT (_ULCAST_(1) << 5)
+#define R10K_CONF_PE (_ULCAST_(1) << 6)
+#define R10K_CONF_PM (_ULCAST_(3) << 7)
+#define R10K_CONF_EC (_ULCAST_(15)<< 9)
+#define R10K_CONF_SB (_ULCAST_(1) << 13)
+#define R10K_CONF_SK (_ULCAST_(1) << 14)
+#define R10K_CONF_SS (_ULCAST_(7) << 16)
+#define R10K_CONF_SC (_ULCAST_(7) << 19)
+#define R10K_CONF_DC (_ULCAST_(7) << 26)
+#define R10K_CONF_IC (_ULCAST_(7) << 29)
+
+/* Bits specific to the VR41xx. */
+#define VR41_CONF_CS (_ULCAST_(1) << 12)
+#define VR41_CONF_M16 (_ULCAST_(1) << 20)
+#define VR41_CONF_AD (_ULCAST_(1) << 23)
+
+/* Bits specific to the R30xx. */
+#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
+#define R30XX_CONF_REV (_ULCAST_(1) << 22)
+#define R30XX_CONF_AC (_ULCAST_(1) << 23)
+#define R30XX_CONF_RF (_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
+#define R30XX_CONF_SB (_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
+
+/* Bits specific to the TX49. */
+#define TX49_CONF_DC (_ULCAST_(1) << 16)
+#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
+#define TX49_CONF_HALT (_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
+
+/* Bits specific to the MIPS32/64 PRA. */
+#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+#define MIPS_CONF_AR (_ULCAST_(7) << 10)
+#define MIPS_CONF_AT (_ULCAST_(3) << 13)
+#define MIPS_CONF_M (_ULCAST_(1) << 31)
+
+/*
+ * R10000 performance counter definitions.
+ *
+ * FIXME: The R10000 performance counter opens a nice way to implement CPU
+ * time accounting with a precission of one cycle. I don't have
+ * R10000 silicon but just a manual, so ...
+ */
+
+/*
+ * Events counted by counter #0
+ */
+#define CE0_CYCLES 0
+#define CE0_INSN_ISSUED 1
+#define CE0_LPSC_ISSUED 2
+#define CE0_S_ISSUED 3
+#define CE0_SC_ISSUED 4
+#define CE0_SC_FAILED 5
+#define CE0_BRANCH_DECODED 6
+#define CE0_QW_WB_SECONDARY 7
+#define CE0_CORRECTED_ECC_ERRORS 8
+#define CE0_ICACHE_MISSES 9
+#define CE0_SCACHE_I_MISSES 10
+#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
+#define CE0_EXT_INTERVENTIONS_REQ 12
+#define CE0_EXT_INVALIDATE_REQ 13
+#define CE0_VIRTUAL_COHERENCY_COND 14
+#define CE0_INSN_GRADUATED 15
+
+/*
+ * Events counted by counter #1
+ */
+#define CE1_CYCLES 0
+#define CE1_INSN_GRADUATED 1
+#define CE1_LPSC_GRADUATED 2
+#define CE1_S_GRADUATED 3
+#define CE1_SC_GRADUATED 4
+#define CE1_FP_INSN_GRADUATED 5
+#define CE1_QW_WB_PRIMARY 6
+#define CE1_TLB_REFILL 7
+#define CE1_BRANCH_MISSPREDICTED 8
+#define CE1_DCACHE_MISS 9
+#define CE1_SCACHE_D_MISSES 10
+#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
+#define CE1_EXT_INTERVENTION_HITS 12
+#define CE1_EXT_INVALIDATE_REQ 13
+#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
+#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
+
+/*
+ * These flags define in which priviledge mode the counters count events
+ */
+#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
+#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
+#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
+#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+
+#ifndef __ASSEMBLY__
+
+#define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE)
+#define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2))
+
+/*
+ * Functions to access the r10k performance counter and control registers
+ */
+#define read_r10k_perf_cntr(counter) \
+({ unsigned int __res; \
+ __asm__ __volatile__( \
+ "mfpc\t%0, "STR(counter) \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_r10k_perf_cntr(counter,val) \
+ __asm__ __volatile__( \
+ "mtpc\t%0, "STR(counter) \
+ : : "r" (val));
+
+#define read_r10k_perf_cntl(counter) \
+({ unsigned int __res; \
+ __asm__ __volatile__( \
+ "mfps\t%0, "STR(counter) \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_r10k_perf_cntl(counter,val) \
+ __asm__ __volatile__( \
+ "mtps\t%0, "STR(counter) \
+ : : "r" (val));
+
+/*
+ * Macros to access the system control coprocessor
+ */
+
+#define __read_32bit_c0_register(source, sel) \
+({ int __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mfc0\t%0, " #source "\n\t" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0\n\t" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define __read_64bit_c0_register(source, sel) \
+({ unsigned long __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0, " #source "\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define __write_32bit_c0_register(register, sel, value) \
+do { \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mtc0\t%z0, " #register "\n\t" \
+ : : "Jr" (value)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mtc0\t%z0, " #register ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
+} while (0)
+
+#define __write_64bit_c0_register(register, sel, value) \
+do { \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%z0, " #register "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmtc0\t%z0, " #register ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
+} while (0)
+
+#define __read_ulong_c0_register(reg, sel) \
+ ((sizeof(unsigned long) == 4) ? \
+ __read_32bit_c0_register(reg, sel) : \
+ __read_64bit_c0_register(reg, sel))
+
+#define __write_ulong_c0_register(reg, sel, val) \
+do { \
+ if (sizeof(unsigned long) == 4) \
+ __write_32bit_c0_register(reg, sel, val); \
+ else \
+ __write_64bit_c0_register(reg, sel, val); \
+} while (0)
+
+/*
+ * These versions are only needed for systems with more than 38 bits of
+ * physical address space running the 32-bit kernel. That's none atm :-)
+ */
+#define __read_64bit_c0_split(source, sel) \
+({ \
+ unsigned long long val; \
+ unsigned long flags; \
+ \
+ local_irq_save(flags); \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%M0, " #source "\n\t" \
+ "dsll\t%L0, %M0, 32\n\t" \
+ "dsrl\t%M0, %M0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ ".set\tmips0" \
+ : "=r" (val)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%M0, " #source ", " #sel "\n\t" \
+ "dsll\t%L0, %M0, 32\n\t" \
+ "dsrl\t%M0, %M0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ ".set\tmips0" \
+ : "=r" (val)); \
+ local_irq_restore(flags); \
+ \
+ val; \
+})
+
+#define __write_64bit_c0_split(source, sel, val) \
+do { \
+ unsigned long flags; \
+ \
+ local_irq_save(flags); \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dsll\t%L0, %L0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ "dsll\t%M0, %M0, 32\n\t" \
+ "or\t%L0, %L0, %M0\n\t" \
+ "dmtc0\t%L0, " #source "\n\t" \
+ ".set\tmips0" \
+ : : "r" (val)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dsll\t%L0, %L0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ "dsll\t%M0, %M0, 32\n\t" \
+ "or\t%L0, %L0, %M0\n\t" \
+ "dmtc0\t%L0, " #source ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "r" (val)); \
+ local_irq_restore(flags); \
+} while (0)
+
+#define read_c0_index() __read_32bit_c0_register($0, 0)
+#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
+
+#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
+
+#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
+
+#define read_c0_conf() __read_32bit_c0_register($3, 0)
+#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
+
+#define read_c0_context() __read_ulong_c0_register($4, 0)
+#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
+
+#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
+
+#define read_c0_wired() __read_32bit_c0_register($6, 0)
+#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info() __read_32bit_c0_register($7, 0)
+
+#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
+#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_count() __read_32bit_c0_register($9, 0)
+#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
+
+#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
+
+#define read_c0_compare() __read_32bit_c0_register($11, 0)
+#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
+
+#define read_c0_status() __read_32bit_c0_register($12, 0)
+#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
+
+#define read_c0_cause() __read_32bit_c0_register($13, 0)
+#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
+
+#define read_c0_prid() __read_32bit_c0_register($15, 0)
+
+#define read_c0_config() __read_32bit_c0_register($16, 0)
+#define read_c0_config1() __read_32bit_c0_register($16, 1)
+#define read_c0_config2() __read_32bit_c0_register($16, 2)
+#define read_c0_config3() __read_32bit_c0_register($16, 3)
+#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
+
+/*
+ * The WatchLo register. There may be upto 8 of them.
+ */
+#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
+
+/*
+ * The WatchHi register. There may be upto 8 of them.
+ */
+#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
+
+#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
+
+#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
+
+#define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
+#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
+
+#define read_c0_framemask() __read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
+
+#define read_c0_debug() __read_32bit_c0_register($23, 0)
+#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
+
+#define read_c0_depc() __read_ulong_c0_register($24, 0)
+#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
+
+#define read_c0_ecc() __read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
+
+#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+
+#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
+
+#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+
+#define read_c0_taglo() __read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
+
+#define read_c0_taghi() __read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
+
+#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
+
+#define read_c0_epc() __read_ulong_c0_register($14, 0)
+#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
+
+#if 1
+/*
+ * Macros to access the system control coprocessor
+ */
+#define read_32bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "mfc0\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+#define read_32bit_cp0_set1_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "cfc0\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+/*
+ * For now use this only with interrupts disabled!
+ */
+#define read_64bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0,"STR(source)"\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_32bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ "mtc0\t%0,"STR(register)"\n\t" \
+ "nop" \
+ : : "r" (value));
+
+#define write_32bit_cp0_set1_register(register,value) \
+ __asm__ __volatile__( \
+ "ctc0\t%0,"STR(register)"\n\t" \
+ "nop" \
+ : : "r" (value));
+
+#define write_64bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%0,"STR(register)"\n\t" \
+ ".set\tmips0" \
+ : : "r" (value))
+
+/*
+ * This should be changed when we get a compiler that support the MIPS32 ISA.
+ */
+#define read_mips32_cp0_config1() \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tnoreorder\n\t" \
+ ".set\tnoat\n\t" \
+ "#.set\tmips64\n\t" \
+ "#mfc0\t$1, $16, 1\n\t" \
+ "#.set\tmips0\n\t" \
+ ".word\t0x40018001\n\t" \
+ "move\t%0,$1\n\t" \
+ ".set\tat\n\t" \
+ ".set\treorder" \
+ :"=r" (__res)); \
+ __res;})
+
+#endif
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define read_32bit_cp1_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "cfc1\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+/* TLB operations. */
+static inline void tlb_probe(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbp\n\t"
+ ".set reorder");
+}
+
+static inline void tlb_read(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbr\n\t"
+ ".set reorder");
+}
+
+static inline void tlb_write_indexed(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbwi\n\t"
+ ".set reorder");
+}
+
+static inline void tlb_write_random(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbwr\n\t"
+ ".set reorder");
+}
+
+/*
+ * Manipulate bits in a c0 register.
+ */
+#define __BUILD_SET_C0(name,register) \
+static inline unsigned int \
+set_c0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_c0_##name(); \
+ res |= set; \
+ write_c0_##name(res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+clear_c0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_c0_##name(); \
+ res &= ~clear; \
+ write_c0_##name(res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+change_c0_##name(unsigned int change, unsigned int new) \
+{ \
+ unsigned int res; \
+ \
+ res = read_c0_##name(); \
+ res &= ~change; \
+ res |= (new & change); \
+ write_c0_##name(res); \
+ \
+ return res; \
+}
+
+__BUILD_SET_C0(status,CP0_STATUS)
+__BUILD_SET_C0(cause,CP0_CAUSE)
+__BUILD_SET_C0(config,CP0_CONFIG)
+
+#define set_cp0_status(x) set_c0_status(x)
+#define set_cp0_cause(x) set_c0_cause(x)
+#define set_cp0_config(x) set_c0_config(x)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_MIPSREGS_H */
diff --git a/firmware/export/thread.h b/firmware/export/thread.h
index 1d5c25c649..ecba179693 100644
--- a/firmware/export/thread.h
+++ b/firmware/export/thread.h
@@ -109,6 +109,14 @@ struct regs
uint32_t lr; /* 36 - r14 (lr) */
uint32_t start; /* 40 - Thread start address, or NULL when started */
};
+#elif defined(CPU_MIPS)
+struct regs
+{
+ uint32_t r[27]; /* 0-104 - Registers $1, v0-v1, a0-a3, t0-t9, s0-s7, gp, fp */
+ uint32_t sp; /* 108 - Stack pointer */
+ uint32_t ra; /* 112 - Return address */
+ uint32_t start; /* 116 - Thread start address, or NULL when started */
+};
#endif /* CONFIG_CPU */
#else
struct regs
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-jz4740.c
new file mode 100755
index 0000000000..b907bb86df
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/ata-jz4740.c
@@ -0,0 +1,40 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "jz4740.h"
+#include "ata.h"
+
+int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
+{
+ (void)start;
+ (void)count;
+ (void)buf;
+ return 0;
+}
+
+int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
+{
+ (void)start;
+ (void)count;
+ (void)buf;
+ return 0;
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/boot.lds b/firmware/target/mips/ingenic_jz47xx/boot.lds
new file mode 100755
index 0000000000..9bc635afad
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/boot.lds
@@ -0,0 +1,107 @@
+#include "config.h"
+#undef mips
+
+OUTPUT_FORMAT("elf32-tradlittlemips")
+OUTPUT_ARCH(MIPS)
+ENTRY(_start)
+STARTUP(target/mips/ingenic_jz47xx/crt0.o)
+
+#define DRAMSIZE (MEMORYSIZE * 0x100000)
+
+#define DRAMORIG 0x80E00000 /* HACK */
+#define IRAMORIG 0x80000000
+#define IRAMSIZE 16K
+
+MEMORY
+{
+ DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
+ IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
+}
+
+SECTIONS
+{
+ . = DRAMORIG;
+
+ .text : {
+ loadaddress = .;
+ _loadaddress = .;
+ *(.init.text);
+ *(.text*);
+ *(.glue_7);
+ *(.glue_7t);
+ . = ALIGN(0x4);
+ } > DRAM
+
+ . = ALIGN(4);
+
+ .rodata :
+ {
+ *(.rodata); /* problems without this, dunno why */
+ *(.rodata*);
+ *(.rodata.str1.1);
+ *(.rodata.str1.4);
+ . = ALIGN(0x4);
+
+ /* Pseudo-allocate the copies of the data sections */
+ _datacopy = .;
+ } > DRAM
+
+ . = ALIGN(4);
+
+ .data : {
+ *(.icode);
+ *(.irodata);
+ *(.idata);
+ *(.data*);
+ *(.scommon*);
+ *(.sdata*);
+ . = ALIGN(0x4);
+ _dataend = . ;
+ } > DRAM
+
+ . = ALIGN(4);
+
+ _gp = ALIGN(16);
+ .got : {
+ *(.got*)
+ }> DRAM
+
+ . = ALIGN(4);
+
+ .stack :
+ {
+ *(.stack)
+ _stackbegin = .;
+ stackbegin = .;
+ . += 0x2000;
+ _stackend = .;
+ stackend = .;
+ } > DRAM
+
+ . = ALIGN(4);
+
+ .bss :
+ {
+ _edata = .;
+ *(.sbss*);
+ *(.bss*);
+ *(.ibss);
+ *(COMMON)
+ _end = .;
+ } > DRAM
+
+ . = ALIGN(4);
+
+ .vectors IRAMORIG :
+ {
+ _vectorsstart = .;
+ KEEP(*(.resetvectors));
+ *(.resetvectors);
+ KEEP(*(.vectors));
+ *(.vectors);
+ _vectorsend = .;
+ } AT > DRAM
+ _vectorscopy = LOADADDR(.vectors);
+
+ . = ALIGN(4);
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S
new file mode 100755
index 0000000000..6ac9ad71ab
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/crt0.S
@@ -0,0 +1,246 @@
+/*
+ * init.S
+ *
+ * Initialization code for JzRISC.
+ *
+ * Author: Seeger Chin
+ * e-mail: seeger.chin@gmail.com
+ *
+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "config.h"
+#include "mips.h"
+
+ .text
+
+ .set mips3
+
+ .extern main
+
+ .global _start
+#ifdef BOOTLOADER
+ .section .init.text,"ax",%progbits
+#else
+ .section .resetvectors,"ax",%progbits
+#endif
+ .set noreorder
+ .set noat
+
+#ifdef BOOTLOADER
+ .word 0 /* HACK */
+ .word 0 /* HACK */
+#endif
+_start:
+ la ra, _start
+ //----------------------------------------------------
+ // init cp0 registers.
+ //----------------------------------------------------
+ mtc0 zero, C0_WATCHLO
+ mtc0 zero, C0_WATCHHI
+
+ li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \
+ | M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \
+ | M_StatusIM2 | M_StatusERL)
+ // BEV = Enable Boot Exception Vectors
+ // IMx = Interrupt mask
+ // ERL = Denotes error level
+ mtc0 t0, C0_STATUS
+
+ li t1, M_CauseIV
+ mtc0 t1, C0_CAUSE
+
+ //----------------------------------------------------
+ // init caches, assumes a 4way*128set*32byte i/d cache
+ //----------------------------------------------------
+ li t0, 3 // enable cache for kseg0 accesses
+ mtc0 t0, C0_CONFIG // CONFIG reg
+ la t0, 0x80000000 // an idx op should use a unmappable address
+ ori t1, t0, 0x4000 // 16kB cache
+ mtc0 zero, C0_TAGLO // TAGLO reg
+ mtc0 zero, C0_TAGHI // TAGHI reg
+
+_init_cache_loop:
+ cache 0x8, 0(t0) // index store icache tag
+ cache 0x9, 0(t0) // index store dcache tag
+ bne t0, t1, _init_cache_loop
+ addiu t0, t0, 0x20 // 32 bytes per cache line
+ nop
+
+ //----------------------------------------------------
+ // Invalidate BTB
+ //----------------------------------------------------
+ mfc0 t0, C0_CONFIG
+ nop
+ ori t0, 2
+ mtc0 t0, C0_CONFIG
+ nop
+
+ //----------------------------------------------------
+ // setup stack, jump to C code
+ //----------------------------------------------------
+ la sp, stackend
+ la t0, stackbegin
+ li t1, 0xDEADBEEF
+
+_init_stack_loop:
+ sw t1, 0(t0)
+ bne t0, sp, _init_stack_loop
+ addiu t0, t0, 4
+
+ la t0, main
+ jr t0
+ nop
+
+
+#ifndef BOOTLOADER
+ .section .vectors,"ax",%progbits
+#endif
+ .extern exception_handler
+ .global except_common_entry
+ .type except_common_entry,@function
+except_common_entry:
+ la k0, exception_handler
+ jr k0
+ nop
+ nop
+ nop
+
+ .extern _int
+ .extern _exception
+ .global exception_handler
+ .type exception_handler,@function
+ .set noreorder
+exception_handler:
+
+
+ addiu sp, -0x80 # Add Immediate Unsigned
+ sw ra, 0(sp) # Store Word
+ sw fp, 4(sp) # Store Word
+ sw gp, 8(sp) # Store Word
+ sw t9, 0xC(sp) # Store Word
+ sw t8, 0x10(sp) # Store Word
+ sw s7, 0x14(sp) # Store Word
+ sw s6, 0x18(sp) # Store Word
+ sw s5, 0x1C(sp) # Store Word
+ sw s4, 0x20(sp) # Store Word
+ sw s3, 0x24(sp) # Store Word
+ sw s2, 0x28(sp) # Store Word
+ sw s1, 0x2C(sp) # Store Word
+ sw s0, 0x30(sp) # Store Word
+ sw t7, 0x34(sp) # Store Word
+ sw t6, 0x38(sp) # Store Word
+ sw t5, 0x3C(sp) # Store Word
+ sw t4, 0x40(sp) # Store Word
+ sw t3, 0x44(sp) # Store Word
+ sw t2, 0x48(sp) # Store Word
+ sw t1, 0x4C(sp) # Store Word
+ sw t0, 0x50(sp) # Store Word
+ sw a3, 0x54(sp) # Store Word
+ sw a2, 0x58(sp) # Store Word
+ sw a1, 0x5C(sp) # Store Word
+ sw a0, 0x60(sp) # Store Word
+ sw v1, 0x64(sp) # Store Word
+ sw v0, 0x68(sp) # Store Word
+ sw $1, 0x6C(sp) # Store Word
+ mflo t0 # Move F LO
+ nop
+ sw t0, 0x70(sp) # Store Word
+ mfhi t0 # Move F HI
+ nop
+ sw t0, 0x74(sp) # Store Word
+ mfc0 t0, C0_STATUS # Status register
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sw t0, 0x78(sp) # Store Word
+ mfc0 t0, C0_EPC # Exception Program Counter
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sw t0, 0x7C(sp) # Store Word
+ li k1, 0x7C # Load Immediate
+ mfc0 k0, C0_CAUSE # C0_CAUSE of last exception
+ and k0, k1 # AND
+ beq zero, k0, _int # Branch on Equal
+ nop
+ la k0, _exception
+ jr k0
+ nop
+
+ .global _int
+ .type _int,@function
+_int:
+ jal intr_handler # Jump And Link
+ nop
+ lw ra, 0(sp) # Load Word
+ lw fp, 4(sp) # Load Word
+ sw gp, 8(sp) # Store Word
+ lw t9, 0xC(sp) # Load Word
+ lw t8, 0x10(sp) # Load Word
+ lw s7, 0x14(sp) # Load Word
+ lw s6, 0x18(sp) # Load Word
+ lw s5, 0x1C(sp) # Load Word
+ lw s4, 0x20(sp) # Load Word
+ lw s3, 0x24(sp) # Load Word
+ lw s2, 0x28(sp) # Load Word
+ lw s1, 0x2C(sp) # Load Word
+ lw s0, 0x30(sp) # Load Word
+ lw t7, 0x34(sp) # Load Word
+ lw t6, 0x38(sp) # Load Word
+ lw t5, 0x3C(sp) # Load Word
+ lw t4, 0x40(sp) # Load Word
+ lw t3, 0x44(sp) # Load Word
+ lw t2, 0x48(sp) # Load Word
+ lw t1, 0x4C(sp) # Load Word
+ lw t0, 0x50(sp) # Load Word
+ lw a3, 0x54(sp) # Load Word
+ lw a2, 0x58(sp) # Load Word
+ lw a1, 0x5C(sp) # Load Word
+ lw a0, 0x60(sp) # Load Word
+ lw v1, 0x64(sp) # Load Word
+ lw v0, 0x68(sp) # Load Word
+ lw v1, 0x6C(sp) # Load Word
+ lw k0, 0x70(sp) # Load Word
+ mtlo k0 # Move To LO
+ nop
+ lw k0, 0x74(sp) # Load Word
+ mthi k0 # Move To HI
+ nop
+ lw k0, 0x78(sp) # Load Word
+ nop
+ mtc0 k0, C0_STATUS # Status register
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ lw k0, 0x7C(sp) # Load Word
+ nop
+ mtc0 k0, C0_EPC # Exception Program Counter
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ sll zero, 1 # Shift Left Logical
+ addiu sp, 0x80 # Add Immediate Unsigned
+ eret # Exception Return
+ nop
+
+ .extern _except_handler
+ .global _exception
+ .type _exception,@function
+_exception:
+ move a0, sp
+ mfc0 a1, C0_CAUSE # C0_CAUSE of last exception
+ mfc0 a2, C0_EPC # Exception Program Counter
+ la k0, except_handler # Load Address
+ jr k0 # Jump Register
+ nop
+
+ .set reorder
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
new file mode 100755
index 0000000000..429178aeee
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
@@ -0,0 +1,94 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "jz4740.h"
+#include "lcd.h"
+#include "lcd-target.h"
+
+static volatile bool _lcd_on = false;
+static volatile bool lcd_poweroff = false;
+
+/* LCD init */
+void lcd_init_device(void)
+{
+ lcd_init_controller();
+ _lcd_on = true;
+}
+
+void lcd_enable(bool state)
+{
+ if(state)
+ lcd_on();
+ else
+ lcd_off();
+
+ _lcd_on = state;
+}
+
+bool lcd_enabled(void)
+{
+ return _lcd_on;
+}
+
+#define LCDADDR(x, y) ((unsigned int)&lcd_framebuffer[(y)][(x)])
+#define LCD_UNCACHED(addr) ((unsigned int)(addr) | 0xA0000000)
+
+/* Update a fraction of the display. */
+void lcd_update_rect(int x, int y, int width, int height)
+{
+ /* HACKY... */
+ x=0; y=0; width=400; height=240;
+ lcd_set_target(x, y, width-1, height-1);
+
+ REG_DMAC_DCCSR(0) = 0;
+ REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
+ REG_DMAC_DSAR(0) = LCDADDR(x,y) & 0x1FFFFFFF;
+#if 0
+ REG_DMAC_DTAR(0) = LCD_UNCACHED(SLCD_FIFO);
+#else
+ REG_DMAC_DTAR(0) = 0x130500B0; /* SLCD_FIFO */
+#endif
+ REG_DMAC_DTCR(0) = (width*height);
+
+ REG_DMAC_DCMD(0) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */
+ | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */
+ REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */
+
+ jz_flush_icache();
+
+ REG_DMAC_DMACR = DMAC_DMACR_DMAE;
+
+ while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) )
+ asm("nop");
+
+ //REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_TT;
+}
+
+/* Update the display.
+ This must be called after all other LCD functions that change the display. */
+void lcd_update(void)
+{
+ if (!_lcd_on)
+ return;
+
+ lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h
new file mode 100755
index 0000000000..e74f008a3e
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h
@@ -0,0 +1,28 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef _ADC_TARGET_H_
+#define _ADC_TARGET_H_
+
+#define NUM_ADC_CHANNELS 4
+
+#define ADC_BUTTONS 0
+
+#endif /* _ADC_TARGET_H_ */
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c
new file mode 100755
index 0000000000..9deab7712a
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c
@@ -0,0 +1,80 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "jz4740.h"
+#include "backlight-target.h"
+
+#define GPIO_PWM 123
+#define PWM_CHN 7
+#define PWM_FULL 101
+
+static void set_backlight(int unk, int val)
+{
+ if(val == 0)
+ __gpio_as_pwm7();
+ else
+ {
+ REG_TCU_TCSR(7) |= 2;
+ REG_TCU_TCSR(7) &= ~0x100;
+ int tmp;
+ tmp = (unk/2 + __cpm_get_rtcclk()) / unk;
+ if(tmp > 0xFFFF)
+ tmp = 0xFFFF;
+
+ __tcu_set_half_data(7, (tmp * unk * 1374389535) >> 5);
+ __tcu_set_full_data(7, tmp);
+
+ REG_TCU_TSCR = (1 << 7);
+ REG_TCU_TESR = (1 << 7);
+
+ __tcu_enable_pwm_output(7);
+ }
+ __tcu_set_count(7, 0);
+}
+
+bool _backlight_init(void)
+{
+ __gpio_as_pwm7();
+
+ __tcu_stop_counter(7);
+ __tcu_disable_pwm_output(7);
+
+ set_backlight(300, 7);
+
+ return true;
+}
+void _backlight_on(void)
+{
+ set_backlight(300, 7);
+}
+void _backlight_off(void)
+{
+ set_backlight(300, 0);
+}
+
+#ifdef HAVE_BACKLIGHT_BRIGHTNESS
+void _backlight_set_brightness(int brightness)
+{
+ (void)brightness;
+ return;
+}
+#endif
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h
new file mode 100755
index 0000000000..4170f96cc0
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef BACKLIGHT_TARGET_H
+#define BACKLIGHT_TARGET_H
+
+#ifdef BOOTLOADER
+#define BACKLIGHT_DRIVER_CLOSE
+/* Force the whole driver to be built */
+#define BACKLIGHT_FULL_INIT
+#endif
+
+#include <stdbool.h>
+
+bool _backlight_init(void);
+void _backlight_on(void);
+void _backlight_off(void);
+void _backlight_set_brightness(int brightness);
+
+#endif /* BACKLIGHT_TARGET_H */
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c
new file mode 100755
index 0000000000..e42325bcb3
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c
@@ -0,0 +1,123 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "jz4740.h"
+#include "button-target.h"
+
+#define BTN_VOL_DOWN (1 << 27)
+#define BTN_VOL_UP (1 << 0)
+#define BTN_MENU (1 << 1)
+#define BTN_OFF (1 << 29)
+#define BTN_HOLD (1 << 16)
+#define BTN_MASK (BTN_VOL_DOWN | BTN_VOL_UP \
+ | BTN_MENU | BTN_OFF )
+
+#define SADC_CFG_INIT ( \
+ (2 << SADC_CFG_CLKOUT_NUM_BIT) | \
+ SADC_CFG_XYZ1Z2 | \
+ SADC_CFG_SNUM_5 | \
+ (1 << SADC_CFG_CLKDIV_BIT) | \
+ SADC_CFG_PBAT_HIGH | \
+ SADC_CFG_CMD_INT_PEN )
+
+bool button_hold(void)
+{
+ return (REG_GPIO_PXPIN(3) ^ BTN_HOLD ? 1 : 0);
+}
+
+void button_init_device(void)
+{
+ REG_SADC_ENA = 0;
+ REG_SADC_STATE &= (~REG_SADC_STATE);
+ REG_SADC_CTRL = 0x1f;
+
+ __cpm_start_sadc();
+ REG_SADC_CFG = SADC_CFG_INIT;
+
+ REG_SADC_SAMETIME = 1;
+ REG_SADC_WAITTIME = 1000; //per 100 HZ
+ REG_SADC_STATE &= (~REG_SADC_STATE);
+ REG_SADC_CTRL &= (~(SADC_CTRL_PENDM | SADC_CTRL_TSRDYM));
+ REG_SADC_ENA = SADC_ENA_TSEN; // | REG_SADC_ENA;//SADC_ENA_TSEN | SADC_ENA_PBATEN | SADC_ENA_SADCINEN;
+}
+
+static int touch_to_pixels(short x, short y)
+{
+ /* X:300 -> 3800 Y:300->3900 */
+ x -= 300;
+ y -= 300;
+
+ x /= 3200 / LCD_WIDTH;
+ y /= 3600 / LCD_HEIGHT;
+
+ return (x << 16) | y;
+}
+
+int button_read_device(int *data)
+{
+ unsigned int key = ~REG_GPIO_PXPIN(3);
+ int ret = 0;
+ if(key & BTN_MASK)
+ {
+ if(key & BTN_VOL_DOWN)
+ ret |= BUTTON_VOL_DOWN;
+ if(key & BTN_VOL_UP)
+ ret |= BUTTON_VOL_UP;
+ if(key & BTN_MENU)
+ ret |= BUTTON_MENU;
+ if(key & BTN_OFF)
+ ret |= BUTTON_POWER;
+ }
+
+ if(REG_SADC_STATE & (SADC_CTRL_TSRDYM|SADC_STATE_PEND))
+ {
+ if(REG_SADC_STATE & SADC_CTRL_PENDM)
+ {
+ REG_SADC_CTRL &= (~(SADC_CTRL_PENUM | SADC_CTRL_TSRDYM));
+ REG_SADC_CTRL |= (SADC_CTRL_PENDM);
+ unsigned int dat;
+ unsigned short xData,yData;
+ short tsz1Data,tsz2Data;
+
+ dat = REG_SADC_TSDAT;
+
+ xData = (dat >> 0) & 0xfff;
+ yData = (dat >> 16) & 0xfff;
+
+ dat = REG_SADC_TSDAT;
+ tsz1Data = (dat >> 0) & 0xfff;
+ tsz2Data = (dat >> 16) & 0xfff;
+
+ *data = touch_to_pixels(xData, yData);
+
+ tsz1Data = tsz2Data - tsz1Data;
+ }
+ REG_SADC_STATE = 0;
+ //__intc_unmask_irq(IRQ_SADC);
+ }
+
+ return ret;
+}
+void button_set_touch_available(void)
+{
+ return;
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h
new file mode 100755
index 0000000000..23ce386cb1
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h
@@ -0,0 +1,69 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef BUTTON_TARGET_H
+#define BUTTON_TARGET_H
+
+
+#include <stdbool.h>
+#include "config.h"
+
+#define HAS_BUTTON_HOLD
+
+bool button_hold(void);
+void button_init_device(void);
+int button_read_device(int *data);
+void button_set_touch_available(void);
+
+/* Main unit's buttons */
+#define BUTTON_POWER 0x00000001
+#define BUTTON_VOL_UP 0x00000002
+#define BUTTON_VOL_DOWN 0x00000004
+#define BUTTON_MENU 0x00000008
+
+/* Compatibility hacks for flipping. Needs a somewhat better fix. */
+#define BUTTON_LEFT BUTTON_MIDLEFT
+#define BUTTON_RIGHT BUTTON_MIDRIGHT
+#define BUTTON_UP BUTTON_TOPMIDDLE
+#define BUTTON_DOWN BUTTON_BOTTOMMIDDLE
+
+/* Touchpad Screen Area Buttons */
+#define BUTTON_TOPLEFT 0x00000010
+#define BUTTON_TOPMIDDLE 0x00000020
+#define BUTTON_TOPRIGHT 0x00000040
+#define BUTTON_MIDLEFT 0x00000080
+#define BUTTON_CENTER 0x00000100
+#define BUTTON_MIDRIGHT 0x00000200
+#define BUTTON_BOTTOMLEFT 0x00000400
+#define BUTTON_BOTTOMMIDDLE 0x00000800
+#define BUTTON_BOTTOMRIGHT 0x00001000
+
+#define BUTTON_TOUCH 0x00002000
+
+#define BUTTON_MAIN 0x3FFF
+
+/* No remote */
+#define BUTTON_REMOTE 0
+
+/* Software power-off */
+#define POWEROFF_BUTTON BUTTON_POWER
+#define POWEROFF_COUNT 10
+
+#endif /* BUTTON_TARGET_H */
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
new file mode 100755
index 0000000000..d46cee6884
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
@@ -0,0 +1,201 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "jz4740.h"
+#include "lcd-target.h"
+
+#define PIN_CS_N (32*1+17) /* Chip select */
+#define PIN_RESET_N (32*1+18) /* Reset */
+
+#define my__gpio_as_lcd_16bit() \
+do { \
+ REG_GPIO_PXFUNS(2) = 0x001cffff; \
+ REG_GPIO_PXSELC(2) = 0x001cffff; \
+ REG_GPIO_PXPES(2) = 0x001cffff; \
+} while (0)
+
+
+#define SLEEP(x) for(i=0; i<x; i++) asm("nop"); asm("nop");
+#define DELAY SLEEP(700000);
+static void _display_pin_init(void)
+{
+ int i;
+ my__gpio_as_lcd_16bit();
+ __gpio_as_output(PIN_CS_N);
+ __gpio_as_output(PIN_RESET_N);
+ __gpio_clear_pin(PIN_CS_N);
+
+ __gpio_set_pin(PIN_RESET_N);
+ DELAY;
+ __gpio_clear_pin(PIN_RESET_N);
+ DELAY;
+ __gpio_set_pin(PIN_RESET_N);
+ DELAY;
+}
+
+#define WAIT_ON_SLCD while(REG_SLCD_STATE & SLCD_STATE_BUSY);
+#define SLCD_SET_DATA(x) WAIT_ON_SLCD; REG_SLCD_DATA = (x) | SLCD_DATA_RS_DATA;
+#define SLCD_SET_COMMAND(x) WAIT_ON_SLCD; REG_SLCD_DATA = (x) | SLCD_DATA_RS_COMMAND;
+#define SLCD_SEND_COMMAND(cmd,val) SLCD_SET_COMMAND(cmd); SLCD_SET_DATA(val);
+static void _display_on(void)
+{
+ int i;
+
+ SLCD_SEND_COMMAND(0x600, 1);
+ SLEEP(700000);
+ SLCD_SEND_COMMAND(0x600, 0);
+ SLEEP(700000);
+ SLCD_SEND_COMMAND(0x606, 0);
+
+ SLCD_SEND_COMMAND(1, 0x100);
+ SLCD_SEND_COMMAND(2, 0x100);
+ SLCD_SEND_COMMAND(3, 0x1028);
+ SLCD_SEND_COMMAND(8, 0x503);
+ SLCD_SEND_COMMAND(9, 1);
+ SLCD_SEND_COMMAND(0xB, 0x10);
+ SLCD_SEND_COMMAND(0xC, 0);
+ SLCD_SEND_COMMAND(0xF, 0);
+ SLCD_SEND_COMMAND(7, 1);
+ SLCD_SEND_COMMAND(0x10, 0x12);
+ SLCD_SEND_COMMAND(0x11, 0x202);
+ SLCD_SEND_COMMAND(0x12, 0x300);
+ SLCD_SEND_COMMAND(0x20, 0x21e);
+ SLCD_SEND_COMMAND(0x21, 0x202);
+ SLCD_SEND_COMMAND(0x22, 0x100);
+ SLCD_SEND_COMMAND(0x90, 0x8000);
+ SLCD_SEND_COMMAND(0x100, 0x16b0);
+ SLCD_SEND_COMMAND(0x101, 0x147);
+ SLCD_SEND_COMMAND(0x102, 0x1bd);
+ SLCD_SEND_COMMAND(0x103, 0x2f00);
+ SLCD_SEND_COMMAND(0x107, 0);
+ SLCD_SEND_COMMAND(0x110, 1);
+ SLCD_SEND_COMMAND(0x200, 0); /* set cursor at x_start */
+ SLCD_SEND_COMMAND(0x201, 0); /* set cursor at y_start */
+ SLCD_SEND_COMMAND(0x210, 0); /* y_start*/
+ SLCD_SEND_COMMAND(0x211, 239); /* y_end */
+ SLCD_SEND_COMMAND(0x212, 0); /* x_start */
+ SLCD_SEND_COMMAND(0x213, 399); /* x_end */
+ SLCD_SEND_COMMAND(0x280, 0);
+ SLCD_SEND_COMMAND(0x281, 6);
+ SLCD_SEND_COMMAND(0x282, 0);
+ SLCD_SEND_COMMAND(0x300, 0x101);
+ SLCD_SEND_COMMAND(0x301, 0xb27);
+ SLCD_SEND_COMMAND(0x302, 0x132a);
+ SLCD_SEND_COMMAND(0x303, 0x2a13);
+ SLCD_SEND_COMMAND(0x304, 0x270b);
+ SLCD_SEND_COMMAND(0x305, 0x101);
+ SLCD_SEND_COMMAND(0x306, 0x1205);
+ SLCD_SEND_COMMAND(0x307, 0x512);
+ SLCD_SEND_COMMAND(0x308, 5);
+ SLCD_SEND_COMMAND(0x309, 3);
+ SLCD_SEND_COMMAND(0x30a, 0xf04);
+ SLCD_SEND_COMMAND(0x30b, 0xf00);
+ SLCD_SEND_COMMAND(0x30c, 0xf);
+ SLCD_SEND_COMMAND(0x30d, 0x40f);
+ SLCD_SEND_COMMAND(0x30e, 0x300);
+ SLCD_SEND_COMMAND(0x30f, 0x500);
+ SLCD_SEND_COMMAND(0x400, 0x3100);
+ SLCD_SEND_COMMAND(0x401, 1);
+ SLCD_SEND_COMMAND(0x404, 0);
+ SLCD_SEND_COMMAND(0x500, 0);
+ SLCD_SEND_COMMAND(0x501, 0);
+ SLCD_SEND_COMMAND(0x502, 0);
+ SLCD_SEND_COMMAND(0x503, 0);
+ SLCD_SEND_COMMAND(0x504, 0);
+ SLCD_SEND_COMMAND(0x505, 0);
+ SLCD_SEND_COMMAND(0x606, 0);
+ SLCD_SEND_COMMAND(0x6f0, 0);
+ SLCD_SEND_COMMAND(0x7f0, 0x5420);
+ SLCD_SEND_COMMAND(0x7f3, 0x288a);
+ SLCD_SEND_COMMAND(0x7f4, 0x22);
+ SLCD_SEND_COMMAND(0x7f5, 1);
+ SLCD_SEND_COMMAND(0x7f0, 0);
+
+ SLCD_SEND_COMMAND(7, 0x173);
+ SLEEP(3500000);
+ SLCD_SEND_COMMAND(7, 0x171);
+ SLEEP(3500000);
+ SLCD_SEND_COMMAND(7, 0x173);
+ SLEEP(3500000);
+}
+
+static void _set_lcd_bus(void)
+{
+ REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK;
+ REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD;
+
+ REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT
+ | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING
+ | SLCD_CFG_TYPE_PARALLEL);
+
+ REG_SLCD_CTRL = SLCD_CTRL_DMA_EN;
+}
+
+static void _set_lcd_clock(void)
+{
+ unsigned int val;
+ int pll_div;
+
+ __cpm_stop_lcd();
+ pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
+ pll_div = pll_div ? 1 : 2 ;
+ val = ( __cpm_get_pllout()/pll_div ) / 336000000;
+ val--;
+ if ( val > 0x1ff )
+ {
+ //printf("CPM_LPCDR too large, set it to 0x1ff\n");
+ val = 0x1ff;
+ }
+ __cpm_set_pixdiv(val);
+ __cpm_start_lcd();
+}
+
+void lcd_init_controller(void)
+{
+ int i;
+ _display_pin_init();
+ _set_lcd_bus();
+ _set_lcd_clock();
+ SLEEP(1000);
+ _display_on();
+}
+
+void lcd_set_target(short x, short y, short width, short height)
+{
+ SLCD_SEND_COMMAND(0x210, y); /* y_start */
+ SLCD_SEND_COMMAND(0x211, y+height); /* y_end */
+ SLCD_SEND_COMMAND(0x212, x); /* x_start */
+ SLCD_SEND_COMMAND(0x213, x+width); /* x_end */
+ SLCD_SEND_COMMAND(0x200, x); /* set cursor at x_start */
+ SLCD_SEND_COMMAND(0x201, y); /* set cursor at y_start */
+ SLCD_SET_COMMAND(0x202); /* write data? */
+}
+
+void lcd_on(void)
+{
+ _display_on();
+}
+
+void lcd_off(void)
+{
+ return;
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h
new file mode 100755
index 0000000000..e643608d56
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h
@@ -0,0 +1,36 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef LCD_TARGET_H
+#define LCD_TARGET_H
+
+#include <stdbool.h>
+
+void lcd_enable(bool state);
+bool lcd_enabled(void);
+void lcd_init_device(void);
+
+
+void lcd_init_controller(void);
+void lcd_set_target(short x, short y, short width, short height);
+void lcd_on(void);
+void lcd_off(void);
+
+#endif /* LCD_TARGET_H */
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h
new file mode 100755
index 0000000000..30893aaaa3
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h
@@ -0,0 +1,26 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef USB_TARGET_H
+#define USB_TARGET_H
+
+void usb_init_device(void);
+
+#endif
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
new file mode 100755
index 0000000000..4963cac517
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
@@ -0,0 +1,71 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "jz4740.h"
+#include "mipsregs.h"
+
+void intr_handler(void)
+{
+ return;
+}
+
+void except_handler(void* stack_ptr, unsigned int cause, unsigned int epc)
+{
+ (void)stack_ptr;
+ (void)cause;
+ (void)epc;
+ REG8(USB_REG_POWER) &= ~USB_POWER_SOFTCONN;
+ while(1);
+}
+
+void system_reboot(void)
+{
+ while(1);
+}
+
+void cli(void)
+{
+ register unsigned int t;
+ t = read_c0_status();
+ t &= ~1;
+ write_c0_status(t);
+}
+
+unsigned int mips_get_sr(void)
+{
+ unsigned int t = read_c0_status();
+ return t;
+}
+
+void sti(void)
+{
+ register unsigned int t;
+ t = read_c0_status();
+ t |= 1;
+ t &= ~2;
+ write_c0_status(t);
+}
+
+void tick_start(unsigned int interval_in_ms)
+{
+ (void)interval_in_ms;
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
new file mode 100755
index 0000000000..2fff6423b9
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -0,0 +1,103 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "jz4740.h"
+#include "mipsregs.h"
+
+/* Core-level interrupt masking */
+
+/* This one returns the old status */
+#define HIGHEST_IRQ_LEVEL 0
+
+#define set_irq_level(status) \
+ set_interrupt_status((status), ST0_IE)
+#define set_fiq_status(status) \
+ set_interrupt_status((status), ST0_IE)
+
+static inline int set_interrupt_status(int status, int mask)
+{
+ unsigned int res, oldstatus;
+
+ res = oldstatus = read_c0_status();
+ res &= ~mask;
+ res |= (status & mask);
+ write_c0_status(res);
+
+ return oldstatus;
+}
+
+static inline void enable_interrupt(void)
+{
+ /* Set IE bit */
+ set_c0_status(ST0_IE);
+}
+
+static inline void disable_interrupt(void)
+{
+ /* Clear IE bit */
+ clear_c0_status(ST0_IE);
+}
+
+#define disable_irq() \
+ disable_interrupt()
+
+#define enable_irq() \
+ enable_interrupt()
+
+#define disable_fiq() \
+ disable_interrupt()
+
+#define enable_fiq() \
+ enable_interrupt()
+
+static inline int disable_interrupt_save(int mask)
+{
+ unsigned int oldstatus;
+
+ oldstatus = read_c0_status();
+ write_c0_status(oldstatus | mask);
+
+ return oldstatus;
+}
+
+#define disable_irq_save() \
+ disable_interrupt_save(ST0_IE)
+
+#define disable_fiq_save() \
+ disable_interrupt_save(ST0_IE)
+
+static inline void restore_interrupt(int status)
+{
+ write_c0_status(status);
+}
+
+#define restore_irq(cpsr) \
+ restore_interrupt(cpsr)
+
+#define restore_fiq(cpsr) \
+ restore_interrupt(cpsr)
+
+#define swap16(x) (((x) & 0xff) << 8 | ((x) >> 8) & 0xff)
+#define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff)
+
+void sti(void);
+void cli(void);
diff --git a/firmware/thread.c b/firmware/thread.c
index 4a808fb4b8..2eaa422841 100644
--- a/firmware/thread.c
+++ b/firmware/thread.c
@@ -985,6 +985,149 @@ static inline void core_sleep(void)
: : "z"(&SBYCR-GBR) : "r1");
}
+#elif CPU_MIPS == 32
+
+/*---------------------------------------------------------------------------
+ * Start the thread running and terminate it if it returns
+ *---------------------------------------------------------------------------
+ */
+void start_thread(void); /* Provide C access to ASM label */
+#if 0
+static void __attribute__((used)) __start_thread(void)
+{
+
+ /* $v0 = context */
+ asm volatile (
+ ".set noreorder \n"
+ "_start_thread: \n" /* Start here - no naked attribute */
+ "lw $8, (4)$2 \n" /* Fetch thread function pointer ($8 = $t0, $2 = $v0) */
+ "lw $29, (108)$2 \n" /* Set initial sp(=$29) */
+ "jalr $8 \n" /* Start the thread ($8 = $t0,)*/
+ "sw $0, (116)$2 \n" /* Clear start address ($2 = $v0) */
+ ".set reorder \n"
+ );
+ thread_exit();
+
+}
+#else
+void start_thread(void)
+{
+ return;
+}
+#endif
+
+/* Place context pointer in $v0 slot, function pointer in $v1 slot, and
+ * start_thread pointer in context_start */
+#define THREAD_STARTUP_INIT(core, thread, function) \
+ ({ (thread)->context.r[0] = (uint32_t)&(thread)->context, \
+ (thread)->context.r[1] = (uint32_t)(function), \
+ (thread)->context.start = (uint32_t)start_thread; })
+
+/*---------------------------------------------------------------------------
+ * Store non-volatile context.
+ *---------------------------------------------------------------------------
+ */
+static inline void store_context(void* addr)
+{
+#if 0
+ asm volatile (
+ ".set noreorder \n"
+ ".set noat \n"
+ "sw $1, (0)%0 \n"
+ "sw $2,(4)%0 \n" /* $v0 */
+ "sw $3,(8)%0 \n" /* $v1 */
+ "sw $4,(12)%0 \n" /* $a0 */
+ "sw $5,(16)%0 \n" /* $a1 */
+ "sw $6,(20)%0 \n" /* $a2 */
+ "sw $7,(24)%0 \n" /* $a3 */
+ "sw $8,(28)%0 \n" /* $t0 */
+ "sw $9,(32)%0 \n" /* $t1 */
+ "sw $10,(36)%0 \n" /* $t2 */
+ "sw $11,(40)%0 \n" /* $t3 */
+ "sw $12,(44)%0 \n" /* $t4 */
+ "sw $13,(48)%0 \n" /* $t5 */
+ "sw $14,(52)%0 \n" /* $t6 */
+ "sw $15,(56)%0 \n" /* $t7 */
+ "sw $24,(60)%0 \n" /* $t8 */
+ "sw $25,(64)%0 \n" /* $t9 */
+ "sw $16,(68)%0 \n" /* $s0 */
+ "sw $17,(72)%0 \n" /* $s1 */
+ "sw $18,(76)%0 \n" /* $s2 */
+ "sw $19,(80)%0 \n" /* $s3 */
+ "sw $20,(84)%0 \n" /* $s4 */
+ "sw $21,(88)%0 \n" /* $s5 */
+ "sw $22,(92)%0 \n" /* $s6 */
+ "sw $23,(96)%0 \n" /* $s7 */
+ "sw $28,(100)%0 \n" /* gp */
+ "sw $30,(104)%0 \n" /* fp */
+ "sw $29,(108)%0 \n" /* sp */
+ "sw $31,(112)%0 \n" /* ra */
+ ".set reorder \n"
+ : : "r" (addr)
+ );
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * Load non-volatile context.
+ *---------------------------------------------------------------------------
+ */
+static inline void load_context(const void* addr)
+{
+#if 0
+ asm volatile (
+ ".set noat \n"
+ ".set noreorder \n"
+ "lw $8, 116(%0) \n" /* Get start address ($8 = $t0) */
+ //"tst r0, r0 \n"
+ "j .running \n" /* NULL -> already running */
+ "jr $8 \n" /* $t0 = $8 = context */
+ ".running: \n"
+ "lw $1, (0)%0 \n"
+ "lw $2,(4)%0 \n" /* $v0 */
+ "lw $3,(8)%0 \n" /* $v1 */
+ "lw $4,(12)%0 \n" /* $a0 */
+ "lw $5,(16)%0 \n" /* $a1 */
+ "lw $6,(20)%0 \n" /* $a2 */
+ "lw $7,(24)%0 \n" /* $a3 */
+ "lw $8,(28)%0 \n" /* $t0 */
+ "lw $9,(32)%0 \n" /* $t1 */
+ "lw $10,(36)%0 \n" /* $t2 */
+ "lw $11,(40)%0 \n" /* $t3 */
+ "lw $12,(44)%0 \n" /* $t4 */
+ "lw $13,(48)%0 \n" /* $t5 */
+ "lw $14,(52)%0 \n" /* $t6 */
+ "lw $15,(56)%0 \n" /* $t7 */
+ "lw $24,(60)%0 \n" /* $t8 */
+ "lw $25,(64)%0 \n" /* $t9 */
+ "lw $16,(68)%0 \n" /* $s0 */
+ "lw $17,(72)%0 \n" /* $s1 */
+ "lw $18,(76)%0 \n" /* $s2 */
+ "lw $19,(80)%0 \n" /* $s3 */
+ "lw $20,(84)%0 \n" /* $s4 */
+ "lw $21,(88)%0 \n" /* $s5 */
+ "lw $22,(92)%0 \n" /* $s6 */
+ "lw $23,(96)%0 \n" /* $s7 */
+ "lw $28,(100)%0 \n" /* gp */
+ "lw $30,(104)%0 \n" /* fp */
+ "lw $29,(108)%0 \n" /* sp */
+ "lw $31,(112)%0 \n" /* ra */
+ ".set reorder \n"
+ : : "r" (addr) : "v0" /* only! */
+ );
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * Put core in a power-saving state.
+ *---------------------------------------------------------------------------
+ */
+static inline void core_sleep(void)
+{
+ asm volatile("nop\n");
+}
+
+
#endif /* CONFIG_CPU == */
/*
@@ -1909,6 +2052,8 @@ static inline void block_thread_on_l(struct thread_entry *thread,
*/
void switch_thread(void)
{
+#ifndef ONDA_VX747
+
const unsigned int core = CURRENT_CORE;
struct thread_entry *block = cores[core].block_task;
struct thread_entry *thread = cores[core].running;
@@ -2043,6 +2188,8 @@ void switch_thread(void)
#ifdef RB_PROFILE
profile_thread_started(thread - threads);
#endif
+
+#endif
}
/*---------------------------------------------------------------------------
diff --git a/tools/configure b/tools/configure
index 6410f9043f..4f0917068d 100755
--- a/tools/configure
+++ b/tools/configure
@@ -280,6 +280,15 @@ arm1136jfscc () {
gccchoice="4.0.3"
}
+mipselcc () {
+ prefixtools mipsel-linux-
+ GCCOPTS="$CCOPTS -mips32 -mno-abicalls"
+ GCCOPTIMIZE="-fomit-frame-pointer"
+ GCCOPTS="$GCCOPTS -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -msoft-float -G 0"
+ endian="little"
+ gccchoice="4.1.2"
+}
+
whichadvanced () {
##################################################################
# Prompt for specific developer options
@@ -688,6 +697,9 @@ cat <<EOF
90) Zen Vision:M 30GB 100) GoGear SA9200 110) M6SL
91) Zen Vision:M 60GB 101) GoGear HDD1630
92) Zen Vision
+
+ ==Onda==
+ 120) VX747
EOF
buildfor=`input`;
@@ -1747,6 +1759,28 @@ fi
t_manufacturer="s5l8700"
t_model="meizu-m6sl"
;;
+
+ 120|ondavx747)
+ target_id=44
+ modelname="ondavx747"
+ target="-DONDA_VX747"
+ memory=16 #FIXME
+ mipselcc
+ tool="cp"
+ bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
+ bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
+ output="rockbox.vx747"
+ appextra="recorder:gui"
+ plugins="no" #FIXME
+ swcodec="yes"
+ toolset=$genericbitmaptools
+ boottool="cp"
+ bootoutput="rockboot.vx747"
+ # architecture, manufacturer and model for the target-tree build
+ t_cpu="mips"
+ t_manufacturer="ingenic_jz47xx"
+ t_model="onda_vx747"
+ ;;
*)
echo "Please select a supported target platform!"
exit
diff --git a/tools/rockboxdev.sh b/tools/rockboxdev.sh
index f5d4da2c90..8eb1de08fc 100755
--- a/tools/rockboxdev.sh
+++ b/tools/rockboxdev.sh
@@ -168,6 +168,8 @@ case $1 in
;;
[Ii])
target="mipsel-elf"
+ gccver="4.1.2"
+ binutils="2.17"
;;
*)
echo "unsupported"