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-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-jz4760.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
index a8e40e4e31..ff87e5ad9e 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
@@ -503,6 +503,9 @@ static void pll0_init(unsigned int freq)
/* Init MSC clock; shoot for 48MHz base clock. */
REG_CPM_MSCCDR = MSCCDR_MCS | ((freq / 48000000) - 1);
+ /* Clock LCD clock as low as possible here */
+ __cpm_set_pixdiv(2048 -1);
+
/* init PLL */
REG_CPM_CPCCR = cfcr;
REG_CPM_CPPCR0 = plcr1;