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-rw-r--r--firmware/target/arm/rk27xx/system-rk27xx.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c
index ac423955d6..0e7fca4c06 100644
--- a/firmware/target/arm/rk27xx/system-rk27xx.c
+++ b/firmware/target/arm/rk27xx/system-rk27xx.c
@@ -117,6 +117,34 @@ void fiq_dummy(void)
void system_init(void)
{
+ /* SDRAM tweaks */
+ MCSDR_MODE = (2<<4)|3; /* CAS=2, burst=8 */
+ MCSDR_T_REF = (125*100) >> 3; /* 125/8 = 15.625 autorefresh interval */
+ MCSDR_T_RFC = (64*100) / 1000; /* autorefresh period */
+ MCSDR_T_RP = 1; /* precharge period */
+ MCSDR_T_RCD = 1; /* active to RD/WR delay */
+
+ /* turn off clock for unused modules */
+ SCU_CLKCFG |= (1<<31) | /* WDT pclk */
+ (1<<30) | /* RTC pclk */
+ (1<<26) | /* HS_ADC clock */
+ (1<<25) | /* HS_ADC HCLK */
+ (1<<21) | /* SPI clock */
+ (1<<19) | /* UART1 clock */
+ (1<<18) | /* UART0 clock */
+ (1<<15) | /* VIP clock */
+ (1<<14) | /* VIP HCLK */
+ (1<<13) | /* LCDC clock */
+ (1<<9) | /* NAND HCLK */
+ (1<<5) | /* USB host HCLK */
+ (1<<1) | /* DSP clock */
+ (1<<0); /* OTP clock (dunno what it is */
+
+ /* turn off DSP pll */
+ SCU_PLLCON2 |= (1<<22);
+
+ /* turn off codec pll */
+ SCU_PLLCON3 |= (1<<22);
return;
}
@@ -124,6 +152,7 @@ void system_init(void)
void system_reboot(void)
{
/* use Watchdog to reset */
+ SCU_CLKCFG &= ~(1<<31);
WDTLR = 1;
WDTCON = (1<<4) | (1<<3);