diff options
-rw-r--r-- | bootloader/ipod.c | 14 | ||||
-rw-r--r-- | firmware/export/pp5020.h | 113 | ||||
-rw-r--r-- | firmware/rolo.c | 8 | ||||
-rw-r--r-- | firmware/system.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/crt0-pp.S | 2 | ||||
-rw-r--r-- | firmware/target/arm/ipod/backlight-nano_video.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/ipod/lcd-color_nano.c | 10 | ||||
-rw-r--r-- | firmware/target/arm/ipod/lcd-gray.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/sandisk/sansa-e200/ata-e200.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/sandisk/sansa-e200/lcd-e200.c | 8 |
10 files changed, 100 insertions, 77 deletions
diff --git a/bootloader/ipod.c b/bootloader/ipod.c index 73b4fffc71..0600ea62c1 100644 --- a/bootloader/ipod.c +++ b/bootloader/ipod.c @@ -82,14 +82,14 @@ static void ser_opto_keypad_cfg(int val) { int start_time; - outl(inl(0x6000d004) & ~0x80, 0x6000d004); + GPIOB_ENABLE &=~ 0x80; outl(inl(0x7000c104) | 0xc000000, 0x7000c104); outl(val, 0x7000c120); outl(inl(0x7000c100) | 0x80000000, 0x7000c100); - outl(inl(0x6000d024) & ~0x10, 0x6000d024); - outl(inl(0x6000d014) | 0x10, 0x6000d014); + GPIOB_OUTPUT_VAL &=~ 0x10; + GPIOB_OUTPUT_EN |= 0x10; start_time = USEC_TIMER; do { @@ -100,9 +100,9 @@ static void ser_opto_keypad_cfg(int val) outl(inl(0x7000c100) & ~0x80000000, 0x7000c100); - outl(inl(0x6000d004) | 0x80, 0x6000d004); - outl(inl(0x6000d024) | 0x10, 0x6000d024); - outl(inl(0x6000d014) & ~0x10, 0x6000d014); + GPIOB_ENABLE |= 0x80; + GPIOB_OUTPUT_VAL |= 0x10; + GPIOB_OUTPUT_EN &=~0x10; outl(inl(0x7000c104) | 0xc000000, 0x7000c104); outl(inl(0x7000c100) | 0x60000000, 0x7000c100); @@ -253,7 +253,7 @@ void* main(void) outl(((0x100 | 1) << 3), 0x6000d824); /* set port L07 on */ - outl(((0x100 | 1) << 7), 0x6000d12c); + GPIOL_OUTPUT_VAL = ((0x100 | 1) << 7); #elif CONFIG_BACKLIGHT==BL_IPOD3G outl(inl(IPOD_LCD_BASE) | 0x2, IPOD_LCD_BASE); #endif diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 60d14491e0..ade1f138a0 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h @@ -20,11 +20,72 @@ #define __PP5020_H__ /* All info gleaned and/or copied from the iPodLinux project. */ + +/* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */ #define DRAM_START 0x10000000 +/* Processor ID */ +#define PROCESSOR_ID (*(volatile unsigned long *)(0x60000000)) + +#define PROC_ID_CPU 0x55 +#define PROC_ID_COP 0xaa + +/* Interrupts */ +#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024)) +#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124)) +#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028)) +#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128)) +#define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000)) +#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100)) + +#define TIMER1_IRQ 0 +#define TIMER2_IRQ 1 +#define I2S_IRQ 10 +#define IDE_IRQ 23 +#define GPIO_IRQ (32+0) +#define SER0_IRQ (32+4) +#define SER1_IRQ (32+5) +#define I2C_IRQ (32+8) + +#define TIMER1_MASK (1 << TIMER1_IRQ) +#define TIMER2_MASK (1 << TIMER2_IRQ) +#define I2S_MASK (1 << I2S_IRQ) +#define IDE_MASK (1 << IDE_IRQ) +#define GPIO_MASK (1 << (GPIO_IRQ-32)) +#define SER0_MASK (1 << (SER0_IRQ-32)) +#define SER1_MASK (1 << (SER1_IRQ-32)) +#define I2C_MASK (1 << (I2C_IRQ-32)) + +/* Timers */ +#define TIMER1_CFG (*(volatile unsigned long *)(0x60005000)) +#define TIMER1_VAL (*(volatile unsigned long *)(0x60005004)) +#define TIMER2_CFG (*(volatile unsigned long *)(0x60005008)) +#define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c)) +#define USEC_TIMER (*(volatile unsigned long *)(0x60005010)) + +/* Device Controller */ +#define DEV_RS (*(volatile unsigned long *)(0x60006004)) +#define DEV_EN (*(volatile unsigned long *)(0x6000600c)) + +#define DEV_SYSTEM 0x4 +#define DEV_I2C 0x1000 +#define DEV_USB 0x400000 + +/* Processors Control */ #define CPU_CTL (*(volatile unsigned long *)(0x60007000)) #define COP_CTL (*(volatile unsigned long *)(0x60007004)) +#define PROC_SLEEP 0x80000000 +#define PROC_WAKE 0x0 + +/* Cache Control */ +#define CACHE_CTL (*(volatile unsigned long *)(0x6000c000)) + +#define CACHE_DISABLE 0 +#define CACHE_ENABLE 1 +#define CACHE_INIT 4 + +/* GPIO Ports */ #define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000)) #define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004)) #define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008)) @@ -124,56 +185,24 @@ #define GPIOK_INT_CLR (*(volatile unsigned long *)(0x6000d178)) #define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c)) -#define DEV_RS (*(volatile unsigned long *)(0x60006004)) -#define DEV_EN (*(volatile unsigned long *)(0x6000600c)) - -#define DEV_SYSTEM 0x4 -#define DEV_I2C 0x1000 -#define DEV_USB 0x400000 - +/* Device initialization */ #define DEV_INIT (*(volatile unsigned long *)(0x70000020)) #define INIT_USB 0x80000000 -#define TIMER1_CFG (*(volatile unsigned long *)(0x60005000)) -#define TIMER1_VAL (*(volatile unsigned long *)(0x60005004)) -#define TIMER2_CFG (*(volatile unsigned long *)(0x60005008)) -#define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c)) -#define USEC_TIMER (*(volatile unsigned long *)(0x60005010)) - -#define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000)) -#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100)) -#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024)) -#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124)) -#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028)) -#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128)) - -#define TIMER1_IRQ 0 -#define TIMER2_IRQ 1 -#define I2S_IRQ 10 -#define IDE_IRQ 23 -#define GPIO_IRQ (32+0) -#define SER0_IRQ (32+4) -#define SER1_IRQ (32+5) -#define I2C_IRQ (32+8) - -#define TIMER1_MASK (1 << TIMER1_IRQ) -#define TIMER2_MASK (1 << TIMER2_IRQ) -#define I2S_MASK (1 << I2S_IRQ) -#define IDE_MASK (1 << IDE_IRQ) -#define GPIO_MASK (1 << (GPIO_IRQ-32)) -#define SER0_MASK (1 << (SER0_IRQ-32)) -#define SER1_MASK (1 << (SER1_IRQ-32)) -#define I2C_MASK (1 << (I2C_IRQ-32)) - +/* I2C */ #define I2C_BASE 0x7000c000 +/* I2S */ #define IISCONFIG (*(volatile unsigned long*)(0x70002800)) - #define IISFIFO_CFG (*(volatile unsigned long*)(0x7000280c)) #define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) #define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) +/* USB controller */ +#define USB_BASE 0xc5000000 + +/* Memory controller */ #define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000)) #define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004)) #define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008)) @@ -183,10 +212,4 @@ #define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018)) #define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c)) -/* The PortalPlayer USB controller uses base address 0xc5000000 */ -#define USB_BASE 0xc5000000 - -#define PROC_SLEEP 0x80000000 -#define PROC_WAKE 0x0 - #endif diff --git a/firmware/rolo.c b/firmware/rolo.c index 1489a8e695..4ac730b7ef 100644 --- a/firmware/rolo.c +++ b/firmware/rolo.c @@ -50,10 +50,10 @@ void rolo_restart_cop(void) { /* Invalidate cache */ outl(inl(0xf000f044) | 0x6, 0xf000f044); - while ((inl(0x6000c000) & 0x8000) != 0) {} + while ((CACHE_CTL & 0x8000) != 0) {} /* Disable cache */ - outl(0x0, 0x6000C000); + CACHE_CTL = CACHE_DISABLE; /* Wait while RoLo loads the image into SDRAM */ /* TODO: Accept checksum failure gracefully */ @@ -115,10 +115,10 @@ void rolo_restart(const unsigned char* source, unsigned char* dest, /* Flush cache */ outl(inl(0xf000f044) | 0x2, 0xf000f044); - while ((inl(0x6000c000) & 0x8000) != 0) {} + while ((CACHE_CTL & 0x8000) != 0) {} /* Disable cache */ - outl(0x0, 0x6000C000); + CACHE_CTL = CACHE_DISABLE; /* Reset the memory mapping registers to zero */ for (i=0;i<8;i++) diff --git a/firmware/system.c b/firmware/system.c index 463eec5053..a86d945093 100644 --- a/firmware/system.c +++ b/firmware/system.c @@ -648,7 +648,7 @@ void irq(void) unsigned int current_core(void) { - if(((*(volatile unsigned long *)(0x60000000)) & 0xff) == 0x55) + if((PROCESSOR_ID & 0xff) == PROC_ID_CPU) { return CPU; } @@ -670,7 +670,7 @@ static void ipod_init_cache(void) unsigned i; /* cache init mode? */ - outl(0x4, 0x6000C000); + CACHE_CTL = CACHE_INIT; /* PP5002 has 8KB cache */ for (i = 0xf0004000; i < 0xf0006000; i += 16) { @@ -681,7 +681,7 @@ static void ipod_init_cache(void) outl(0x3fc0, 0xf000f044); /* enable cache */ - outl(0x1, 0x6000C000); + CACHE_CTL = CACHE_ENABLE; for (i = 0x10000000; i < 0x10002000; i += 16) inb(i); diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S index 892275e411..e0d1034f74 100644 --- a/firmware/target/arm/crt0-pp.S +++ b/firmware/target/arm/crt0-pp.S @@ -205,7 +205,7 @@ cop_init: orr r1, r1, #0x6 str r1, [r0] - ldr r0, =0x6000c000 + ldr r0, =CACHE_CTRL 1: ldr r1, [r0] tst r1, #0x8000 diff --git a/firmware/target/arm/ipod/backlight-nano_video.c b/firmware/target/arm/ipod/backlight-nano_video.c index 5559709333..a5ef334d61 100644 --- a/firmware/target/arm/ipod/backlight-nano_video.c +++ b/firmware/target/arm/ipod/backlight-nano_video.c @@ -37,7 +37,7 @@ inline void __backlight_on(void) outl(((0x100 | 1) << 3), 0x6000d824); /* set port L07 on */ - outl(((0x100 | 1) << 7), 0x6000d12c); + GPIOL_OUTPUT_VAL = ((0x100 | 1) << 7); } inline void __backlight_off(void) @@ -46,5 +46,5 @@ inline void __backlight_off(void) outl(((0x100 | 0) << 3), 0x6000d824); /* set port L07 off */ - outl(((0x100 | 0) << 7), 0x6000d12c); + GPIOL_OUTPUT_VAL = ((0x100 | 0) << 7); } diff --git a/firmware/target/arm/ipod/lcd-color_nano.c b/firmware/target/arm/ipod/lcd-color_nano.c index 7da878ef14..6a29cbe680 100644 --- a/firmware/target/arm/ipod/lcd-color_nano.c +++ b/firmware/target/arm/ipod/lcd-color_nano.c @@ -115,9 +115,9 @@ void lcd_init_device(void) int gpio_a01, gpio_a04; /* A01 */ - gpio_a01 = (inl(0x6000D030) & 0x2) >> 1; + gpio_a01 = (GPIOA_INPUT_VAL & 0x2) >> 1; /* A04 */ - gpio_a04 = (inl(0x6000D030) & 0x10) >> 4; + gpio_a04 = (GPIOA_INPUT_VAL & 0x10) >> 4; if (((gpio_a01 << 1) | gpio_a04) == 0 || ((gpio_a01 << 1) | gpio_a04) == 2) { lcd_type = 0; @@ -126,12 +126,12 @@ void lcd_init_device(void) } } - outl(inl(0x6000d004) | 0x4, 0x6000d004); /* B02 enable */ - outl(inl(0x6000d004) | 0x8, 0x6000d004); /* B03 enable */ + GPIOB_ENABLE |= 0x4; /* B02 enable */ + GPIOB_ENABLE |= 0x8; /* B03 enable */ outl(inl(0x70000084) | 0x2000000, 0x70000084); /* D01 enable */ outl(inl(0x70000080) | 0x2000000, 0x70000080); /* D01 =1 */ - outl(inl(0x6000600c) | 0x20000, 0x6000600c); /* PWM enable */ + DEV_EN |= 0x20000; /* PWM enable */ #elif CONFIG_LCD == LCD_IPODNANO /* iPodLinux doesn't appear have any LCD init code for the Nano */ diff --git a/firmware/target/arm/ipod/lcd-gray.c b/firmware/target/arm/ipod/lcd-gray.c index 620c4355c3..1493751c3b 100644 --- a/firmware/target/arm/ipod/lcd-gray.c +++ b/firmware/target/arm/ipod/lcd-gray.c @@ -133,12 +133,12 @@ void lcd_init_device(void) lcd_cmd_and_data(R_ENTRY_MODE, 0x0000); #ifdef IPOD_4G - outl(inl(0x6000d004) | 0x4, 0x6000d004); /* B02 enable */ - outl(inl(0x6000d004) | 0x8, 0x6000d004); /* B03 enable */ + GPIOB_ENABLE |= 0x4; /* B02 enable */ + GPIOB_ENABLE |= 0x8; /* B03 enable */ outl(inl(0x70000084) | 0x2000000, 0x70000084); /* D01 enable */ outl(inl(0x70000080) | 0x2000000, 0x70000080); /* D01 =1 */ - outl(inl(0x6000600c) | 0x20000, 0x6000600c); /* PWM enable */ + DEV_EN |= 0x20000; /* PWM enable */ #endif } diff --git a/firmware/target/arm/sandisk/sansa-e200/ata-e200.c b/firmware/target/arm/sandisk/sansa-e200/ata-e200.c index 56f351c001..cf05397a78 100644 --- a/firmware/target/arm/sandisk/sansa-e200/ata-e200.c +++ b/firmware/target/arm/sandisk/sansa-e200/ata-e200.c @@ -364,9 +364,9 @@ void sd_init_device(void) GPIOD_ENABLE |= (0x1f); GPIOD_OUTPUT_EN |= (0x1f); GPIOD_OUTPUT_VAL |= (0x1f); - outl(inl(0x6000600c) | (1 << 14), 0x6000600c); - outl(inl(0x60006004) | (1 << 14), 0x60006004); - outl(inl(0x60006004) & ~(1 << 14), 0x60006004); /* Reset Controller? */ + DEV_EN |= (1 << 14); /* Enable controller */ + DEV_RS |= (1 << 14); /* Reset controller */ + DEV_RS &=~(1 << 14); /* Clear Reset */ outl(0, 0x6000b000); outl(0, 0x6000a000); /* Init DMA controller? */ diff --git a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c index 25bb6f04aa..e34ebd7c5a 100644 --- a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c +++ b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c @@ -110,7 +110,7 @@ static inline void cache_flush(void) { #ifndef BOOTLOADER outl(inl(0xf000f044) | 0x2, 0xf000f044); - while ((inl(0x6000c000) & 0x8000) != 0) + while ((CACHE_CTL & 0x8000) != 0) { } #endif @@ -141,12 +141,12 @@ inline void lcd_init_device(void) outl(((inl(0x70000010) & (0x03ffffff)) | (0x15 << 26)), 0x70000010); outl(((inl(0x70000014) & (0x0fffffff)) | (0x5 << 28)), 0x70000014); outl((inl(0x70000020) & ~(0x3 << 10)), 0x70000020); - outl((inl(0x6000600c) | (1 << 26)), 0x6000600c); /* Enable controller */ + DEV_EN |= (1 << 26); /* Enable controller */ outl(0x6, 0x600060d0); - outl((inl(0x60006004) | (1 << 26)), 0x60006004); /* Reset controller? */ + DEV_RS |= (1 << 26); /* Reset controller */ outl((inl(0x70000020) & ~(1 << 14)), 0x70000020); lcd_bus_idle(); - outl((inl(0x60006004) & ~(1 << 26)), 0x60006004); /* Clear reset? */ + DEV_RS &=~(1 << 26); /* Clear reset */ udelay(1000); LCD_REG_0 = (LCD_REG_0 & (0x00ffffff)) | (0x22 << 24); |