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-rw-r--r--firmware/target/arm/imx233/system-target.h41
1 files changed, 41 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h
index 163eacb41f..0f7bde4896 100644
--- a/firmware/target/arm/imx233/system-target.h
+++ b/firmware/target/arm/imx233/system-target.h
@@ -31,10 +31,35 @@
#define HW_DIGCTL_MICROSECONDS (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
#define HW_POWER_BASE 0x80044000
+
+#define HW_POWER_CTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x0))
+
+#define HW_POWER_5VCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x10))
+
+#define HW_POWER_MINPWR (*(volatile uint32_t *)(HW_POWER_BASE + 0x20))
+
+#define HW_POWER_CHARGE (*(volatile uint32_t *)(HW_POWER_BASE + 0x30))
+
+#define HW_POWER_VDDDCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x40))
+#define HW_POWER_VDDDCTRL__TRG_BP 0
+#define HW_POWER_VDDDCTRL__TRG_BM 0x1f
+#define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */
+#define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */
+
+#define HW_POWER_VDDACTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x50))
+
+#define HW_POWER_VDDIOCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x60))
+
+#define HW_POWER_VDDMEMCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x70))
+
+#define HW_POWER_MISC (*(volatile uint32_t *)(HW_POWER_BASE + 0x90))
+
#define HW_POWER_STS (*(volatile uint32_t *)(HW_POWER_BASE + 0xc0))
#define HW_POWER_STS__PSWITCH_BP 20
#define HW_POWER_STS__PSWITCH_BM (3 << 20)
+#define HW_POWER_BATTMONITOR (*(volatile uint32_t *)(HW_POWER_BASE + 0xe0))
+
#define HW_POWER_RESET (*(volatile uint32_t *)(HW_POWER_BASE + 0x100))
#define HW_POWER_RESET__UNLOCK 0x3E770000
#define HW_POWER_RESET__PWD 0x1
@@ -67,6 +92,22 @@
#define INT_SRC_LCDIF_ERROR 46
#define INT_SRC_NR_SOURCES 66
+/**
+ * Absolute maximum CPU speed: 454.74 MHz
+ * Intermediate CPU speeds: 392.73 MHz, 360MHz, 261.82 MHz, 64 MHz
+ * Absolute minimum CPU speed: 24 MHz */
+#define IMX233_CPUFREQ_454_MHz 454740000
+#define IMX233_CPUFREQ_392_MHz 392730000
+#define IMX233_CPUFREQ_360_MHz 360000000
+#define IMX233_CPUFREQ_261_MHz 261820000
+#define IMX233_CPUFREQ_64_MHz 64000000
+#define IMX233_CPUFREQ_24_MHz 24000000
+
+#define CPUFREQ_DEFAULT IMX233_CPUFREQ_454_MHz
+#define CPUFREQ_NORMAL IMX233_CPUFREQ_454_MHz
+#define CPUFREQ_MAX IMX233_CPUFREQ_454_MHz
+#define CPUFREQ_SLEEP IMX233_CPUFREQ_454_MHz
+
void imx233_enable_interrupt(int src, bool enable);
void imx233_softirq(int src, bool enable);
void udelay(unsigned us);