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Diffstat (limited to 'firmware/target/arm/system-target.h')
-rw-r--r--firmware/target/arm/system-target.h142
1 files changed, 23 insertions, 119 deletions
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index ceb8be2079..2b72e9293e 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -8,6 +8,7 @@
* $Id$
*
* Copyright (C) 2002 by Alan Korr
+ * Copyright (C) 2007 by Michael Sevakis
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
@@ -19,137 +20,40 @@
#ifndef SYSTEM_TARGET_H
#define SYSTEM_TARGET_H
-#define nop \
- asm volatile ("nop")
+#include "system-arm.h"
-/* This gets too complicated otherwise with all the ARM variation and would
- have conflicts with another system-target.h elsewhere so include a
- subheader from here. */
+#define inl(a) (*(volatile unsigned long *) (a))
+#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
+#define inb(a) (*(volatile unsigned char *) (a))
+#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
+#define inw(a) (*(volatile unsigned short *) (a))
+#define outw(a,b) (*(volatile unsigned short *) (b) = (a))
+extern unsigned int ipod_hw_rev;
-#ifdef CPU_PP
-#include "system-pp.h"
-#elif CONFIG_CPU == S3C2440
-#include "system-meg-fx.h"
-#endif
-
-/* TODO: Implement set_irq_level and check CPU frequencies */
-
-#if CONFIG_CPU == S3C2440
-
-#define CPUFREQ_DEFAULT 98784000
-#define CPUFREQ_NORMAL 98784000
-#define CPUFREQ_MAX 296352000
-
-#elif CONFIG_CPU == PNX0101
-
-#define CPUFREQ_DEFAULT 12000000
-#define CPUFREQ_NORMAL 48000000
-#define CPUFREQ_MAX 60000000
-
-#else
-
-#define CPUFREQ_DEFAULT_MULT 8
-#define CPUFREQ_DEFAULT 24000000
-#define CPUFREQ_NORMAL_MULT 10
-#define CPUFREQ_NORMAL 30000000
-#define CPUFREQ_MAX_MULT 25
-#define CPUFREQ_MAX 75000000
-
-#endif
-
-static inline uint16_t swap16(uint16_t value)
- /*
- result[15..8] = value[ 7..0];
- result[ 7..0] = value[15..8];
- */
+static inline void udelay(unsigned usecs)
{
- return (value >> 8) | (value << 8);
+ unsigned stop = USEC_TIMER + usecs;
+ while (TIME_BEFORE(USEC_TIMER, stop));
}
-static inline uint32_t swap32(uint32_t value)
- /*
- result[31..24] = value[ 7.. 0];
- result[23..16] = value[15.. 8];
- result[15.. 8] = value[23..16];
- result[ 7.. 0] = value[31..24];
- */
-{
- uint32_t tmp;
+unsigned int current_core(void);
- asm volatile (
- "eor %1, %0, %0, ror #16 \n\t"
- "bic %1, %1, #0xff0000 \n\t"
- "mov %0, %0, ror #8 \n\t"
- "eor %0, %0, %1, lsr #8 \n\t"
- : "+r" (value), "=r" (tmp)
- );
- return value;
-}
+#if CONFIG_CPU != PP5002
-static inline uint32_t swap_odd_even32(uint32_t value)
+#define HAVE_INVALIDATE_ICACHE
+static inline void invalidate_icache(void)
{
- /*
- result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
- result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
- */
- uint32_t tmp;
-
- asm volatile ( /* ABCD */
- "bic %1, %0, #0x00ff00 \n\t" /* AB.D */
- "bic %0, %0, #0xff0000 \n\t" /* A.CD */
- "mov %0, %0, lsr #8 \n\t" /* .A.C */
- "orr %0, %0, %1, lsl #8 \n\t" /* B.D.|.A.C */
- : "+r" (value), "=r" (tmp) /* BADC */
- );
- return value;
+ outl(inl(0xf000f044) | 0x6, 0xf000f044);
+ while ((CACHE_CTL & 0x8000) != 0);
}
-#define HIGHEST_IRQ_LEVEL (1)
-
-static inline int set_irq_level(int level)
-{
- unsigned long cpsr;
- /* Read the old level and set the new one */
- asm volatile ("mrs %0,cpsr" : "=r" (cpsr));
- asm volatile ("msr cpsr_c,%0"
- : : "r" ((cpsr & ~0x80) | (level << 7)));
- return (cpsr >> 7) & 1;
-}
-
-static inline void set_fiq_handler(void(*fiq_handler)(void))
+#define HAVE_FLUSH_ICACHE
+static inline void flush_icache(void)
{
- /* Install the FIQ handler */
- *((unsigned int*)(15*4)) = (unsigned int)fiq_handler;
+ outl(inl(0xf000f044) | 0x2, 0xf000f044);
+ while ((CACHE_CTL & 0x8000) != 0);
}
-static inline void enable_fiq(void)
-{
- /* Clear FIQ disable bit */
- asm volatile (
- "mrs r0, cpsr \n"\
- "bic r0, r0, #0x40 \n"\
- "msr cpsr_c, r0 "
- : : : "r0"
- );
-}
-
-static inline void disable_fiq(void)
-{
- /* Set FIQ disable bit */
- asm volatile (
- "mrs r0, cpsr \n"\
- "orr r0, r0, #0x40 \n"\
- "msr cpsr_c, r0 "
- : : : "r0"
- );
-}
-
-#if CONFIG_CPU == PNX0101
-typedef void (*interrupt_handler_t)(void);
-
-void irq_set_int_handler(int n, interrupt_handler_t handler);
-void irq_enable_int(int n);
-void irq_disable_int(int n);
-#endif
+#endif /* CONFIG_CPU */
#endif /* SYSTEM_TARGET_H */