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+<?xml version="1.0"?>
+<soc version="2">
+ <name>vsoc</name>
+ <title>Virtual SOC</title>
+ <desc>Virtual SoC is a nice and powerful chip.</desc>
+ <author>Amaury Pouly</author>
+ <isa>ARM</isa>
+ <version>0.5</version>
+ <node>
+ <name>int</name>
+ <title>Interrupt Collector</title>
+ <desc>The interrupt collector controls the routing of interrupt to the processor</desc>
+ <instance>
+ <name>ICOLL</name>
+ <title>Interrupt collector</title>
+ <address>0x80000000</address>
+ </instance>
+ <node>
+ <name>status</name>
+ <access>read-only</access>
+ <title>Interrupt status register</title>
+ <instance>
+ <name>STATUS</name>
+ <address>0x4</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>VDDIO_BO</name>
+ <desc>VDDIO brownout interrupt status</desc>
+ <position>0</position>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>enable</name>
+ <title>Interrupt enable register</title>
+ <instance>
+ <name>ENABLE</name>
+ <address>0x8</address>
+ </instance>
+ <register>
+ <width>16</width>
+ <field>
+ <name>VDDIO_BO</name>
+ <desc>VDDIO brownout interrupt enable</desc>
+ <position>0</position>
+ <width>2</width>
+ <enum>
+ <name>DISABLED</name>
+ <desc>Interrupt is disabled</desc>
+ <value>0</value>
+ </enum>
+ <enum>
+ <name>ENABLED</name>
+ <desc>Interrupt is enabled</desc>
+ <value>1</value>
+ </enum>
+ <enum>
+ <name>NMI</name>
+ <desc>Interrupt is non-maskable</desc>
+ <value>2</value>
+ </enum>
+ </field>
+ </register>
+ <variant>
+ <type>set</type>
+ <offset>4</offset>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <offset>8</offset>
+ </variant>
+ </node>
+ </node>
+ <node>
+ <name>gpio</name>
+ <title>GPIO controller</title>
+ <desc>A GPIO controller manages several ports</desc>
+ <instance>
+ <name>CPU_GPIO</name>
+ <title>CPU GPIO controller 1 through 3</title>
+ <range>
+ <first>1</first>
+ <count>3</count>
+ <formula variable="n">0x80001000+(n-1)*0x1000</formula>
+ </range>
+ </instance>
+ <instance>
+ <name>COP_GPIO</name>
+ <title>Companion processor GPIO controller</title>
+ <desc>Although the companion processor GPIO controller is accessible from the CPU, it incurs an extra penalty on the bus</desc>
+ <address>0x90000000</address>
+ </instance>
+ <node>
+ <name>port</name>
+ <title>GPIO port</title>
+ <instance>
+ <name>PORT</name>
+ <range>
+ <first>0</first>
+ <count>4</count>
+ <base>0</base>
+ <stride>0x100</stride>
+ </range>
+ </instance>
+ <node>
+ <name>input</name>
+ <title>Input register</title>
+ <instance>
+ <name>IN</name>
+ <address>0</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>VALUE</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ </node>
+ <node>
+ <name>output_enable</name>
+ <title>Output enable register</title>
+ <instance>
+ <name>OE</name>
+ <address>0x10</address>
+ </instance>
+ <register>
+ <width>8</width>
+ <field>
+ <name>ENABLE</name>
+ <position>0</position>
+ <width>8</width>
+ </field>
+ </register>
+ <variant>
+ <type>set</type>
+ <address>4</address>
+ </variant>
+ <variant>
+ <type>clr</type>
+ <address>8</address>
+ </variant>
+ <variant>
+ <type>mask</type>
+ <address>12</address>
+ </variant>
+ </node>
+ </node>
+ </node>
+</soc> \ No newline at end of file