path: root/firmware/target/arm/imx233/clkctrl-imx233.h
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2016-05-28imx233: generate register headers using headergen_v2 and update code for itAmaury Pouly1-2/+2
NOTE: this commit does not introduce any change, ideally even the binary should be almost the same. I checked the disassembly by hand and there are only a few differences here and there, mostly the compiler decides to compile very close expressions slightly differently. I tried to run the new code on several targets to make sure and saw no difference. The major syntax changes of the new headers are as follows: - BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once: BF_WR(reg, field1(value1), field2(value2), ...) - BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW - there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply BF_WR with field_V(name) - the old BF_SETV macro has no trivial equivalent and is replaced with its its equivalent for BF_WR(reg_SET, ...) I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the redundant "regs". Final note: the registers were generated using the following command: ./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2014-03-08imx233: add function to change cpu/hbus frequency safelyAmaury Pouly1-0/+2
Change-Id: I88e9ad54ba65846ae4d94ae03009b3656f2489f2
2013-06-17imx233: fix clkctrl for stmp3600 and stmp3700Amaury Pouly1-2/+6
Change-Id: I7596e41c0d0b7fdcc18f7d328a0927c2c78dc4cb
2013-06-17imx233: normalise clkctrlAmaury Pouly1-55/+21
The clkctrl functions were becoming a mess. Normalise the names, get rid of the xtal derived as special case and use the same interface. Change-Id: Ib954a8d30a6bd691914b5e0d97774ec9fc560c50
2013-06-16imx233: rewrite clkctrl using new register headersAmaury Pouly1-80/+3
Change-Id: I6c79e99ed4ab20e00c3110d870e144a6c8596769
2013-01-10imx233: implement emi frequency scaling (disabled by default)Amaury Pouly1-0/+1
CPU frequency scaling is basically useless without scaling the memory frequency. On the i.MX233, the EMI (external memory interface) and DRAM blocks are responsable for the DDR settings. This commits implements emi frequency scaling. Only some settings are implemented and the timings values only apply to mDDR (extracted from Sigmatel linux port) and have been checked to work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled by default but I expected some battery life savings by boosting higher to 454MHz and unboosting lower to 64MHz. Note that changing the emi frequency is particularly tricky and to avoid writing it entirely in assembly we rely on the compiler to not use the stack except in the prolog and epilog (because it's in dram which is disabled when doing the change) and to put constant pools in iram which should always be true if the compiler isn't completely dumb and since the code itself is put in iram. If this proves to be insufficient, one can always switch the stack to the irq stack since interrupts are disabled during the change. Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
2012-12-26imx233: fix potential hbus dividor settings + docAmaury Pouly1-1/+4
HBUS uses the same field for integer and fractional dividers, the choice is made by a bit. Make sure both are changed together, otherwise this could result in the wrong divider to be used and in HBUS freq to be too low or too high (very bad). Change-Id: I253d8eeee26c5038868b729c4f791511295a39f0
2012-08-30imx233: fix header, add emi functionAmaury Pouly1-1/+3
Change-Id: I1030e94f0dad4b66646cafa20b61df8a5c7f9278
2012-05-21imx233: enable PLL on startupAmaury Pouly1-1/+2
Implement PLL enabling/disable and unconditionally power the PLL on startup. This is needed at least on the Zen X-Fi2. Change-Id: Ib9ddfdeaf973cedded4b3586dd16aa95a61e78ba
2012-05-19imx233: fix clkctrl namingAmaury Pouly1-20/+21
Move to a more consistent naming convention like the other devices Change-Id: I4ddbbee27ee9f5ae775c5776592ec7ce02b30948
2012-01-21imx233: fix clkctrl code (some registers don't have a SET/CLR variant)Amaury Pouly1-0/+5
Change-Id: I3ce6a77cdc5ea89e1e43bc00c9ec43664e765fdc
2011-12-26imx233: implement core_sleepAmaury Pouly1-0/+11
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-12-03imx233: add control for more clocks, add debug clock debug screenAmaury Pouly1-9/+72
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-10-18imx233/fuze+: move to a more generic xtal derived clock enabling function, ↵Amaury Pouly1-1/+11
fix timrot accordingly git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-09-14imx233/fuze+: implement usb enableAmaury Pouly1-2/+4
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-07-03imx233/fuze+: replace software i2c by hardware i2c, make some code more ↵Amaury Pouly1-0/+5
correct, reduce code size of lcd init sequences git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-06-30imx233/fuze+: ssp, dma, mmc now work properly, partially implement cpu ↵Amaury Pouly1-3/+24
frequency changing, implement panic waiting git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-06-17fuze+: add more clocking code, add dma code, add ssp code, add stub usb ↵Amaury Pouly1-0/+16
code, update storage to SD + MMC, beginning of the driver git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-05-01Sansa Fuze+: initial commit (bootloader only, LCD basically working)Amaury Pouly1-0/+52
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657