path: root/firmware/target/arm/imx233/icoll-imx233.c
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2016-12-12imx233: add more icoll statisticsAmaury Pouly1-0/+15
Those new statistics give the maximum time an IRQ took and also the total time spent in IRQ, for each IRQ. Hopefully those do not take took much time or space to collect. If this is the case, it can be enabled in debug builds only the future. Change-Id: I05af172897c5cb7ffcc9322452f974d8f968e29d
2016-12-12imx233: fix IRQ handler w.r.t unwinderAmaury Pouly1-5/+12
The IRQ handler saves registers on the IRQ stack, saves the old PC to imx233 HW_DIGCTL_SCRATCH0 register and switcht to SVC for the actual handling. The old code had a problem in that if the unwinder is called during the IRQ (for example by the watchdog), then __get_sp() will use SPSR_svc to discover the previous mode, switch to it and recover SP. But SPSR_svc is invalid, it should be SPSR_irq but we switch from IRQ to SVC mode. The new code copies SPSR_irq to SPSR_svc in IRQ to fix this problem. It also saves/restore SCRATCH0 in case I one day renable nested interrupts or use SCRATCH0 for other purposes. I also changed the old watchdog code to call UIE directly instead of trying to make the code crash with a SWI. Change-Id: Id87462d410764b019bd2aa9adc71cb917ade32e3
2016-05-28imx233: generate register headers using headergen_v2 and update code for itAmaury Pouly1-14/+28
NOTE: this commit does not introduce any change, ideally even the binary should be almost the same. I checked the disassembly by hand and there are only a few differences here and there, mostly the compiler decides to compile very close expressions slightly differently. I tried to run the new code on several targets to make sure and saw no difference. The major syntax changes of the new headers are as follows: - BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once: BF_WR(reg, field1(value1), field2(value2), ...) - BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW - there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply BF_WR with field_V(name) - the old BF_SETV macro has no trivial equivalent and is replaced with its its equivalent for BF_WR(reg_SET, ...) I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the redundant "regs". Final note: the registers were generated using the following command: ./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2014-02-16imx233: rework interrupt nesting, disabled for nowAmaury Pouly1-20/+30
Rework the irq code, to put more code in the C part. When interrupt nesting is enable, Rockbox gets pretty unstable so disable it for now. Change-Id: Iee18b539c80ea408273f6082975faaa87d3ee1b6
2014-02-10imx233: add hardware and software watchdogAmaury Pouly1-0/+3
The hardware watchdog automatically shutdown the device after 10s of inactivity, being defined as 10s without the tick IRQ fired (aka braindead device). The software IRQ mechanism is more interesting: it uses a very high priority timer setup as one-shot to trigger after 5s of inactivity (but IRQ still enabled). When detected, it patches the running code to insert a SWI instruction so that on interrupt return it will trigger a SWI and produce a meaningfull backtrace to debug the deadlock. This should allow to debug freezes in IRQ context. Change-Id: Ic55dad01201676bfb6dd79e78e535c6707cb88e6
2014-02-10imx233: add support for nested IRQAmaury Pouly1-7/+32
Rewrite IRQ handling to allow nested IRQs: on each IRQ entry, we save the parameters on the (IRQ) stack and then switch to SVC mode (with its own stack) and renable interrupts. Make sure interrupt is properly acknowledged by using the read side-effect (RSE) mode and handle priority levels as well. Change-Id: I3fd68289b430c56bdd256868939238ff268e42b4
2014-02-10imx233: cleanup icoll and add software irq sourcesAmaury Pouly1-6/+13
Change-Id: I4cf2b0b74cf391021afaec08329ec7cf5dbd578d
2014-02-10imx233: enhance icoll with priority and soft IRQAmaury Pouly1-0/+29
Change-Id: If9568ab6e11bf933b2cc607e5a86866a975886bc
2014-02-10imx233: clean timrot a bitAmaury Pouly1-1/+2
Change-Id: Ic803a6b5c93978cd3246e553579ac8a1ba35e191
2013-06-17imx233: fix icoll for stmp3600 and stmp3700Amaury Pouly1-14/+38
Change-Id: I97b86d67b53615eca0d870058ff5c095c3063151
2013-06-16imx233: rewrite icoll to use new register headersAmaury Pouly1-10/+8
Change-Id: I0bf30849d18a8493627025b383ce75ce524777ab
2012-12-29imx233: increase irq storm thresholdAmaury Pouly1-1/+1
On heavy storage operations (like database update), the ssp dma irq can be fired around ~10000/sec. Change-Id: I0e33df6258e051abd4fe110a0f408a19671cd8ad
2012-12-29Fix copyright headersAmaury Pouly1-1/+1
Change-Id: Ie65920b1192e9b737fcc2554d280fbcedfa39800
2012-12-26imx233: use tick insteaf of msec to collect statisticsAmaury Pouly1-8/+8
The current code uses the msec irq to collect statistics and detect irq storms (debug). But this irq is triggered 1000 times per sec and we don't need that accuracy. This commit removes the msec irq and use the tick timer instead which is triggered only 100 times per second. Change-Id: If14b9503c89a3af370ef322678f10e35fafb4b8a
2012-05-19imx233: move icoll stuff to its own fileAmaury Pouly1-0/+177
The icoll code now has an IRQ storm detection mechanism which will prevent the device from hard freezing in case it happen. Change-Id: I9861238dce61d29af1e48f9c534ec63a7f23465c