path: root/firmware/target/arm/imx233/system-target.h
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2017-10-28imx233: Implement mutex for cpu_boost_lock/unlockWilliam Wilgus1-0/+17
Playing AAC-HE files resulted in a race condition between audio/codec/buffering for set_cpu_frequency Change-Id: I35e1c1fd18db623e2990c305acdca03f57184d0d
2016-12-12imx233: refactor power off and rebootAmaury Pouly1-1/+1
There is no reason to use different code paths Change-Id: I4894c7963c802b56b5d3576909e1008a7c401935
2016-05-28imx233: fix frequency reportingAmaury Pouly1-5/+5
The code reported the frequency in kHz instead of Hz, thus breaking a debug screen. Change-Id: Id46de970cfb55bcdc09b63f59b244ee3ad6264b8
2016-05-28imx233: generate register headers using headergen_v2 and update code for itAmaury Pouly1-3/+0
NOTE: this commit does not introduce any change, ideally even the binary should be almost the same. I checked the disassembly by hand and there are only a few differences here and there, mostly the compiler decides to compile very close expressions slightly differently. I tried to run the new code on several targets to make sure and saw no difference. The major syntax changes of the new headers are as follows: - BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once: BF_WR(reg, field1(value1), field2(value2), ...) - BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW - there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply BF_WR with field_V(name) - the old BF_SETV macro has no trivial equivalent and is replaced with its its equivalent for BF_WR(reg_SET, ...) I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the redundant "regs". Final note: the registers were generated using the following command: ./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2014-03-08imx233: prepare frequency scaling for stmp3700Amaury Pouly1-4/+7
Add entry for stmp3700 maximum frequency which is 320MHz. Change-Id: I6db4aad4efa0a7c1347a1ceb262a0295f63057ae
2014-02-10imx233: stop the watchdog before loading main firmwareAmaury Pouly1-0/+1
Change-Id: I0a13444d6788a09b0fc04ed1a5115cb2e5fe6f57
2014-02-10imx233: add hardware and software watchdogAmaury Pouly1-0/+3
The hardware watchdog automatically shutdown the device after 10s of inactivity, being defined as 10s without the tick IRQ fired (aka braindead device). The software IRQ mechanism is more interesting: it uses a very high priority timer setup as one-shot to trigger after 5s of inactivity (but IRQ still enabled). When detected, it patches the running code to insert a SWI instruction so that on interrupt return it will trigger a SWI and produce a meaningfull backtrace to debug the deadlock. This should allow to debug freezes in IRQ context. Change-Id: Ic55dad01201676bfb6dd79e78e535c6707cb88e6
2013-09-25imx233: always boost in bootloaderAmaury Pouly1-0/+2
Many imx233 targets boot in a very low performance mode, typically cpu and dram at 24MHz. This results in very slow boots and very unstable USB bootloader mode. Since cpu frequency scaling is disabled in bootloader in rockbox, always make the frequency scaling code available and boost at boot time. Change-Id: Ie96623c00f7c4cd9a377b84dcb14b772558cfa4d
2013-06-16imx233: rewrite digctl using new register headersAmaury Pouly1-27/+2
Change-Id: I910a09e07b9f5a82bb6cb150739fcebc942cb7c1
2013-01-10imx233: implement emi frequency scaling (disabled by default)Amaury Pouly1-9/+21
CPU frequency scaling is basically useless without scaling the memory frequency. On the i.MX233, the EMI (external memory interface) and DRAM blocks are responsable for the DDR settings. This commits implements emi frequency scaling. Only some settings are implemented and the timings values only apply to mDDR (extracted from Sigmatel linux port) and have been checked to work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled by default but I expected some battery life savings by boosting higher to 454MHz and unboosting lower to 64MHz. Note that changing the emi frequency is particularly tricky and to avoid writing it entirely in assembly we rely on the compiler to not use the stack except in the prolog and epilog (because it's in dram which is disabled when doing the change) and to put constant pools in iram which should always be true if the compiler isn't completely dumb and since the code itself is put in iram. If this proves to be insufficient, one can always switch the stack to the irq stack since interrupts are disabled during the change. Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
2012-08-30imx233: implement basic frequency scaling and enable auto-slowAmaury Pouly1-3/+3
This does not scale the EMI frequency and keep the processor betweel 261MHz and 454MHz. It can still be improve. The auto-slow divisor could still be change, 8 seems reasonable for now Change-Id: I639bb3f6b7f8efedc7dc58d08127849156eeb1b6
2012-05-19imx233: move icoll stuff to its own fileAmaury Pouly1-44/+1
The icoll code now has an IRQ storm detection mechanism which will prevent the device from hard freezing in case it happen. Change-Id: I9861238dce61d29af1e48f9c534ec63a7f23465c
2012-02-05imx233: add audioin init code, add adc dma interrupts, fix register definesAmaury Pouly1-0/+2
Change-Id: I204afbd3390f8dcde6ea1315ea6aa8dde12d3749
2012-02-01imx233/fuze+: set a few recommended power bits by Freescale, remove some ↵Amaury Pouly1-3/+1
uneeded headers, implement audio path selection for playback and radio Change-Id: If926ead9b776504a58eb102fcc0e9acadf4f7379
2012-01-15imx233: add DCP driver (only memcpy implemented), move channel arbiter to ↵Amaury Pouly1-0/+3
kernel-imx233 Change-Id: I2bc5a49459c354027fc67a880bbf3b87c942bdd0
2012-01-04imx233: move dbg function declaration to system-target.hRafaël Carré1-0/+2
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-12-31firewire/usb_remove/insert_int: move to system-target.hRafaël Carré1-0/+3
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-12-26imx233: implement core_sleepAmaury Pouly1-0/+1
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-10-18imx233/fuze+: fix typo and add dac dma/error interruptsAmaury Pouly1-0/+2
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-09-14imx233/fuze+: implement usb enableAmaury Pouly1-0/+14
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-09-13imx233/fuze+: add more interrupts, rewrite block resetting, reset icoll on ↵Amaury Pouly1-0/+1
boot (useful for firmware) git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-09-05imx233:fuze+: major memory and usb reworkAmaury Pouly1-34/+2
- now identity map dram uncached and have a cached and buffered virtual alias - rework dma to handle virtual to physical pointers conversion - fix lcd frame pointer - implement usb detection properly - implement bootloader usb properly - allow the bootloader to disable MMC windowing (useful for recovery) git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-07-22imx233/fuze+: implement gpio interruptsAmaury Pouly1-0/+4
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-07-03imx233/fuze+: replace software i2c by hardware i2c, make some code more ↵Amaury Pouly1-0/+2
correct, reduce code size of lcd init sequences git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-06-30imx233/fuze+: ssp, dma, mmc now work properly, partially implement cpu ↵Amaury Pouly1-0/+41
frequency changing, implement panic waiting git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-06-17fuze+: add more clocking code, add dma code, add ssp code, add stub usb ↵Amaury Pouly1-0/+4
code, update storage to SD + MMC, beginning of the driver git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-05-04fuze+: move defines from .c to .h; implement button reading for volume ↵Amaury Pouly1-0/+27
up/down and power git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
2011-05-01Sansa Fuze+: initial commit (bootloader only, LCD basically working)Amaury Pouly1-0/+53
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657