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path: root/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
AgeCommit message (Expand)AuthorFilesLines
2020-09-06jz4760: Fix and re-enable the hardware udelay() timerSolomon Peachy1-12/+19
2020-09-05mips: Convert 'nop' to 'ssnop' -- for future-proofingSolomon Peachy1-1/+1
2020-09-03mips: Heavily rework DMA & caching codeSolomon Peachy1-2/+1
2020-09-02jz4760: Dial down PIXCLK as low as possibleSolomon Peachy1-0/+3
2020-08-30jz4760: Explicitly disable UARTs at startupSolomon Peachy1-0/+12
2020-08-30jz4760: Prioritize Audio DMA and TCU0 (systick) above all othersSolomon Peachy1-31/+13
2020-08-30jz4760: Revert back to the delay loop udelay()Solomon Peachy1-1/+1
2020-08-29jz4760: Rework IRQ priorities, make audio the highest.Solomon Peachy1-10/+29
2020-08-29jz4760: Disable dynamic clocking entirely.Solomon Peachy1-1/+1
2020-08-29jz4760: do the MSC (ie SD) clocking setup when we change PLL0Solomon Peachy1-6/+4
2020-08-28jz4760: Pull non-PLL init out of pll0_init() code.Solomon Peachy1-16/+15
2020-08-26jz4760: fix the new udelay() to use _micro_seconds, not millisecondsSolomon Peachy1-4/+6
2020-08-25jz4760: Give each SD interface its own DMA channel, semaphore, and mutexSolomon Peachy1-2/+4
2020-08-12jz4760: Use HW timer for more a more accurate udelay()Solomon Peachy1-0/+29
2020-08-07jz4760: Support dynamic reclocking!Solomon Peachy1-19/+42
2020-08-07jz4760: Fixes in PLL calculation and reportingSolomon Peachy1-12/+10
2020-08-07xduoox3: Set PLL0 to 480MHz, not 492.Solomon Peachy1-1/+1
2020-08-07jz4760: Don't enable PLL1 until we need audio.Solomon Peachy1-17/+30
2018-07-28Add cleaned-up xDuoo X3 supportSolomon Peachy1-0/+710